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Searched +full:0 +full:x4e000 (Results 1 – 21 of 21) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,q6sstopcc.yaml40 reg = <0x07500000 0x4e000>, <0x07550000 0x10000>;
/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml148 reg = <0x03c00000 0xa0000>;
156 reg = <0x30000000 0x50000>;
159 ranges = <0x0 0x30000000 0x50000>;
162 reg = <0x4e000 0x1000>;
168 reg = <0x4f000 0x1000>;
192 #size-cells = <0>;
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_9_1_sar2130p.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
[all …]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x290,
35 .base = 0x16000, .len = 0x290,
39 .base = 0x17000, .len = 0x290,
43 .base = 0x18000, .len = 0x290,
47 .base = 0x19000, .len = 0x290,
51 .base = 0x1a000, .len = 0x290,
59 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_8_4_sa8775p.h11 .max_mixer_blendstages = 0xb,
22 .base = 0x0, .len = 0x494,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_12_2_glymur.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x1000,
35 .base = 0x16000, .len = 0x1000,
39 .base = 0x17000, .len = 0x1000,
43 .base = 0x18000, .len = 0x1000,
47 .base = 0x19000, .len = 0x1000,
51 .base = 0x1a000, .len = 0x1000,
55 .base = 0x1b000, .len = 0x1000,
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
[all …]
/linux/drivers/interconnect/qcom/
H A Dsar2130p.c232 .port_offsets = { 0x9e000 },
234 .urg_fwd = 0,
249 .port_offsets = { 0x9f000 },
251 .urg_fwd = 0,
275 .port_offsets = { 0xe000, 0x4e000 },
276 .prio = 0,
277 .urg_fwd = 0,
292 .port_offsets = { 0xf000, 0x4f000 },
293 .prio = 0,
308 .port_offsets = { 0x9d000 },
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-sm6115.c50 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
63 .enable_reg = 0x79000,
64 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
97 { 0x0, 1 },
102 .offset = 0x0,
118 .l = 0x3c,
119 .vco_val = 0x1 << 20,
[all …]
H A Dgcc-sm6375.c54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
H A Dgcc-sm6125.c42 .offset = 0x0,
45 .enable_reg = 0x79000,
46 .enable_mask = BIT(0),
85 .offset = 0x3000,
88 .enable_reg = 0x79000,
102 .offset = 0x4000,
105 .enable_reg = 0x79000,
119 .offset = 0x5000,
122 .enable_reg = 0x79000,
136 .offset = 0x6000,
[all …]
H A Dgcc-msm8909.c52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
H A Dgcc-qcs404.c49 { P_XO, 0 },
68 .offset = 0x21000,
71 .enable_reg = 0x45008,
84 .offset = 0x21000,
88 .enable_reg = 0x45000,
89 .enable_mask = BIT(0),
100 .offset = 0x21000,
104 .enable_reg = 0x45000,
105 .enable_mask = BIT(0),
117 .offset = 0x20000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]