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12

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,q6sstopcc.yaml40 reg = <0x07500000 0x4e000>, <0x07550000 0x10000>;
/linux/Documentation/devicetree/bindings/pinctrl/
H A Drealtek,rtd1315e-pinctrl.yaml95 0: power supply of 1.8V
97 enum: [0, 1]
118 8 configurable levels (0 to 7), with higher values indicating
125 minimum: 0
133 minimum: 0
141 0: 0ns
147 enum: [ 0, 2, 3, 4, 5 ]
164 reg = <0x4e000 0x130>;
178 realtek,drive-strength-p = <0x2>;
179 realtek,drive-strength-n = <0x2>;
[all …]
H A Drealtek,rtd1619b-pinctrl.yaml93 0: power supply of 1.8V
95 enum: [0, 1]
116 8 configurable levels (0 to 7), with higher values indicating
123 minimum: 0
131 minimum: 0
139 0: 0ns
145 enum: [ 0, 2, 3, 4, 5 ]
162 reg = <0x4e000 0x130>;
176 realtek,drive-strength-p = <0x2>;
177 realtek,drive-strength-n = <0x2>;
[all …]
H A Drealtek,rtd1319d-pinctrl.yaml94 0: power supply of 1.8V
96 enum: [0, 1]
117 8 configurable levels (0 to 7), with higher values indicating
124 minimum: 0
132 minimum: 0
140 0: 0ns
146 enum: [ 0, 2, 3, 4, 5 ]
163 reg = <0x4e000 0x130>;
177 realtek,drive-strength-p = <0x2>;
178 realtek,drive-strength-n = <0x2>;
[all …]
/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml147 reg = <0x03c00000 0xa0000>;
155 reg = <0x30000000 0x50000>;
158 ranges = <0x0 0x30000000 0x50000>;
161 reg = <0x4e000 0x1000>;
167 reg = <0x4f000 0x1000>;
191 #size-cells = <0>;
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_7_0_sm8350.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 .base = 0x15000, .len = 0x290,
39 .base = 0x16000, .len = 0x290,
44 .base = 0x17000, .len = 0x290,
49 .base = 0x18000, .len = 0x290,
54 .base = 0x19000, .len = 0x290,
59 .base = 0x1a000, .len = 0x290,
68 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_10_0_sm8650.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
26 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
34 .base = 0x15000, .len = 0x1000,
39 .base = 0x16000, .len = 0x1000,
44 .base = 0x17000, .len = 0x1000,
49 .base = 0x18000, .len = 0x1000,
54 .base = 0x19000, .len = 0x1000,
59 .base = 0x1a000, .len = 0x1000,
68 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
34 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
[all …]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
33 .base = 0x15000, .len = 0x290,
38 .base = 0x16000, .len = 0x290,
43 .base = 0x17000, .len = 0x290,
48 .base = 0x18000, .len = 0x290,
53 .base = 0x19000, .len = 0x290,
58 .base = 0x1a000, .len = 0x290,
67 .base = 0x4000, .len = 0x344,
[all …]
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_MN_MASTER_ERR_EN_0 0x200
34 #define FABRIC_MN_MASTER_ERR_FORCE_0 0x204
35 #define FABRIC_MN_MASTER_ERR_STATUS_0 0x208
36 #define FABRIC_MN_MASTER_ERR_OVERFLOW_STATUS_0 0x20c
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-qcm2290.c46 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
61 .enable_reg = 0x79000,
62 .enable_mask = BIT(0),
75 { 0x1, 2 },
80 .offset = 0x0,
95 .offset = 0x1000,
98 .enable_reg = 0x79000,
113 .l = 0x3c,
114 .alpha = 0x0,
[all …]
H A Dgcc-sm6115.c50 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
63 .enable_reg = 0x79000,
64 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
97 { 0x0, 1 },
102 .offset = 0x0,
118 .l = 0x3c,
119 .vco_val = 0x1 << 20,
[all …]
H A Dgcc-sm6375.c54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
H A Dgcc-sm6125.c42 .offset = 0x0,
45 .enable_reg = 0x79000,
46 .enable_mask = BIT(0),
85 .offset = 0x3000,
88 .enable_reg = 0x79000,
102 .offset = 0x4000,
105 .enable_reg = 0x79000,
119 .offset = 0x5000,
122 .enable_reg = 0x79000,
136 .offset = 0x6000,
[all …]
H A Dgcc-msm8909.c52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
H A Dgcc-qcs404.c49 { P_XO, 0 },
68 .offset = 0x21000,
71 .enable_reg = 0x45008,
84 .offset = 0x21000,
88 .enable_reg = 0x45000,
89 .enable_mask = BIT(0),
100 .offset = 0x21000,
104 .enable_reg = 0x45000,
105 .enable_mask = BIT(0),
117 .offset = 0x20000,
[all …]
H A Dgcc-msm8917.c54 .offset = 0x21000,
57 .enable_reg = 0x45008,
72 .offset = 0x21000,
75 .enable_reg = 0x45000,
76 .enable_mask = BIT(0),
89 .offset = 0x21000,
102 { 700000000, 1400000000, 0 },
107 .config_ctl_val = 0x4001055b,
108 .early_output_mask = 0,
114 .offset = 0x22000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
44 reg = <0x0 0x02490000 0x0 0x10000>;
71 snps,burst-map = <0x7>;
78 reg = <0x0 0x2600000 0x0 0x210000>;
116 dma-channel-mask = <0xfffffffe>;
129 ranges = <0x02900000 0x0 0x02900000 0x200000>;
134 reg = <0x02900800 0x800>;
[all …]
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x0 0xf000>,
30 <0x0 0x0010f000 0x0 0x1000>;
36 reg = <0x0 0x2200000 0x0 0x10000>,
37 <0x0 0x2210000 0x0 0x10000>;
90 gpio-ranges = <&pinmux 0 0 169>;
95 reg = <0x0 0x02300000 0x0 0x1000>;
105 reg = <0x0 0x2390000 0x0 0x1000>,
106 <0x0 0x23a0000 0x0 0x1000>,
[all …]

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