Lines Matching +full:0 +full:x4e000
46 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
61 .enable_reg = 0x79000,
62 .enable_mask = BIT(0),
75 { 0x1, 2 },
80 .offset = 0x0,
95 .offset = 0x1000,
98 .enable_reg = 0x79000,
113 .l = 0x3c,
114 .alpha = 0x0,
115 .vco_val = 0x1 << 20,
117 .main_output_mask = BIT(0),
118 .config_ctl_val = 0x4001055B,
119 .test_ctl_hi1_val = 0x1,
123 .offset = 0xa000,
128 .enable_reg = 0x79000,
143 .l = 0x1B,
144 .alpha = 0x55555555,
145 .alpha_hi = 0xB5,
147 .vco_val = 0x2 << 20,
149 .main_output_mask = BIT(0),
150 .config_ctl_val = 0x4001055B,
151 .test_ctl_hi1_val = 0x1,
155 .offset = 0xb000,
161 .enable_reg = 0x79000,
175 .offset = 0x3000,
178 .enable_reg = 0x79000,
192 { 0x1, 2 },
197 .offset = 0x3000,
212 .offset = 0x4000,
215 .enable_reg = 0x79000,
229 .offset = 0x5000,
232 .enable_reg = 0x79000,
246 .offset = 0x6000,
249 .enable_reg = 0x79000,
263 { 0x1, 2 },
268 .offset = 0x6000,
283 .offset = 0x7000,
286 .enable_reg = 0x79000,
301 .l = 0x1B,
302 .alpha = 0x55555555,
303 .alpha_hi = 0xC5,
305 .vco_val = 0x2 << 20,
307 .main_output_mask = BIT(0),
309 .post_div_val = 0x1 << 8,
311 .config_ctl_val = 0x4001055B,
312 .test_ctl_hi1_val = 0x1,
316 .offset = 0x8000,
322 .enable_reg = 0x79000,
336 { 0x1, 2 },
341 .offset = 0x8000,
358 .l = 0x3C,
359 .alpha = 0x0,
360 .post_div_val = 0x1 << 8,
362 .main_output_mask = BIT(0),
364 .config_ctl_val = 0x00004289,
365 .test_ctl_val = 0x08000000,
369 .offset = 0x9000,
374 .enable_reg = 0x79000,
388 { 0x1, 2 },
393 .offset = 0x9000,
409 { P_BI_TCXO, 0 },
421 { P_BI_TCXO, 0 },
435 { P_BI_TCXO, 0 },
449 { P_BI_TCXO, 0 },
467 { P_BI_TCXO, 0 },
485 { P_BI_TCXO, 0 },
501 { P_BI_TCXO, 0 },
521 { P_BI_TCXO, 0 },
541 { P_BI_TCXO, 0 },
561 { P_BI_TCXO, 0 },
581 { P_BI_TCXO, 0 },
599 { P_BI_TCXO, 0 },
615 { P_BI_TCXO, 0 },
625 { P_BI_TCXO, 0 },
639 F(19200000, P_BI_TCXO, 1, 0, 0),
644 .cmd_rcgr = 0x1a034,
645 .mnd_width = 0,
658 .reg = 0x1a04c,
659 .shift = 0,
672 F(19200000, P_BI_TCXO, 1, 0, 0),
673 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
674 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
675 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
680 .cmd_rcgr = 0x5802c,
681 .mnd_width = 0,
694 F(19200000, P_BI_TCXO, 1, 0, 0),
695 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
700 .cmd_rcgr = 0x56000,
701 .mnd_width = 0,
714 F(19200000, P_BI_TCXO, 1, 0, 0),
715 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
716 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
717 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
722 .cmd_rcgr = 0x45000,
723 .mnd_width = 0,
736 .cmd_rcgr = 0x4501c,
737 .mnd_width = 0,
750 F(19200000, P_BI_TCXO, 1, 0, 0),
757 .cmd_rcgr = 0x51000,
772 .cmd_rcgr = 0x5101c,
787 .cmd_rcgr = 0x51038,
802 .cmd_rcgr = 0x51054,
817 F(19200000, P_BI_TCXO, 1, 0, 0),
818 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
819 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
824 .cmd_rcgr = 0x55024,
825 .mnd_width = 0,
838 F(19200000, P_BI_TCXO, 1, 0, 0),
839 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
840 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
841 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
842 F(580000000, P_GPLL8_OUT_EARLY, 1, 0, 0),
847 .cmd_rcgr = 0x55004,
848 .mnd_width = 0,
862 F(19200000, P_BI_TCXO, 1, 0, 0),
863 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
864 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
865 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
866 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
867 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
868 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
869 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
870 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
871 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
872 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
873 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
874 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
875 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
876 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
877 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
882 .cmd_rcgr = 0x52004,
896 F(19200000, P_BI_TCXO, 1, 0, 0),
897 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
898 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
899 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
900 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
901 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
906 .cmd_rcgr = 0x52094,
907 .mnd_width = 0,
920 .cmd_rcgr = 0x52024,
934 .cmd_rcgr = 0x520b4,
935 .mnd_width = 0,
948 F(19200000, P_BI_TCXO, 1, 0, 0),
949 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
951 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
956 .cmd_rcgr = 0x52064,
971 F(19200000, P_BI_TCXO, 1, 0, 0),
972 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
973 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
978 .cmd_rcgr = 0x58010,
979 .mnd_width = 0,
992 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
993 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
994 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
995 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
1000 .cmd_rcgr = 0x4d004,
1014 .cmd_rcgr = 0x4e004,
1028 .cmd_rcgr = 0x4f004,
1042 F(19200000, P_BI_TCXO, 1, 0, 0),
1043 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
1048 .cmd_rcgr = 0x20010,
1049 .mnd_width = 0,
1064 F(19200000, P_BI_TCXO, 1, 0, 0),
1069 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1072 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1076 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
1077 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1089 .cmd_rcgr = 0x1f148,
1105 .cmd_rcgr = 0x1f278,
1121 .cmd_rcgr = 0x1f3a8,
1137 .cmd_rcgr = 0x1f4d8,
1153 .cmd_rcgr = 0x1f608,
1169 .cmd_rcgr = 0x1f738,
1182 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1183 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1184 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1185 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1190 .cmd_rcgr = 0x38028,
1204 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1205 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1206 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1207 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1208 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1213 .cmd_rcgr = 0x38010,
1214 .mnd_width = 0,
1228 F(19200000, P_BI_TCXO, 1, 0, 0),
1229 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1230 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1231 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1232 F(202000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
1237 .cmd_rcgr = 0x1e00c,
1252 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1253 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1254 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1255 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1260 .cmd_rcgr = 0x1a01c,
1274 .cmd_rcgr = 0x1a060,
1275 .mnd_width = 0,
1288 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
1289 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
1290 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1291 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1296 .cmd_rcgr = 0x58060,
1297 .mnd_width = 0,
1311 .halt_reg = 0x1d004,
1313 .hwcg_reg = 0x1d004,
1316 .enable_reg = 0x1d004,
1317 .enable_mask = BIT(0),
1326 .halt_reg = 0x1d008,
1328 .hwcg_reg = 0x1d008,
1331 .enable_reg = 0x1d008,
1332 .enable_mask = BIT(0),
1341 .halt_reg = 0x71154,
1343 .hwcg_reg = 0x71154,
1346 .enable_reg = 0x71154,
1347 .enable_mask = BIT(0),
1356 .halt_reg = 0x23004,
1358 .hwcg_reg = 0x23004,
1361 .enable_reg = 0x79004,
1371 .halt_reg = 0x17070,
1373 .hwcg_reg = 0x17070,
1376 .enable_reg = 0x79004,
1386 .halt_reg = 0x1706c,
1388 .hwcg_reg = 0x1706c,
1391 .enable_reg = 0x79004,
1401 .halt_reg = 0x17008,
1403 .hwcg_reg = 0x17008,
1406 .enable_reg = 0x17008,
1407 .enable_mask = BIT(0),
1417 .halt_reg = 0x17028,
1420 .enable_reg = 0x17028,
1421 .enable_mask = BIT(0),
1431 .halt_reg = 0x58044,
1434 .enable_reg = 0x58044,
1435 .enable_mask = BIT(0),
1448 .halt_reg = 0x5804c,
1450 .hwcg_reg = 0x5804c,
1453 .enable_reg = 0x5804c,
1454 .enable_mask = BIT(0),
1463 .halt_reg = 0x58050,
1465 .hwcg_reg = 0x58050,
1468 .enable_reg = 0x58050,
1469 .enable_mask = BIT(0),
1478 .halt_reg = 0x56018,
1481 .enable_reg = 0x56018,
1482 .enable_mask = BIT(0),
1495 .halt_reg = 0x52088,
1498 .enable_reg = 0x52088,
1499 .enable_mask = BIT(0),
1512 .halt_reg = 0x5208c,
1515 .enable_reg = 0x5208c,
1516 .enable_mask = BIT(0),
1529 .halt_reg = 0x45018,
1532 .enable_reg = 0x45018,
1533 .enable_mask = BIT(0),
1546 .halt_reg = 0x45034,
1549 .enable_reg = 0x45034,
1550 .enable_mask = BIT(0),
1563 .halt_reg = 0x51018,
1566 .enable_reg = 0x51018,
1567 .enable_mask = BIT(0),
1580 .halt_reg = 0x51034,
1583 .enable_reg = 0x51034,
1584 .enable_mask = BIT(0),
1597 .halt_reg = 0x51050,
1600 .enable_reg = 0x51050,
1601 .enable_mask = BIT(0),
1614 .halt_reg = 0x5106c,
1617 .enable_reg = 0x5106c,
1618 .enable_mask = BIT(0),
1631 .halt_reg = 0x58054,
1634 .enable_reg = 0x58054,
1635 .enable_mask = BIT(0),
1644 .halt_reg = 0x5503c,
1647 .enable_reg = 0x5503c,
1648 .enable_mask = BIT(0),
1661 .halt_reg = 0x5501c,
1664 .enable_reg = 0x5501c,
1665 .enable_mask = BIT(0),
1678 .halt_reg = 0x5805c,
1681 .enable_reg = 0x5805c,
1682 .enable_mask = BIT(0),
1691 .halt_reg = 0x5201c,
1694 .enable_reg = 0x5201c,
1695 .enable_mask = BIT(0),
1708 .halt_reg = 0x5207c,
1711 .enable_reg = 0x5207c,
1712 .enable_mask = BIT(0),
1725 .halt_reg = 0x520ac,
1728 .enable_reg = 0x520ac,
1729 .enable_mask = BIT(0),
1742 .halt_reg = 0x5203c,
1745 .enable_reg = 0x5203c,
1746 .enable_mask = BIT(0),
1759 .halt_reg = 0x52080,
1762 .enable_reg = 0x52080,
1763 .enable_mask = BIT(0),
1776 .halt_reg = 0x520cc,
1779 .enable_reg = 0x520cc,
1780 .enable_mask = BIT(0),
1793 .halt_reg = 0x58028,
1796 .enable_reg = 0x58028,
1797 .enable_mask = BIT(0),
1810 .halt_reg = 0x1a084,
1812 .hwcg_reg = 0x1a084,
1815 .enable_reg = 0x1a084,
1816 .enable_mask = BIT(0),
1829 .halt_reg = 0x1700c,
1831 .hwcg_reg = 0x1700c,
1834 .enable_reg = 0x1700c,
1835 .enable_mask = BIT(0),
1845 .reg = 0x17058,
1846 .shift = 0,
1859 .enable_reg = 0x79004,
1873 .halt_reg = 0x17020,
1875 .hwcg_reg = 0x17020,
1878 .enable_reg = 0x17020,
1879 .enable_mask = BIT(0),
1888 .halt_reg = 0x17064,
1890 .hwcg_reg = 0x17064,
1893 .enable_reg = 0x7900c,
1903 .halt_reg = 0x1702c,
1906 .enable_reg = 0x1702c,
1907 .enable_mask = BIT(0),
1917 .halt_reg = 0x4d000,
1920 .enable_reg = 0x4d000,
1921 .enable_mask = BIT(0),
1934 .halt_reg = 0x4e000,
1937 .enable_reg = 0x4e000,
1938 .enable_mask = BIT(0),
1951 .halt_reg = 0x4f000,
1954 .enable_reg = 0x4f000,
1955 .enable_mask = BIT(0),
1968 .halt_reg = 0x36004,
1970 .hwcg_reg = 0x36004,
1973 .enable_reg = 0x36004,
1974 .enable_mask = BIT(0),
1986 .enable_reg = 0x79004,
2002 .enable_reg = 0x79004,
2016 .halt_reg = 0x36100,
2019 .enable_reg = 0x36100,
2020 .enable_mask = BIT(0),
2029 .halt_reg = 0x3600c,
2031 .hwcg_reg = 0x3600c,
2034 .enable_reg = 0x3600c,
2035 .enable_mask = BIT(0),
2044 .halt_reg = 0x36018,
2047 .enable_reg = 0x36018,
2048 .enable_mask = BIT(0),
2057 .halt_reg = 0x36048,
2059 .hwcg_reg = 0x36048,
2062 .enable_reg = 0x79004,
2073 .halt_reg = 0x2000c,
2076 .enable_reg = 0x2000c,
2077 .enable_mask = BIT(0),
2090 .halt_reg = 0x20004,
2092 .hwcg_reg = 0x20004,
2095 .enable_reg = 0x20004,
2096 .enable_mask = BIT(0),
2105 .halt_reg = 0x20008,
2108 .enable_reg = 0x20008,
2109 .enable_mask = BIT(0),
2118 .halt_reg = 0x2002c,
2121 .enable_reg = 0x2002c,
2122 .enable_mask = BIT(0),
2131 .halt_reg = 0x17014,
2133 .hwcg_reg = 0x17014,
2136 .enable_reg = 0x7900c,
2137 .enable_mask = BIT(0),
2146 .halt_reg = 0x17060,
2148 .hwcg_reg = 0x17060,
2151 .enable_reg = 0x7900c,
2161 .halt_reg = 0x17018,
2163 .hwcg_reg = 0x17018,
2166 .enable_reg = 0x7900c,
2176 .halt_reg = 0x36040,
2178 .hwcg_reg = 0x36040,
2181 .enable_reg = 0x7900c,
2191 .halt_reg = 0x17010,
2193 .hwcg_reg = 0x17010,
2196 .enable_reg = 0x79004,
2206 .halt_reg = 0x1f014,
2209 .enable_reg = 0x7900c,
2219 .halt_reg = 0x1f00c,
2222 .enable_reg = 0x7900c,
2232 .halt_reg = 0x1f144,
2235 .enable_reg = 0x7900c,
2249 .halt_reg = 0x1f274,
2252 .enable_reg = 0x7900c,
2266 .halt_reg = 0x1f3a4,
2269 .enable_reg = 0x7900c,
2283 .halt_reg = 0x1f4d4,
2286 .enable_reg = 0x7900c,
2300 .halt_reg = 0x1f604,
2303 .enable_reg = 0x7900c,
2317 .halt_reg = 0x1f734,
2320 .enable_reg = 0x7900c,
2334 .halt_reg = 0x1f004,
2336 .hwcg_reg = 0x1f004,
2339 .enable_reg = 0x7900c,
2349 .halt_reg = 0x1f008,
2351 .hwcg_reg = 0x1f008,
2354 .enable_reg = 0x7900c,
2364 .halt_reg = 0x38008,
2367 .enable_reg = 0x38008,
2368 .enable_mask = BIT(0),
2377 .halt_reg = 0x38004,
2380 .enable_reg = 0x38004,
2381 .enable_mask = BIT(0),
2394 .halt_reg = 0x3800c,
2396 .hwcg_reg = 0x3800c,
2399 .enable_reg = 0x3800c,
2400 .enable_mask = BIT(0),
2413 .halt_reg = 0x1e008,
2416 .enable_reg = 0x1e008,
2417 .enable_mask = BIT(0),
2426 .halt_reg = 0x1e004,
2429 .enable_reg = 0x1e004,
2430 .enable_mask = BIT(0),
2443 .halt_reg = 0x2b06c,
2445 .hwcg_reg = 0x2b06c,
2448 .enable_reg = 0x79004,
2449 .enable_mask = BIT(0),
2459 .halt_reg = 0x1a080,
2461 .hwcg_reg = 0x1a080,
2464 .enable_reg = 0x1a080,
2465 .enable_mask = BIT(0),
2478 .halt_reg = 0x1a010,
2481 .enable_reg = 0x1a010,
2482 .enable_mask = BIT(0),
2495 .halt_reg = 0x1a018,
2498 .enable_reg = 0x1a018,
2499 .enable_mask = BIT(0),
2512 .halt_reg = 0x1a014,
2515 .enable_reg = 0x1a014,
2516 .enable_mask = BIT(0),
2525 .halt_reg = 0x9f000,
2528 .enable_reg = 0x9f000,
2529 .enable_mask = BIT(0),
2538 .halt_reg = 0x1a054,
2541 .enable_reg = 0x1a054,
2542 .enable_mask = BIT(0),
2555 .halt_reg = 0x1a058,
2557 .hwcg_reg = 0x1a058,
2560 .enable_reg = 0x1a058,
2561 .enable_mask = BIT(0),
2570 .halt_reg = 0x6e008,
2573 .enable_reg = 0x6e008,
2574 .enable_mask = BIT(0),
2583 .halt_reg = 0x6e010,
2586 .enable_reg = 0x6e010,
2587 .enable_mask = BIT(0),
2596 .halt_reg = 0x6e004,
2599 .enable_reg = 0x6e004,
2600 .enable_mask = BIT(0),
2609 .halt_reg = 0x17004,
2611 .hwcg_reg = 0x17004,
2614 .enable_reg = 0x17004,
2615 .enable_mask = BIT(0),
2624 .halt_reg = 0x1701c,
2626 .hwcg_reg = 0x1701c,
2629 .enable_reg = 0x1701c,
2630 .enable_mask = BIT(0),
2639 .halt_reg = 0x17068,
2641 .hwcg_reg = 0x17068,
2644 .enable_reg = 0x79004,
2654 .halt_reg = 0x580a4,
2656 .hwcg_reg = 0x580a4,
2659 .enable_reg = 0x580a4,
2660 .enable_mask = BIT(0),
2673 .halt_reg = 0x5808c,
2676 .enable_reg = 0x5808c,
2677 .enable_mask = BIT(0),
2690 .halt_reg = 0x17024,
2693 .enable_reg = 0x17024,
2694 .enable_mask = BIT(0),
2703 .gdscr = 0x58004,
2711 .gdscr = 0x1a004,
2719 .gdscr = 0x58098,
2727 .gdscr = 0x5807c,
2735 .gdscr = 0x7d060,
2744 .gdscr = 0x7d07c,
2753 .gdscr = 0x7d074,
2762 .gdscr = 0x7d078,
2915 [GCC_CAMSS_OPE_BCR] = { 0x55000 },
2916 [GCC_CAMSS_TFE_BCR] = { 0x52000 },
2917 [GCC_CAMSS_TOP_BCR] = { 0x58000 },
2918 [GCC_GPU_BCR] = { 0x36000 },
2919 [GCC_MMSS_BCR] = { 0x17000 },
2920 [GCC_PDM_BCR] = { 0x20000 },
2921 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x1f000 },
2922 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
2923 [GCC_SDCC1_BCR] = { 0x38000 },
2924 [GCC_SDCC2_BCR] = { 0x1e000 },
2925 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
2926 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
2927 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
2928 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
2929 [GCC_VCODEC0_BCR] = { 0x58094 },
2930 [GCC_VENUS_BCR] = { 0x58078 },
2931 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
2958 .max_register = 0xc7000,