Lines Matching +full:0 +full:x4e000
56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
91 .n_reg = 0x4a00c,
92 .config_reg = 0x4a014,
93 .mode_reg = 0x4a000,
94 .status_reg = 0x4a01c,
107 .enable_reg = 0x45000,
120 { 1100000000, 57, 7, 24, 0 },
125 .l_reg = 0x22004,
126 .m_reg = 0x22008,
127 .n_reg = 0x2200c,
128 .config_reg = 0x22010,
129 .mode_reg = 0x22000,
130 .status_reg = 0x22024,
144 .enable_reg = 0x45000,
161 .vco_val = 0x0,
162 .vco_mask = 0x3 << 20,
163 .pre_div_val = 0x0,
164 .pre_div_mask = 0x7 << 12,
165 .post_div_val = 0x0,
166 .post_div_mask = 0x3 << 8,
168 .main_output_mask = BIT(0),
173 .l_reg = 0x24004,
174 .m_reg = 0x24008,
175 .n_reg = 0x2400c,
176 .config_reg = 0x24018,
177 .mode_reg = 0x24000,
178 .status_reg = 0x24024,
191 .enable_reg = 0x45000,
204 .mode_reg = 0x37000,
205 .l_reg = 0x37004,
206 .m_reg = 0x37008,
207 .n_reg = 0x3700c,
208 .config_reg = 0x37014,
209 .status_reg = 0x3701c,
222 .enable_reg = 0x45000,
235 { P_XO, 0 },
247 { P_XO, 0 },
259 { P_XO, 0 },
273 { P_XO, 0 },
287 { P_XO, 0 },
292 { P_XO, 0 },
297 { P_XO, 0 },
309 { P_XO, 0 },
321 { P_XO, 0 },
343 { P_XO, 0 },
353 { P_XO_A, 0 },
371 { P_XO, 0 },
381 { P_XO, 0 },
389 { P_XO, 0 },
394 { P_XO, 0 },
399 { P_XO, 0 },
405 { P_XO, 0 },
415 { P_XO, 0 },
427 { P_XO, 0 },
437 { P_XO, 0 },
449 { P_XO, 0 },
463 F(19200000, P_XO, 1, 0, 0),
464 F(300000000, P_GPLL4_OUT, 4, 0, 0),
465 F(540000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
470 .cmd_rcgr = 0x78008,
483 F(19200000, P_XO, 1, 0, 0),
484 F(300000000, P_GPLL4_OUT, 4, 0, 0),
485 F(540000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
490 .cmd_rcgr = 0x79008,
503 F(19200000, P_XO_A, 1, 0, 0),
504 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
505 F(88890000, P_GPLL0_OUT_MAIN, 9, 0, 0),
506 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
511 .cmd_rcgr = 0x46000,
530 F(19200000, P_XO, 1, 0, 0),
531 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
536 .cmd_rcgr = 0x200c,
550 F(4800000, P_XO, 4, 0, 0),
551 F(9600000, P_XO, 2, 0, 0),
553 F(19200000, P_XO, 1, 0, 0),
555 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
560 .cmd_rcgr = 0x2024,
574 .cmd_rcgr = 0x3000,
587 .cmd_rcgr = 0x3014,
601 .cmd_rcgr = 0x4000,
614 .cmd_rcgr = 0x4024,
628 .cmd_rcgr = 0x5000,
641 .cmd_rcgr = 0x5024,
659 F(19200000, P_XO, 1, 0, 0),
675 .cmd_rcgr = 0x2044,
689 .cmd_rcgr = 0x3034,
703 .cmd_rcgr = 0xc00c,
716 .cmd_rcgr = 0xc024,
730 .cmd_rcgr = 0xd000,
743 .cmd_rcgr = 0xd014,
757 .cmd_rcgr = 0xf000,
770 .cmd_rcgr = 0xf024,
784 .cmd_rcgr = 0x18000,
797 .cmd_rcgr = 0x18024,
811 .cmd_rcgr = 0xc044,
825 .cmd_rcgr = 0xd034,
839 F(19200000, P_XO, 1, 0, 0),
845 .cmd_rcgr = 0x51000,
859 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
860 F(240000000, P_GPLL4_AUX, 5, 0, 0),
861 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
862 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
863 F(480000000, P_GPLL4_AUX, 2.5, 0, 0),
868 .cmd_rcgr = 0x58018,
881 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
882 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
883 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
888 .cmd_rcgr = 0x4e020,
901 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
902 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
903 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
908 .cmd_rcgr = 0x4f020,
921 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
922 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
923 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
928 .cmd_rcgr = 0x3c020,
941 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
942 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
943 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
948 .cmd_rcgr = 0x54000,
962 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
963 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
964 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
969 .cmd_rcgr = 0x55000,
983 F(133330000, P_GPLL0_OUT_MAIN, 6, 0, 0),
984 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
985 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
986 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
991 .cmd_rcgr = 0x57000,
1006 F(66670000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1011 .cmd_rcgr = 0x52000,
1025 .cmd_rcgr = 0x53000,
1039 .cmd_rcgr = 0x5c000,
1053 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1054 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1055 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1060 .cmd_rcgr = 0x4e000,
1073 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1074 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1075 F(266670000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1080 .cmd_rcgr = 0x4f000,
1094 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1099 .cmd_rcgr = 0x5a000,
1113 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1114 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1115 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1116 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1117 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1118 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1119 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1120 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1121 F(300000000, P_GPLL4_OUT, 4, 0, 0),
1122 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1123 F(466000000, P_GPLL2_AUX, 2, 0, 0),
1128 .cmd_rcgr = 0x58000,
1141 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1142 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1143 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1144 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1145 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1146 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1147 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1148 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1149 F(300000000, P_GPLL4_OUT, 4, 0, 0),
1150 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1151 F(466000000, P_GPLL2_AUX, 2, 0, 0),
1156 .cmd_rcgr = 0x58054,
1169 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1170 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1171 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1172 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1177 .cmd_rcgr = 0x16004,
1190 F(19200000, P_XO, 1, 0, 0),
1195 .cmd_rcgr = 0x8004,
1211 F(19200000, P_XO, 1, 0, 0),
1216 .cmd_rcgr = 0x9004,
1232 F(19200000, P_XO, 1, 0, 0),
1237 .cmd_rcgr = 0xa004,
1253 .cmd_rcgr = 0x4d044,
1254 .mnd_width = 0,
1267 .cmd_rcgr = 0x4d0b0,
1268 .mnd_width = 0,
1281 F(19200000, P_XO, 1, 0, 0),
1286 .cmd_rcgr = 0x4d05c,
1299 .cmd_rcgr = 0x4d0a8,
1312 F(50000000, P_GPLL0_OUT_MDP, 16, 0, 0),
1313 F(80000000, P_GPLL0_OUT_MDP, 10, 0, 0),
1314 F(100000000, P_GPLL0_OUT_MDP, 8, 0, 0),
1315 F(145454545, P_GPLL0_OUT_MDP, 5.5, 0, 0),
1316 F(160000000, P_GPLL0_OUT_MDP, 5, 0, 0),
1317 F(177777778, P_GPLL0_OUT_MDP, 4.5, 0, 0),
1318 F(200000000, P_GPLL0_OUT_MDP, 4, 0, 0),
1319 F(270000000, P_GPLL6_OUT, 4, 0, 0),
1320 F(320000000, P_GPLL0_OUT_MDP, 2.5, 0, 0),
1321 F(360000000, P_GPLL6_OUT, 3, 0, 0),
1326 .cmd_rcgr = 0x4d014,
1339 .cmd_rcgr = 0x4d000,
1353 .cmd_rcgr = 0x4d0b8,
1367 F(19200000, P_XO, 1, 0, 0),
1372 .cmd_rcgr = 0x4d02c,
1385 F(19200000, P_XO, 1, 0, 0),
1386 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1387 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1388 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1389 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1390 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1391 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1392 F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
1393 F(240000000, P_GPLL6_GFX3D, 4.5, 0, 0),
1394 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1395 F(300000000, P_GPLL4_GFX3D, 4, 0, 0),
1396 F(360000000, P_GPLL6_GFX3D, 3, 0, 0),
1397 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1398 F(432000000, P_GPLL6_GFX3D, 2.5, 0, 0),
1399 F(480000000, P_GPLL4_GFX3D, 2.5, 0, 0),
1400 F(540000000, P_GPLL6_GFX3D, 2, 0, 0),
1401 F(600000000, P_GPLL4_GFX3D, 2, 0, 0),
1413 .cmd_rcgr = 0x59000,
1421 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
1426 .cmd_rcgr = 0x44010,
1439 F(19200000, P_XO, 1, 0, 0),
1440 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1445 .cmd_rcgr = 0x3a00c,
1462 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1463 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1464 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1465 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1466 F(342850000, P_GPLL4_OUT, 3.5, 0, 0),
1467 F(400000000, P_GPLL4_OUT, 3, 0, 0),
1476 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1477 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1478 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1479 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1480 F(186400000, P_GPLL2_OUT, 5, 0, 0),
1481 F(372800000, P_GPLL2_OUT, 2.5, 0, 0),
1493 .cmd_rcgr = 0x42004,
1507 F(100000000, P_GPLL0_OUT_M, 8, 0, 0),
1508 F(200000000, P_GPLL0_OUT_M, 4, 0, 0),
1513 .cmd_rcgr = 0x5d000,
1532 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1533 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1534 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1535 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1536 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1541 .cmd_rcgr = 0x43004,
1555 .cmd_rcgr = 0x39004,
1574 .cmd_rcgr = 0x3f034,
1588 F(64000000, P_GPLL0_OUT, 12.5, 0, 0),
1593 .cmd_rcgr = 0x3f010,
1607 F(57140000, P_GPLL0_OUT_MAIN, 14, 0, 0),
1608 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1609 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1610 F(177780000, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1615 .cmd_rcgr = 0x41010,
1628 F(72727200, P_GPLL0_OUT_MAIN, 11, 0, 0),
1629 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1630 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1631 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1632 F(228570000, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
1633 F(310667000, P_GPLL2_AUX, 3, 0, 0),
1634 F(360000000, P_GPLL6_AUX, 3, 0, 0),
1635 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
1636 F(466000000, P_GPLL2_AUX, 2, 0, 0),
1641 .cmd_rcgr = 0x4c000,
1655 .halt_reg = 0x78004,
1657 .enable_reg = 0x78004,
1658 .enable_mask = BIT(0),
1672 .halt_reg = 0x79004,
1674 .enable_reg = 0x79004,
1675 .enable_mask = BIT(0),
1689 .halt_reg = 0x2008,
1692 .enable_reg = 0x2008,
1693 .enable_mask = BIT(0),
1707 .halt_reg = 0x2004,
1710 .enable_reg = 0x2004,
1711 .enable_mask = BIT(0),
1725 .halt_reg = 0x3010,
1728 .enable_reg = 0x3010,
1729 .enable_mask = BIT(0),
1743 .halt_reg = 0x300c,
1746 .enable_reg = 0x300c,
1747 .enable_mask = BIT(0),
1761 .halt_reg = 0x4020,
1764 .enable_reg = 0x4020,
1765 .enable_mask = BIT(0),
1779 .halt_reg = 0x401c,
1782 .enable_reg = 0x401c,
1783 .enable_mask = BIT(0),
1797 .halt_reg = 0x5020,
1800 .enable_reg = 0x5020,
1801 .enable_mask = BIT(0),
1815 .halt_reg = 0x501c,
1818 .enable_reg = 0x501c,
1819 .enable_mask = BIT(0),
1833 .halt_reg = 0x203c,
1836 .enable_reg = 0x203c,
1837 .enable_mask = BIT(0),
1851 .halt_reg = 0x302c,
1854 .enable_reg = 0x302c,
1855 .enable_mask = BIT(0),
1869 .halt_reg = 0xc008,
1872 .enable_reg = 0xc008,
1873 .enable_mask = BIT(0),
1887 .halt_reg = 0xc004,
1890 .enable_reg = 0xc004,
1891 .enable_mask = BIT(0),
1905 .halt_reg = 0xd010,
1908 .enable_reg = 0xd010,
1909 .enable_mask = BIT(0),
1923 .halt_reg = 0xd00c,
1926 .enable_reg = 0xd00c,
1927 .enable_mask = BIT(0),
1941 .halt_reg = 0xf020,
1944 .enable_reg = 0xf020,
1945 .enable_mask = BIT(0),
1959 .halt_reg = 0xf01c,
1962 .enable_reg = 0xf01c,
1963 .enable_mask = BIT(0),
1977 .halt_reg = 0x18020,
1980 .enable_reg = 0x18020,
1981 .enable_mask = BIT(0),
1995 .halt_reg = 0x1801c,
1998 .enable_reg = 0x1801c,
1999 .enable_mask = BIT(0),
2013 .halt_reg = 0xc03c,
2016 .enable_reg = 0xc03c,
2017 .enable_mask = BIT(0),
2031 .halt_reg = 0xd02c,
2034 .enable_reg = 0xd02c,
2035 .enable_mask = BIT(0),
2049 .halt_reg = 0x5101c,
2051 .enable_reg = 0x5101c,
2052 .enable_mask = BIT(0),
2066 .halt_reg = 0x51018,
2068 .enable_reg = 0x51018,
2069 .enable_mask = BIT(0),
2083 .halt_reg = 0x58040,
2085 .enable_reg = 0x58040,
2086 .enable_mask = BIT(0),
2100 .halt_reg = 0x58064,
2102 .enable_reg = 0x58064,
2103 .enable_mask = BIT(0),
2112 .halt_reg = 0x5803c,
2114 .enable_reg = 0x5803c,
2115 .enable_mask = BIT(0),
2129 .halt_reg = 0x4e040,
2131 .enable_reg = 0x4e040,
2132 .enable_mask = BIT(0),
2146 .halt_reg = 0x4e03c,
2148 .enable_reg = 0x4e03c,
2149 .enable_mask = BIT(0),
2163 .halt_reg = 0x4e048,
2165 .enable_reg = 0x4e048,
2166 .enable_mask = BIT(0),
2180 .halt_reg = 0x4e058,
2182 .enable_reg = 0x4e058,
2183 .enable_mask = BIT(0),
2197 .halt_reg = 0x4e050,
2199 .enable_reg = 0x4e050,
2200 .enable_mask = BIT(0),
2214 .halt_reg = 0x4f040,
2216 .enable_reg = 0x4f040,
2217 .enable_mask = BIT(0),
2231 .halt_reg = 0x4f03c,
2233 .enable_reg = 0x4f03c,
2234 .enable_mask = BIT(0),
2248 .halt_reg = 0x4f048,
2250 .enable_reg = 0x4f048,
2251 .enable_mask = BIT(0),
2265 .halt_reg = 0x4f058,
2267 .enable_reg = 0x4f058,
2268 .enable_mask = BIT(0),
2282 .halt_reg = 0x4f050,
2284 .enable_reg = 0x4f050,
2285 .enable_mask = BIT(0),
2299 .halt_reg = 0x3c040,
2301 .enable_reg = 0x3c040,
2302 .enable_mask = BIT(0),
2316 .halt_reg = 0x3c03c,
2318 .enable_reg = 0x3c03c,
2319 .enable_mask = BIT(0),
2333 .halt_reg = 0x3c048,
2335 .enable_reg = 0x3c048,
2336 .enable_mask = BIT(0),
2350 .halt_reg = 0x3c058,
2352 .enable_reg = 0x3c058,
2353 .enable_mask = BIT(0),
2367 .halt_reg = 0x3c050,
2369 .enable_reg = 0x3c050,
2370 .enable_mask = BIT(0),
2384 .halt_reg = 0x58050,
2386 .enable_reg = 0x58050,
2387 .enable_mask = BIT(0),
2401 .halt_reg = 0x58074,
2403 .enable_reg = 0x58074,
2404 .enable_mask = BIT(0),
2418 .halt_reg = 0x54018,
2420 .enable_reg = 0x54018,
2421 .enable_mask = BIT(0),
2435 .halt_reg = 0x55018,
2437 .enable_reg = 0x55018,
2438 .enable_mask = BIT(0),
2452 .halt_reg = 0x50004,
2454 .enable_reg = 0x50004,
2455 .enable_mask = BIT(0),
2469 .halt_reg = 0x57020,
2472 .enable_reg = 0x57020,
2473 .enable_mask = BIT(0),
2487 .halt_reg = 0x57024,
2489 .enable_reg = 0x57024,
2490 .enable_mask = BIT(0),
2504 .halt_reg = 0x57028,
2506 .enable_reg = 0x57028,
2507 .enable_mask = BIT(0),
2516 .halt_reg = 0x52018,
2518 .enable_reg = 0x52018,
2519 .enable_mask = BIT(0),
2533 .halt_reg = 0x53018,
2535 .enable_reg = 0x53018,
2536 .enable_mask = BIT(0),
2550 .halt_reg = 0x5c018,
2552 .enable_reg = 0x5c018,
2553 .enable_mask = BIT(0),
2566 .halt_reg = 0x5600c,
2568 .enable_reg = 0x5600c,
2569 .enable_mask = BIT(0),
2583 .halt_reg = 0x4e01c,
2585 .enable_reg = 0x4e01c,
2586 .enable_mask = BIT(0),
2600 .halt_reg = 0x4f01c,
2602 .enable_reg = 0x4f01c,
2603 .enable_mask = BIT(0),
2617 .halt_reg = 0x56004,
2619 .enable_reg = 0x56004,
2620 .enable_mask = BIT(0),
2629 .halt_reg = 0x5a014,
2631 .enable_reg = 0x5a014,
2632 .enable_mask = BIT(0),
2646 .halt_reg = 0x58038,
2648 .enable_reg = 0x58038,
2649 .enable_mask = BIT(0),
2663 .halt_reg = 0x58044,
2665 .enable_reg = 0x58044,
2666 .enable_mask = BIT(0),
2680 .halt_reg = 0x58048,
2682 .enable_reg = 0x58048,
2683 .enable_mask = BIT(0),
2692 .halt_reg = 0x58060,
2694 .enable_reg = 0x58060,
2695 .enable_mask = BIT(0),
2709 .halt_reg = 0x58068,
2711 .enable_reg = 0x58068,
2712 .enable_mask = BIT(0),
2721 .halt_reg = 0x5805c,
2723 .enable_reg = 0x5805c,
2724 .enable_mask = BIT(0),
2738 .halt_reg = 0x77004,
2740 .enable_reg = 0x77004,
2741 .enable_mask = BIT(0),
2750 .halt_reg = 0x59024,
2752 .enable_reg = 0x59024,
2753 .enable_mask = BIT(0),
2767 .halt_reg = 0x8000,
2770 .enable_reg = 0x8000,
2771 .enable_mask = BIT(0),
2785 .halt_reg = 0x9000,
2788 .enable_reg = 0x9000,
2789 .enable_mask = BIT(0),
2803 .halt_reg = 0xa000,
2806 .enable_reg = 0xa000,
2807 .enable_mask = BIT(0),
2821 .halt_reg = 0x4d07c,
2824 .enable_reg = 0x4d07c,
2825 .enable_mask = BIT(0),
2834 .halt_reg = 0x4d080,
2837 .enable_reg = 0x4d080,
2838 .enable_mask = BIT(0),
2847 .halt_reg = 0x4d094,
2850 .enable_reg = 0x4d094,
2851 .enable_mask = BIT(0),
2865 .halt_reg = 0x4d0a0,
2868 .enable_reg = 0x4d0a0,
2869 .enable_mask = BIT(0),
2883 .halt_reg = 0x4d098,
2886 .enable_reg = 0x4d098,
2887 .enable_mask = BIT(0),
2901 .halt_reg = 0x4d09c,
2904 .enable_reg = 0x4d09c,
2905 .enable_mask = BIT(0),
2919 .halt_reg = 0x4d088,
2922 .enable_reg = 0x4d088,
2923 .enable_mask = BIT(0),
2937 .halt_reg = 0x4d084,
2940 .enable_reg = 0x4d084,
2941 .enable_mask = BIT(0),
2955 .halt_reg = 0x4d0a4,
2958 .enable_reg = 0x4d0a4,
2959 .enable_mask = BIT(0),
2973 .halt_reg = 0x4d090,
2976 .enable_reg = 0x4d090,
2977 .enable_mask = BIT(0),
2991 .halt_reg = 0x49000,
2993 .enable_reg = 0x49000,
2994 .enable_mask = BIT(0),
3003 .halt_reg = 0x49004,
3006 .enable_reg = 0x49004,
3007 .enable_mask = BIT(0),
3016 .halt_reg = 0x59048,
3018 .enable_reg = 0x59048,
3019 .enable_mask = BIT(0),
3028 .halt_reg = 0x59028,
3030 .enable_reg = 0x59028,
3031 .enable_mask = BIT(0),
3040 .halt_reg = 0x59044,
3042 .enable_reg = 0x59044,
3043 .enable_mask = BIT(0),
3057 .halt_reg = 0x59020,
3059 .enable_reg = 0x59020,
3060 .enable_mask = BIT(0),
3074 .halt_reg = 0x59040,
3076 .enable_reg = 0x59040,
3077 .enable_mask = BIT(0),
3090 .halt_reg = 0x4400c,
3093 .enable_reg = 0x4400c,
3094 .enable_mask = BIT(0),
3108 .halt_reg = 0x44004,
3111 .enable_reg = 0x44004,
3112 .enable_mask = BIT(0),
3121 .halt_reg = 0x3a008,
3123 .enable_reg = 0x3a008,
3124 .enable_mask = BIT(0),
3133 .halt_reg = 0x3a004,
3135 .enable_reg = 0x3a004,
3136 .enable_mask = BIT(0),
3150 .halt_reg = 0x4201c,
3153 .enable_reg = 0x4201c,
3154 .enable_mask = BIT(0),
3163 .halt_reg = 0x42018,
3166 .enable_reg = 0x42018,
3167 .enable_mask = BIT(0),
3181 .halt_reg = 0x5d014,
3184 .enable_reg = 0x5d014,
3185 .enable_mask = BIT(0),
3199 .halt_reg = 0x4301c,
3202 .enable_reg = 0x4301c,
3203 .enable_mask = BIT(0),
3212 .halt_reg = 0x43018,
3215 .enable_reg = 0x43018,
3216 .enable_mask = BIT(0),
3230 .halt_reg = 0x3901c,
3233 .enable_reg = 0x3901c,
3234 .enable_mask = BIT(0),
3243 .halt_reg = 0x39018,
3246 .enable_reg = 0x39018,
3247 .enable_mask = BIT(0),
3261 .halt_reg = 0x4102c,
3263 .enable_reg = 0x4102c,
3264 .enable_mask = BIT(0),
3273 .halt_reg = 0x41030,
3275 .enable_reg = 0x41030,
3276 .enable_mask = BIT(0),
3285 .halt_reg = 0x3f008,
3287 .enable_reg = 0x3f008,
3288 .enable_mask = BIT(0),
3297 .halt_reg = 0x3f030,
3299 .enable_reg = 0x3f030,
3300 .enable_mask = BIT(0),
3314 .halt_reg = 0x3f004,
3316 .enable_reg = 0x3f004,
3317 .enable_mask = BIT(0),
3331 .halt_reg = 0x41008,
3333 .enable_reg = 0x41008,
3334 .enable_mask = BIT(0),
3343 .halt_reg = 0x41004,
3345 .enable_reg = 0x41004,
3346 .enable_mask = BIT(0),
3360 .halt_reg = 0x4c020,
3362 .enable_reg = 0x4c020,
3363 .enable_mask = BIT(0),
3372 .halt_reg = 0x4c024,
3374 .enable_reg = 0x4c024,
3375 .enable_mask = BIT(0),
3384 .halt_reg = 0x4c02c,
3386 .enable_reg = 0x4c02c,
3387 .enable_mask = BIT(0),
3401 .halt_reg = 0x4c034,
3403 .enable_reg = 0x4c034,
3404 .enable_mask = BIT(0),
3418 .halt_reg = 0x4c01c,
3420 .enable_reg = 0x4c01c,
3421 .enable_mask = BIT(0),
3436 .halt_reg = 0x4601c,
3439 .enable_reg = 0x45004,
3449 .halt_reg = 0x46020,
3452 .enable_reg = 0x45004,
3462 .halt_reg = 0x1008,
3465 .enable_reg = 0x45004,
3475 .halt_reg = 0xb008,
3478 .enable_reg = 0x45004,
3488 .halt_reg = 0x13004,
3491 .enable_reg = 0x45004,
3501 .halt_reg = 0x1300c,
3504 .enable_reg = 0x45004,
3514 .halt_reg = 0x16024,
3517 .enable_reg = 0x45004,
3518 .enable_mask = BIT(0),
3527 .halt_reg = 0x16020,
3530 .enable_reg = 0x45004,
3540 .halt_reg = 0x1601c,
3543 .enable_reg = 0x45004,
3558 .halt_reg = 0x12040,
3561 .enable_reg = 0x4500c,
3571 .halt_reg = 0x12098,
3574 .enable_reg = 0x4500c,
3584 .halt_reg = 0x12010,
3587 .enable_reg = 0x4500c,
3597 .halt_reg = 0x12020,
3600 .enable_reg = 0x4500c,
3610 .halt_reg = 0x12018,
3613 .enable_reg = 0x4500c,
3623 .halt_reg = 0x12044,
3626 .enable_reg = 0x4500c,
3636 .halt_reg = 0x12034,
3639 .enable_reg = 0x4500c,
3649 .halt_reg = 0x1204c,
3652 .enable_reg = 0x4500c,
3662 .halt_reg = 0x1201c,
3665 .enable_reg = 0x4500c,
3675 .halt_reg = 0x12038,
3678 .enable_reg = 0x4500c,
3688 .halt_reg = 0x1209c,
3691 .enable_reg = 0x4500c,
3701 .halt_reg = 0x12014,
3704 .enable_reg = 0x4500c,
3714 .halt_reg = 0x12090,
3717 .enable_reg = 0x4500c,
3727 .halt_reg = 0x1203c,
3730 .enable_reg = 0x4500c,
3740 .gdscr = 0x4c018,
3741 .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
3750 .gdscr = 0x4c028,
3751 .cxcs = (unsigned int []){ 0x4c02c },
3760 .gdscr = 0x4c030,
3768 .gdscr = 0x4d078,
3769 .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
3778 .gdscr = 0x5701c,
3779 .cxcs = (unsigned int []){ 0x57020, 0x57028 },
3788 .gdscr = 0x58034,
3789 .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3798 .gdscr = 0x5806c,
3799 .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3808 .gdscr = 0x58078,
3809 .cxcs = (unsigned int []){ 0x5803c, 0x58064 },
3818 .gdscr = 0x5904c,
3819 .cxcs = (unsigned int []){ 0x59020 },
3829 .gdscr = 0x5901c,
3830 .clamp_io_ctrl = 0x5b00c,
3831 .cxcs = (unsigned int []){ 0x59000, 0x59024 },
4049 [RST_CAMSS_MICRO_BCR] = { 0x56008 },
4050 [RST_USB_HS_BCR] = { 0x41000 },
4051 [RST_QUSB2_PHY_BCR] = { 0x4103c },
4052 [RST_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
4053 [RST_USB_HS_PHY_CFG_AHB_BCR] = { 0x41038 },
4054 [RST_USB_FS_BCR] = { 0x3f000 },
4055 [RST_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
4056 [RST_CAMSS_CSI_VFE1_BCR] = { 0x58070 },
4057 [RST_CAMSS_VFE1_BCR] = { 0x5807c },
4058 [RST_CAMSS_CPP_BCR] = { 0x58080 },
4059 [RST_MSS_BCR] = { 0x71000 },
4079 .max_register = 0x7fffc,
4115 /* Set Sleep and Wakeup cycles to 0 for GMEM clock */ in gcc_msm8976_probe()
4116 ret = regmap_update_bits(regmap, gcc_oxili_gmem_clk.clkr.enable_reg, 0xff0, 0); in gcc_msm8976_probe()
4123 ret = regmap_update_bits(regmap, 0x60000, BIT(2), BIT(2)); in gcc_msm8976_probe()
4127 /* Set Sleep cycles to 0 for OXILI clock */ in gcc_msm8976_probe()
4128 ret = regmap_update_bits(regmap, gcc_oxili_gfx3d_clk.clkr.enable_reg, 0xf0, 0); in gcc_msm8976_probe()