Lines Matching +full:0 +full:x4e000
50 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
63 .enable_reg = 0x79000,
64 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
97 { 0x0, 1 },
102 .offset = 0x0,
118 .l = 0x3c,
119 .vco_val = 0x1 << 20,
121 .main_output_mask = BIT(0),
122 .config_ctl_val = 0x4001055b,
123 .test_ctl_hi1_val = 0x1,
124 .test_ctl_hi_mask = 0x1,
128 .offset = 0xa000,
133 .enable_reg = 0x79000,
147 { 0x0, 1 },
152 .offset = 0xa000,
169 .l = 0x1F,
170 .alpha = 0x0,
171 .alpha_hi = 0x40,
173 .vco_val = 0x2 << 20,
175 .config_ctl_val = 0x4001055b,
176 .test_ctl_hi1_val = 0x1,
177 .test_ctl_hi_mask = 0x1,
181 .offset = 0xb000,
187 .enable_reg = 0x79000,
201 { 0x0, 1 },
206 .offset = 0xb000,
222 .offset = 0x3000,
227 .enable_reg = 0x79000,
241 .offset = 0x4000,
246 .enable_reg = 0x79000,
260 { 0x0, 1 },
265 .offset = 0x4000,
280 .offset = 0x6000,
285 .enable_reg = 0x79000,
299 { 0x1, 2 },
304 .offset = 0x6000,
319 .offset = 0x7000,
324 .enable_reg = 0x79000,
338 { 0x0, 1 },
343 .offset = 0x7000,
359 .l = 0x29,
360 .alpha = 0xAAAAAAAA,
361 .alpha_hi = 0xAA,
363 .vco_val = 0x2 << 20,
365 .main_output_mask = BIT(0),
367 .post_div_val = 0x1 << 8,
369 .config_ctl_val = 0x4001055b,
370 .test_ctl_hi1_val = 0x1,
371 .test_ctl_hi_mask = 0x1,
375 .offset = 0x8000,
381 .enable_reg = 0x79000,
395 { 0x1, 2 },
400 .offset = 0x8000,
417 .l = 0x3C,
418 .alpha = 0x0,
419 .post_div_val = 0x1 << 8,
421 .main_output_mask = BIT(0),
422 .config_ctl_val = 0x00004289,
423 .test_ctl_mask = GENMASK(31, 0),
424 .test_ctl_val = 0x08000000,
428 .offset = 0x9000,
433 .enable_reg = 0x79000,
447 { 0x1, 2 },
452 .offset = 0x9000,
468 { P_BI_TCXO, 0 },
480 { P_BI_TCXO, 0 },
494 { P_BI_TCXO, 0 },
508 { P_BI_TCXO, 0 },
524 { P_BI_TCXO, 0 },
538 { P_BI_TCXO, 0 },
556 { P_BI_TCXO, 0 },
576 { P_BI_TCXO, 0 },
594 { P_BI_TCXO, 0 },
614 { P_BI_TCXO, 0 },
634 { P_BI_TCXO, 0 },
652 { P_BI_TCXO, 0 },
668 { P_BI_TCXO, 0 },
678 { P_BI_TCXO, 0 },
688 F(19200000, P_BI_TCXO, 1, 0, 0),
689 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
690 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
691 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
696 .cmd_rcgr = 0x5802c,
697 .mnd_width = 0,
711 F(19200000, P_BI_TCXO, 1, 0, 0),
712 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
717 .cmd_rcgr = 0x56000,
718 .mnd_width = 0,
732 F(19200000, P_BI_TCXO, 1, 0, 0),
733 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
734 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
735 F(268800000, P_GPLL4_OUT_MAIN, 3, 0, 0),
740 .cmd_rcgr = 0x59000,
741 .mnd_width = 0,
755 .cmd_rcgr = 0x5901c,
756 .mnd_width = 0,
770 .cmd_rcgr = 0x59038,
771 .mnd_width = 0,
785 F(19200000, P_BI_TCXO, 1, 0, 0),
792 .cmd_rcgr = 0x51000,
807 .cmd_rcgr = 0x5101c,
822 .cmd_rcgr = 0x51038,
837 .cmd_rcgr = 0x51054,
852 F(19200000, P_BI_TCXO, 1, 0, 0),
853 F(171428571, P_GPLL0_OUT_EARLY, 3.5, 0, 0),
854 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
859 .cmd_rcgr = 0x55024,
860 .mnd_width = 0,
874 F(19200000, P_BI_TCXO, 1, 0, 0),
875 F(200000000, P_GPLL8_OUT_MAIN, 2, 0, 0),
876 F(266600000, P_GPLL8_OUT_MAIN, 1, 0, 0),
877 F(465000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
878 F(576000000, P_GPLL9_OUT_MAIN, 1, 0, 0),
883 .cmd_rcgr = 0x55004,
884 .mnd_width = 0,
898 F(19200000, P_BI_TCXO, 1, 0, 0),
899 F(128000000, P_GPLL10_OUT_MAIN, 9, 0, 0),
900 F(135529412, P_GPLL10_OUT_MAIN, 8.5, 0, 0),
901 F(144000000, P_GPLL10_OUT_MAIN, 8, 0, 0),
902 F(153600000, P_GPLL10_OUT_MAIN, 7.5, 0, 0),
903 F(164571429, P_GPLL10_OUT_MAIN, 7, 0, 0),
904 F(177230769, P_GPLL10_OUT_MAIN, 6.5, 0, 0),
905 F(192000000, P_GPLL10_OUT_MAIN, 6, 0, 0),
906 F(209454545, P_GPLL10_OUT_MAIN, 5.5, 0, 0),
907 F(230400000, P_GPLL10_OUT_MAIN, 5, 0, 0),
908 F(256000000, P_GPLL10_OUT_MAIN, 4.5, 0, 0),
909 F(288000000, P_GPLL10_OUT_MAIN, 4, 0, 0),
910 F(329142857, P_GPLL10_OUT_MAIN, 3.5, 0, 0),
911 F(384000000, P_GPLL10_OUT_MAIN, 3, 0, 0),
912 F(460800000, P_GPLL10_OUT_MAIN, 2.5, 0, 0),
913 F(576000000, P_GPLL10_OUT_MAIN, 2, 0, 0),
918 .cmd_rcgr = 0x52004,
933 F(19200000, P_BI_TCXO, 1, 0, 0),
934 F(120000000, P_GPLL0_OUT_EARLY, 5, 0, 0),
935 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
936 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
937 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
938 F(426400000, P_GPLL3_OUT_EARLY, 2.5, 0, 0),
943 .cmd_rcgr = 0x52094,
944 .mnd_width = 0,
958 .cmd_rcgr = 0x52024,
973 .cmd_rcgr = 0x520b4,
974 .mnd_width = 0,
988 .cmd_rcgr = 0x52044,
1003 .cmd_rcgr = 0x520d4,
1004 .mnd_width = 0,
1018 F(19200000, P_BI_TCXO, 1, 0, 0),
1019 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1021 F(384000000, P_GPLL6_OUT_EARLY, 2, 0, 0),
1026 .cmd_rcgr = 0x52064,
1041 F(19200000, P_BI_TCXO, 1, 0, 0),
1042 F(40000000, P_GPLL0_OUT_AUX2, 7.5, 0, 0),
1043 F(80000000, P_GPLL0_OUT_EARLY, 7.5, 0, 0),
1048 .cmd_rcgr = 0x58010,
1049 .mnd_width = 0,
1063 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1064 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1065 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1066 F(200000000, P_GPLL0_OUT_AUX2, 1.5, 0, 0),
1071 .cmd_rcgr = 0x4d004,
1085 .cmd_rcgr = 0x4e004,
1099 .cmd_rcgr = 0x4f004,
1113 F(19200000, P_BI_TCXO, 1, 0, 0),
1114 F(60000000, P_GPLL0_OUT_AUX2, 5, 0, 0),
1119 .cmd_rcgr = 0x20010,
1120 .mnd_width = 0,
1135 F(19200000, P_BI_TCXO, 1, 0, 0),
1140 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1143 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1147 F(120000000, P_GPLL0_OUT_AUX2, 2.5, 0, 0),
1148 F(128000000, P_GPLL6_OUT_MAIN, 3, 0, 0),
1160 .cmd_rcgr = 0x1f148,
1176 .cmd_rcgr = 0x1f278,
1192 .cmd_rcgr = 0x1f3a8,
1208 .cmd_rcgr = 0x1f4d8,
1224 .cmd_rcgr = 0x1f608,
1240 .cmd_rcgr = 0x1f738,
1253 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1254 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1255 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
1256 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
1261 .cmd_rcgr = 0x38028,
1275 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1276 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1277 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1278 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1279 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1284 .cmd_rcgr = 0x38010,
1285 .mnd_width = 0,
1299 F(19200000, P_BI_TCXO, 1, 0, 0),
1300 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1301 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1302 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1303 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1308 .cmd_rcgr = 0x1e00c,
1323 F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0),
1324 F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0),
1325 F(100000000, P_GPLL0_OUT_AUX2, 3, 0, 0),
1326 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1327 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1332 .cmd_rcgr = 0x45020,
1346 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1347 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1348 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1349 F(300000000, P_GPLL0_OUT_AUX2, 1, 0, 0),
1354 .cmd_rcgr = 0x45048,
1355 .mnd_width = 0,
1368 F(9600000, P_BI_TCXO, 2, 0, 0),
1369 F(19200000, P_BI_TCXO, 1, 0, 0),
1374 .cmd_rcgr = 0x4507c,
1375 .mnd_width = 0,
1388 F(37500000, P_GPLL0_OUT_AUX2, 8, 0, 0),
1389 F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0),
1390 F(150000000, P_GPLL0_OUT_AUX2, 2, 0, 0),
1395 .cmd_rcgr = 0x45060,
1396 .mnd_width = 0,
1409 F(66666667, P_GPLL0_OUT_AUX2, 4.5, 0, 0),
1410 F(133333333, P_GPLL0_OUT_EARLY, 4.5, 0, 0),
1411 F(200000000, P_GPLL0_OUT_EARLY, 3, 0, 0),
1412 F(240000000, P_GPLL0_OUT_EARLY, 2.5, 0, 0),
1417 .cmd_rcgr = 0x1a01c,
1431 F(19200000, P_BI_TCXO, 1, 0, 0),
1436 .cmd_rcgr = 0x1a034,
1437 .mnd_width = 0,
1450 .reg = 0x1a04c,
1451 .shift = 0,
1463 .cmd_rcgr = 0x1a060,
1464 .mnd_width = 0,
1477 F(133333333, P_GPLL11_OUT_MAIN, 4.5, 0, 0),
1478 F(240000000, P_GPLL11_OUT_MAIN, 2.5, 0, 0),
1479 F(300000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1480 F(384000000, P_GPLL11_OUT_MAIN, 2, 0, 0),
1485 .cmd_rcgr = 0x58060,
1486 .mnd_width = 0,
1500 .halt_reg = 0x1d004,
1502 .hwcg_reg = 0x1d004,
1505 .enable_reg = 0x1d004,
1506 .enable_mask = BIT(0),
1515 .halt_reg = 0x1d008,
1517 .hwcg_reg = 0x1d008,
1520 .enable_reg = 0x1d008,
1521 .enable_mask = BIT(0),
1530 .halt_reg = 0x71154,
1532 .hwcg_reg = 0x71154,
1535 .enable_reg = 0x71154,
1536 .enable_mask = BIT(0),
1545 .halt_reg = 0x23004,
1547 .hwcg_reg = 0x23004,
1550 .enable_reg = 0x79004,
1560 .halt_reg = 0x17070,
1562 .hwcg_reg = 0x17070,
1565 .enable_reg = 0x79004,
1575 .halt_reg = 0x1706c,
1577 .hwcg_reg = 0x1706c,
1580 .enable_reg = 0x79004,
1590 .halt_reg = 0x17008,
1592 .hwcg_reg = 0x17008,
1595 .enable_reg = 0x17008,
1596 .enable_mask = BIT(0),
1606 .halt_reg = 0x17028,
1609 .enable_reg = 0x17028,
1610 .enable_mask = BIT(0),
1620 .halt_reg = 0x58044,
1623 .enable_reg = 0x58044,
1624 .enable_mask = BIT(0),
1638 .halt_reg = 0x5804c,
1640 .hwcg_reg = 0x5804c,
1643 .enable_reg = 0x5804c,
1644 .enable_mask = BIT(0),
1653 .halt_reg = 0x58050,
1655 .hwcg_reg = 0x58050,
1658 .enable_reg = 0x58050,
1659 .enable_mask = BIT(0),
1668 .halt_reg = 0x56018,
1671 .enable_reg = 0x56018,
1672 .enable_mask = BIT(0),
1686 .halt_reg = 0x52088,
1689 .enable_reg = 0x52088,
1690 .enable_mask = BIT(0),
1704 .halt_reg = 0x5208c,
1707 .enable_reg = 0x5208c,
1708 .enable_mask = BIT(0),
1722 .halt_reg = 0x52090,
1725 .enable_reg = 0x52090,
1726 .enable_mask = BIT(0),
1740 .halt_reg = 0x59018,
1743 .enable_reg = 0x59018,
1744 .enable_mask = BIT(0),
1758 .halt_reg = 0x59034,
1761 .enable_reg = 0x59034,
1762 .enable_mask = BIT(0),
1776 .halt_reg = 0x59050,
1779 .enable_reg = 0x59050,
1780 .enable_mask = BIT(0),
1794 .halt_reg = 0x51018,
1797 .enable_reg = 0x51018,
1798 .enable_mask = BIT(0),
1812 .halt_reg = 0x51034,
1815 .enable_reg = 0x51034,
1816 .enable_mask = BIT(0),
1830 .halt_reg = 0x51050,
1833 .enable_reg = 0x51050,
1834 .enable_mask = BIT(0),
1848 .halt_reg = 0x5106c,
1851 .enable_reg = 0x5106c,
1852 .enable_mask = BIT(0),
1866 .halt_reg = 0x58054,
1869 .enable_reg = 0x58054,
1870 .enable_mask = BIT(0),
1879 .halt_reg = 0x5503c,
1882 .enable_reg = 0x5503c,
1883 .enable_mask = BIT(0),
1897 .halt_reg = 0x5501c,
1900 .enable_reg = 0x5501c,
1901 .enable_mask = BIT(0),
1915 .halt_reg = 0x5805c,
1918 .enable_reg = 0x5805c,
1919 .enable_mask = BIT(0),
1928 .halt_reg = 0x5201c,
1931 .enable_reg = 0x5201c,
1932 .enable_mask = BIT(0),
1946 .halt_reg = 0x5207c,
1949 .enable_reg = 0x5207c,
1950 .enable_mask = BIT(0),
1964 .halt_reg = 0x520ac,
1967 .enable_reg = 0x520ac,
1968 .enable_mask = BIT(0),
1982 .halt_reg = 0x5203c,
1985 .enable_reg = 0x5203c,
1986 .enable_mask = BIT(0),
2000 .halt_reg = 0x52080,
2003 .enable_reg = 0x52080,
2004 .enable_mask = BIT(0),
2018 .halt_reg = 0x520cc,
2021 .enable_reg = 0x520cc,
2022 .enable_mask = BIT(0),
2036 .halt_reg = 0x5205c,
2039 .enable_reg = 0x5205c,
2040 .enable_mask = BIT(0),
2054 .halt_reg = 0x52084,
2057 .enable_reg = 0x52084,
2058 .enable_mask = BIT(0),
2072 .halt_reg = 0x520ec,
2075 .enable_reg = 0x520ec,
2076 .enable_mask = BIT(0),
2090 .halt_reg = 0x58028,
2093 .enable_reg = 0x58028,
2094 .enable_mask = BIT(0),
2108 .halt_reg = 0x1a084,
2110 .hwcg_reg = 0x1a084,
2113 .enable_reg = 0x1a084,
2114 .enable_mask = BIT(0),
2128 .halt_reg = 0x2b004,
2130 .hwcg_reg = 0x2b004,
2133 .enable_reg = 0x79004,
2144 .halt_reg = 0x1700c,
2146 .hwcg_reg = 0x1700c,
2149 .enable_reg = 0x1700c,
2150 .enable_mask = BIT(0),
2160 .reg = 0x17058,
2161 .shift = 0,
2174 .enable_reg = 0x79004,
2189 .halt_reg = 0x17020,
2191 .hwcg_reg = 0x17020,
2194 .enable_reg = 0x17020,
2195 .enable_mask = BIT(0),
2204 .halt_reg = 0x17064,
2206 .hwcg_reg = 0x17064,
2209 .enable_reg = 0x7900c,
2219 .halt_reg = 0x1702c,
2222 .enable_reg = 0x1702c,
2223 .enable_mask = BIT(0),
2233 .halt_reg = 0x4d000,
2236 .enable_reg = 0x4d000,
2237 .enable_mask = BIT(0),
2251 .halt_reg = 0x4e000,
2254 .enable_reg = 0x4e000,
2255 .enable_mask = BIT(0),
2269 .halt_reg = 0x4f000,
2272 .enable_reg = 0x4f000,
2273 .enable_mask = BIT(0),
2287 .halt_reg = 0x36004,
2289 .hwcg_reg = 0x36004,
2292 .enable_reg = 0x36004,
2293 .enable_mask = BIT(0),
2305 .enable_reg = 0x79004,
2322 .enable_reg = 0x79004,
2337 .halt_reg = 0x36100,
2340 .enable_reg = 0x36100,
2341 .enable_mask = BIT(0),
2350 .halt_reg = 0x3600c,
2352 .hwcg_reg = 0x3600c,
2355 .enable_reg = 0x3600c,
2356 .enable_mask = BIT(0),
2365 .halt_reg = 0x36018,
2368 .enable_reg = 0x36018,
2369 .enable_mask = BIT(0),
2378 .halt_reg = 0x36048,
2380 .hwcg_reg = 0x36048,
2383 .enable_reg = 0x79004,
2393 .halt_reg = 0x2000c,
2396 .enable_reg = 0x2000c,
2397 .enable_mask = BIT(0),
2411 .halt_reg = 0x20004,
2413 .hwcg_reg = 0x20004,
2416 .enable_reg = 0x20004,
2417 .enable_mask = BIT(0),
2426 .halt_reg = 0x20008,
2429 .enable_reg = 0x20008,
2430 .enable_mask = BIT(0),
2439 .halt_reg = 0x21004,
2441 .hwcg_reg = 0x21004,
2444 .enable_reg = 0x79004,
2454 .halt_reg = 0x17014,
2456 .hwcg_reg = 0x17014,
2459 .enable_reg = 0x7900c,
2460 .enable_mask = BIT(0),
2469 .halt_reg = 0x17060,
2471 .hwcg_reg = 0x17060,
2474 .enable_reg = 0x7900c,
2484 .halt_reg = 0x17018,
2486 .hwcg_reg = 0x17018,
2489 .enable_reg = 0x7900c,
2499 .halt_reg = 0x36040,
2501 .hwcg_reg = 0x36040,
2504 .enable_reg = 0x7900c,
2514 .halt_reg = 0x17010,
2516 .hwcg_reg = 0x17010,
2519 .enable_reg = 0x79004,
2529 .halt_reg = 0x1f014,
2532 .enable_reg = 0x7900c,
2542 .halt_reg = 0x1f00c,
2545 .enable_reg = 0x7900c,
2555 .halt_reg = 0x1f144,
2558 .enable_reg = 0x7900c,
2573 .halt_reg = 0x1f274,
2576 .enable_reg = 0x7900c,
2591 .halt_reg = 0x1f3a4,
2594 .enable_reg = 0x7900c,
2609 .halt_reg = 0x1f4d4,
2612 .enable_reg = 0x7900c,
2627 .halt_reg = 0x1f604,
2630 .enable_reg = 0x7900c,
2645 .halt_reg = 0x1f734,
2648 .enable_reg = 0x7900c,
2663 .halt_reg = 0x1f004,
2665 .hwcg_reg = 0x1f004,
2668 .enable_reg = 0x7900c,
2678 .halt_reg = 0x1f008,
2680 .hwcg_reg = 0x1f008,
2683 .enable_reg = 0x7900c,
2693 .halt_reg = 0x38008,
2696 .enable_reg = 0x38008,
2697 .enable_mask = BIT(0),
2706 .halt_reg = 0x38004,
2709 .enable_reg = 0x38004,
2710 .enable_mask = BIT(0),
2724 .halt_reg = 0x3800c,
2726 .hwcg_reg = 0x3800c,
2729 .enable_reg = 0x3800c,
2730 .enable_mask = BIT(0),
2744 .halt_reg = 0x1e008,
2747 .enable_reg = 0x1e008,
2748 .enable_mask = BIT(0),
2757 .halt_reg = 0x1e004,
2760 .enable_reg = 0x1e004,
2761 .enable_mask = BIT(0),
2775 .halt_reg = 0x2b06c,
2777 .hwcg_reg = 0x2b06c,
2780 .enable_reg = 0x79004,
2781 .enable_mask = BIT(0),
2791 .halt_reg = 0x45098,
2794 .enable_reg = 0x45098,
2795 .enable_mask = BIT(0),
2809 .halt_reg = 0x1a080,
2811 .hwcg_reg = 0x1a080,
2814 .enable_reg = 0x1a080,
2815 .enable_mask = BIT(0),
2829 .halt_reg = 0x8c000,
2832 .enable_reg = 0x8c000,
2833 .enable_mask = BIT(0),
2842 .halt_reg = 0x45014,
2844 .hwcg_reg = 0x45014,
2847 .enable_reg = 0x45014,
2848 .enable_mask = BIT(0),
2857 .halt_reg = 0x45010,
2859 .hwcg_reg = 0x45010,
2862 .enable_reg = 0x45010,
2863 .enable_mask = BIT(0),
2877 .halt_reg = 0x45044,
2879 .hwcg_reg = 0x45044,
2882 .enable_reg = 0x45044,
2883 .enable_mask = BIT(0),
2897 .halt_reg = 0x45078,
2899 .hwcg_reg = 0x45078,
2902 .enable_reg = 0x45078,
2903 .enable_mask = BIT(0),
2917 .halt_reg = 0x4501c,
2920 .enable_reg = 0x4501c,
2921 .enable_mask = BIT(0),
2930 .halt_reg = 0x45018,
2933 .enable_reg = 0x45018,
2934 .enable_mask = BIT(0),
2943 .halt_reg = 0x45040,
2945 .hwcg_reg = 0x45040,
2948 .enable_reg = 0x45040,
2949 .enable_mask = BIT(0),
2963 .halt_reg = 0x1a010,
2966 .enable_reg = 0x1a010,
2967 .enable_mask = BIT(0),
2981 .halt_reg = 0x1a018,
2984 .enable_reg = 0x1a018,
2985 .enable_mask = BIT(0),
2999 .halt_reg = 0x1a014,
3002 .enable_reg = 0x1a014,
3003 .enable_mask = BIT(0),
3012 .halt_reg = 0x9f000,
3015 .enable_reg = 0x9f000,
3016 .enable_mask = BIT(0),
3025 .halt_reg = 0x1a054,
3028 .enable_reg = 0x1a054,
3029 .enable_mask = BIT(0),
3043 .halt_reg = 0x1a058,
3045 .hwcg_reg = 0x1a058,
3048 .enable_reg = 0x1a058,
3049 .enable_mask = BIT(0),
3058 .halt_reg = 0x6e008,
3061 .enable_reg = 0x6e008,
3062 .enable_mask = BIT(0),
3071 .halt_reg = 0x6e010,
3074 .enable_reg = 0x6e010,
3075 .enable_mask = BIT(0),
3084 .halt_reg = 0x6e004,
3087 .enable_reg = 0x6e004,
3088 .enable_mask = BIT(0),
3097 .halt_reg = 0x17004,
3099 .hwcg_reg = 0x17004,
3102 .enable_reg = 0x17004,
3103 .enable_mask = BIT(0),
3112 .halt_reg = 0x1701c,
3114 .hwcg_reg = 0x1701c,
3117 .enable_reg = 0x1701c,
3118 .enable_mask = BIT(0),
3127 .halt_reg = 0x17068,
3129 .hwcg_reg = 0x17068,
3132 .enable_reg = 0x79004,
3142 .halt_reg = 0x580a4,
3144 .hwcg_reg = 0x580a4,
3147 .enable_reg = 0x580a4,
3148 .enable_mask = BIT(0),
3162 .halt_reg = 0x5808c,
3165 .enable_reg = 0x5808c,
3166 .enable_mask = BIT(0),
3180 .halt_reg = 0x17024,
3183 .enable_reg = 0x17024,
3184 .enable_mask = BIT(0),
3193 .gdscr = 0x58004,
3201 .gdscr = 0x45004,
3209 .gdscr = 0x1a004,
3217 .gdscr = 0x58098,
3225 .gdscr = 0x5807c,
3233 .gdscr = 0x7d060,
3242 .gdscr = 0x7d07c,
3251 .gdscr = 0x7d074,
3260 .gdscr = 0x7d078,
3438 [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
3439 [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
3440 [GCC_SDCC1_BCR] = { 0x38000 },
3441 [GCC_SDCC2_BCR] = { 0x1e000 },
3442 [GCC_UFS_PHY_BCR] = { 0x45000 },
3443 [GCC_USB30_PRIM_BCR] = { 0x1a000 },
3444 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
3445 [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
3446 [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
3447 [GCC_VCODEC0_BCR] = { 0x58094 },
3448 [GCC_VENUS_BCR] = { 0x58078 },
3449 [GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
3477 .max_register = 0xc7000,