Lines Matching +full:0 +full:x4e000
49 { P_XO, 0 },
68 .offset = 0x21000,
71 .enable_reg = 0x45008,
84 .offset = 0x21000,
88 .enable_reg = 0x45000,
89 .enable_mask = BIT(0),
100 .offset = 0x21000,
104 .enable_reg = 0x45000,
105 .enable_mask = BIT(0),
117 .offset = 0x20000,
120 .enable_reg = 0x45000,
134 .alpha = 0x0,
136 .post_div_mask = 0xf << 8,
137 .post_div_val = 0x1 << 8,
138 .vco_mask = 0x3 << 20,
139 .main_output_mask = 0x1,
140 .config_ctl_val = 0x4001055b,
144 { 700000000, 1400000000, 0 },
148 .offset = 0x22000,
163 .offset = 0x24000,
166 .enable_reg = 0x45000,
178 .l_reg = 0x37004,
179 .m_reg = 0x37008,
180 .n_reg = 0x3700C,
181 .config_reg = 0x37014,
182 .mode_reg = 0x37000,
183 .status_reg = 0x3701C,
194 .enable_reg = 0x45000,
207 { P_XO, 0 },
222 { P_XO, 0 },
236 { P_XO, 0 },
248 { P_XO, 0 },
258 { P_XO, 0 },
268 { P_XO, 0 },
278 { P_XO, 0 },
292 { P_XO, 0 },
302 { P_XO, 0 },
316 { P_XO, 0 },
326 { P_XO, 0 },
336 { P_XO, 0 },
346 { P_XO, 0 },
360 { P_XO, 0 },
370 { P_XO, 0 },
378 { P_XO, 0 },
388 F(19200000, P_XO, 1, 0, 0),
389 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
390 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
391 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
396 .cmd_rcgr = 0x46000,
397 .mnd_width = 0,
411 F(19200000, P_XO, 1, 0, 0),
412 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
417 .cmd_rcgr = 0x602c,
418 .mnd_width = 0,
432 F(4800000, P_XO, 4, 0, 0),
433 F(9600000, P_XO, 2, 0, 0),
435 F(19200000, P_XO, 1, 0, 0),
437 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
442 .cmd_rcgr = 0x6034,
456 .cmd_rcgr = 0x200c,
457 .mnd_width = 0,
471 F(4800000, P_XO, 4, 0, 0),
472 F(9600000, P_XO, 2, 0, 0),
475 F(19200000, P_XO, 1, 0, 0),
481 .cmd_rcgr = 0x2024,
495 .cmd_rcgr = 0x3000,
496 .mnd_width = 0,
510 F(4800000, P_XO, 4, 0, 0),
511 F(9600000, P_XO, 2, 0, 0),
514 F(19200000, P_XO, 1, 0, 0),
521 .cmd_rcgr = 0x3014,
535 .cmd_rcgr = 0x4000,
536 .mnd_width = 0,
549 .cmd_rcgr = 0x4024,
563 .cmd_rcgr = 0x5000,
564 .mnd_width = 0,
577 .cmd_rcgr = 0x5024,
595 F(19200000, P_XO, 1, 0, 0),
611 .cmd_rcgr = 0x600c,
625 .cmd_rcgr = 0x2044,
639 .cmd_rcgr = 0x3034,
653 .cmd_rcgr = 0x4014,
656 .cfg_off = 0x20,
668 .cmd_rcgr = 0xc00c,
669 .mnd_width = 0,
682 .cmd_rcgr = 0xc024,
696 .cmd_rcgr = 0xc044,
710 .cmd_rcgr = 0x4d044,
711 .mnd_width = 0,
725 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
726 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
727 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
732 .cmd_rcgr = 0x4e01c,
746 F(50000000, P_GPLL1_OUT_MAIN, 10, 0, 0),
747 F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
748 F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
753 .cmd_rcgr = 0x4e014,
754 .mnd_width = 0,
767 F(19200000, P_XO, 1, 0, 0),
772 .cmd_rcgr = 0x4d05c,
773 .mnd_width = 0,
786 F(19200000, P_XO, 1, 0, 0),
787 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
788 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
789 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
790 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
791 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
792 F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
793 F(240000000, P_GPLL6_OUT_AUX, 4.5, 0, 0),
794 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
795 F(270000000, P_GPLL6_OUT_AUX, 4, 0, 0),
796 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
797 F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
798 F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
799 F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
800 F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
801 F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
806 .cmd_rcgr = 0x59000,
807 .mnd_width = 0,
820 F(19200000, P_XO, 1, 0, 0),
821 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
822 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
827 .cmd_rcgr = 0x8004,
841 .cmd_rcgr = 0x9004,
855 .cmd_rcgr = 0xa004,
869 .cmd_rcgr = 0x4d0e4,
870 .mnd_width = 0,
883 .cmd_rcgr = 0x4d0dc,
884 .mnd_width = 0,
897 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
898 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
899 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
900 F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
901 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
902 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
903 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
904 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
905 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
910 .cmd_rcgr = 0x4d014,
911 .mnd_width = 0,
924 F(1200000, P_XO, 16, 0, 0),
929 .cmd_rcgr = 0x3e024,
943 F(19200000, P_XO, 1, 0, 0),
944 F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
945 F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
950 .cmd_rcgr = 0x3e01c,
951 .mnd_width = 0,
964 .cmd_rcgr = 0x4d000,
978 F(19200000, P_XO, 1, 0, 0),
979 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
984 .cmd_rcgr = 0x44010,
985 .mnd_width = 0,
1002 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1003 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1004 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1005 F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1006 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1007 F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1012 .cmd_rcgr = 0x42004,
1026 F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1027 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1032 .cmd_rcgr = 0x5d000,
1050 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1051 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1052 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1053 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1058 .cmd_rcgr = 0x43004,
1072 .cmd_rcgr = 0x41048,
1073 .mnd_width = 0,
1086 F(19200000, P_XO, 1, 0, 0),
1087 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1088 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1089 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1094 .cmd_rcgr = 0x39028,
1108 .cmd_rcgr = 0x3901c,
1109 .mnd_width = 0,
1122 .cmd_rcgr = 0x3903c,
1123 .mnd_width = 0,
1136 F(19200000, P_XO, 1, 0, 0),
1137 F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1138 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1139 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1140 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1145 .cmd_rcgr = 0x41010,
1146 .mnd_width = 0,
1159 .cmd_rcgr = 0x4d02c,
1160 .mnd_width = 0,
1173 F(19200000, P_XO, 1, 0, 0),
1174 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1175 F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1176 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1181 .cmd_rcgr = 0x5e010,
1182 .mnd_width = 0,
1195 .halt_reg = 0x4601c,
1198 .enable_reg = 0x45004,
1213 .halt_reg = 0x5b004,
1216 .enable_reg = 0x4500c,
1226 .halt_reg = 0x59034,
1229 .enable_reg = 0x59034,
1230 .enable_mask = BIT(0),
1243 .halt_reg = 0x59030,
1246 .enable_reg = 0x59030,
1247 .enable_mask = BIT(0),
1256 .halt_reg = 0x31030,
1259 .enable_reg = 0x31030,
1260 .enable_mask = BIT(0),
1274 .halt_reg = 0x31038,
1277 .enable_reg = 0x31038,
1278 .enable_mask = BIT(0),
1287 .halt_reg = 0x1008,
1290 .enable_reg = 0x45004,
1300 .halt_reg = 0x77004,
1303 .enable_reg = 0x77004,
1304 .enable_mask = BIT(0),
1313 .halt_reg = 0x77008,
1316 .enable_reg = 0x77008,
1317 .enable_mask = BIT(0),
1326 .halt_reg = 0x6028,
1329 .enable_reg = 0x6028,
1330 .enable_mask = BIT(0),
1344 .halt_reg = 0x6024,
1347 .enable_reg = 0x6024,
1348 .enable_mask = BIT(0),
1362 .halt_reg = 0x2008,
1365 .enable_reg = 0x2008,
1366 .enable_mask = BIT(0),
1380 .halt_reg = 0x2004,
1383 .enable_reg = 0x2004,
1384 .enable_mask = BIT(0),
1398 .halt_reg = 0x3010,
1401 .enable_reg = 0x3010,
1402 .enable_mask = BIT(0),
1416 .halt_reg = 0x300c,
1419 .enable_reg = 0x300c,
1420 .enable_mask = BIT(0),
1434 .halt_reg = 0x4020,
1437 .enable_reg = 0x4020,
1438 .enable_mask = BIT(0),
1452 .halt_reg = 0x401c,
1455 .enable_reg = 0x401c,
1456 .enable_mask = BIT(0),
1470 .halt_reg = 0x5020,
1473 .enable_reg = 0x5020,
1474 .enable_mask = BIT(0),
1488 .halt_reg = 0x501c,
1491 .enable_reg = 0x501c,
1492 .enable_mask = BIT(0),
1506 .halt_reg = 0x6004,
1509 .enable_reg = 0x6004,
1510 .enable_mask = BIT(0),
1524 .halt_reg = 0x203c,
1527 .enable_reg = 0x203c,
1528 .enable_mask = BIT(0),
1542 .halt_reg = 0x302c,
1545 .enable_reg = 0x302c,
1546 .enable_mask = BIT(0),
1560 .halt_reg = 0x400c,
1563 .enable_reg = 0x400c,
1564 .enable_mask = BIT(0),
1578 .halt_reg = 0xb008,
1581 .enable_reg = 0x45004,
1591 .halt_reg = 0xc008,
1594 .enable_reg = 0xc008,
1595 .enable_mask = BIT(0),
1609 .halt_reg = 0xc004,
1612 .enable_reg = 0xc004,
1613 .enable_mask = BIT(0),
1627 .halt_reg = 0xc03c,
1630 .enable_reg = 0xc03c,
1631 .enable_mask = BIT(0),
1645 .halt_reg = 0x1300c,
1648 .enable_reg = 0x45004,
1658 .halt_reg = 0x16024,
1661 .enable_reg = 0x45004,
1662 .enable_mask = BIT(0),
1671 .halt_reg = 0x16020,
1674 .enable_reg = 0x45004,
1684 .halt_reg = 0x1601c,
1687 .enable_reg = 0x45004,
1697 .halt_reg = 0x4e010,
1700 .enable_reg = 0x4e010,
1701 .enable_mask = BIT(0),
1710 .halt_reg = 0x4e004,
1713 .enable_reg = 0x4e004,
1714 .enable_mask = BIT(0),
1728 .halt_reg = 0x4e008,
1731 .enable_reg = 0x4e008,
1732 .enable_mask = BIT(0),
1746 .halt_reg = 0x4e00c,
1749 .enable_reg = 0x4e00c,
1750 .enable_mask = BIT(0),
1759 .halt_reg = 0xf008,
1762 .enable_reg = 0xf008,
1763 .enable_mask = BIT(0),
1772 .halt_reg = 0xf004,
1775 .enable_reg = 0xf004,
1776 .enable_mask = BIT(0),
1785 .halt_reg = 0x12020,
1788 .enable_reg = 0x4500C,
1798 .halt_reg = 0x12010,
1801 .enable_reg = 0x4500C,
1811 .halt_reg = 0x1203c,
1814 .enable_reg = 0x13020,
1829 .halt_reg = 0x8000,
1832 .enable_reg = 0x8000,
1833 .enable_mask = BIT(0),
1847 .halt_reg = 0x9000,
1850 .enable_reg = 0x9000,
1851 .enable_mask = BIT(0),
1865 .halt_reg = 0xa000,
1868 .enable_reg = 0xa000,
1869 .enable_mask = BIT(0),
1883 .halt_reg = 0x12044,
1886 .enable_reg = 0x4500c,
1896 .halt_reg = 0x1201c,
1899 .enable_reg = 0x4500c,
1909 .halt_reg = 0x4d07c,
1912 .enable_reg = 0x4d07c,
1913 .enable_mask = BIT(0),
1922 .halt_reg = 0x4d080,
1925 .enable_reg = 0x4d080,
1926 .enable_mask = BIT(0),
1935 .halt_reg = 0x4d094,
1938 .enable_reg = 0x4d094,
1939 .enable_mask = BIT(0),
1953 .halt_reg = 0x4d098,
1956 .enable_reg = 0x4d098,
1957 .enable_mask = BIT(0),
1971 .halt_reg = 0x4d0d8,
1974 .enable_reg = 0x4d0d8,
1975 .enable_mask = BIT(0),
1989 .halt_reg = 0x4d0d4,
1992 .enable_reg = 0x4d0d4,
1993 .enable_mask = BIT(0),
2007 .halt_reg = 0x4d088,
2010 .enable_reg = 0x4d088,
2011 .enable_mask = BIT(0),
2025 .halt_reg = 0x4d084,
2028 .enable_reg = 0x4d084,
2029 .enable_mask = BIT(0),
2043 .halt_reg = 0x4d090,
2046 .enable_reg = 0x4d090,
2047 .enable_mask = BIT(0),
2061 .halt_reg = 0x59028,
2064 .enable_reg = 0x59028,
2065 .enable_mask = BIT(0),
2074 .halt_reg = 0x59020,
2077 .enable_reg = 0x59020,
2078 .enable_mask = BIT(0),
2092 .halt_reg = 0x3e014,
2095 .enable_reg = 0x45004,
2110 .halt_reg = 0x3e008,
2113 .enable_reg = 0x45004,
2123 .halt_reg = 0x3e018,
2126 .enable_reg = 0x45004,
2136 .halt_reg = 0x3e00c,
2139 .enable_reg = 0x45004,
2154 .halt_reg = 0x3e010,
2157 .enable_reg = 0x45004,
2167 .halt_reg = 0x27008,
2170 .enable_reg = 0x27008,
2171 .enable_mask = BIT(0),
2181 .halt_reg = 0x2700c,
2184 .enable_reg = 0x2700c,
2185 .enable_mask = BIT(0),
2195 .halt_reg = 0x4400c,
2198 .enable_reg = 0x4400c,
2199 .enable_mask = BIT(0),
2213 .halt_reg = 0x44004,
2216 .enable_reg = 0x44004,
2217 .enable_mask = BIT(0),
2226 .halt_reg = 0x13004,
2229 .enable_reg = 0x45004,
2240 .halt_reg = 0x44018,
2243 .enable_reg = 0x44018,
2244 .enable_mask = BIT(0),
2253 .halt_reg = 0x49004,
2256 .enable_reg = 0x49004,
2257 .enable_mask = BIT(0),
2266 .halt_reg = 0x4a004,
2269 .enable_reg = 0x4a004,
2270 .enable_mask = BIT(0),
2279 .halt_reg = 0x29084,
2282 .enable_reg = 0x45004,
2292 .halt_reg = 0x4201c,
2295 .enable_reg = 0x4201c,
2296 .enable_mask = BIT(0),
2305 .halt_reg = 0x42018,
2308 .enable_reg = 0x42018,
2309 .enable_mask = BIT(0),
2323 .halt_reg = 0x5d014,
2326 .enable_reg = 0x5d014,
2327 .enable_mask = BIT(0),
2341 .halt_reg = 0x5e004,
2344 .enable_reg = 0x5e004,
2345 .enable_mask = BIT(0),
2354 .halt_reg = 0x4301c,
2357 .enable_reg = 0x4301c,
2358 .enable_mask = BIT(0),
2367 .halt_reg = 0x43018,
2370 .enable_reg = 0x43018,
2371 .enable_mask = BIT(0),
2385 .halt_reg = 0x12038,
2388 .enable_reg = 0x3600C,
2398 .halt_reg = 0x26014,
2401 .enable_reg = 0x26014,
2402 .enable_mask = BIT(0),
2415 .halt_reg = 0x4100C,
2418 .enable_reg = 0x4100C,
2419 .enable_mask = BIT(0),
2428 .halt_reg = 0x41044,
2431 .enable_reg = 0x41044,
2432 .enable_mask = BIT(0),
2446 .halt_reg = 0x4102c,
2449 .enable_reg = 0x4102c,
2450 .enable_mask = BIT(0),
2459 .halt_reg = 0x3900c,
2462 .enable_reg = 0x3900c,
2463 .enable_mask = BIT(0),
2477 .halt_reg = 0x39014,
2480 .enable_reg = 0x39014,
2481 .enable_mask = BIT(0),
2495 .halt_reg = 0x39010,
2498 .enable_reg = 0x39010,
2499 .enable_mask = BIT(0),
2508 .halt_reg = 0x39044,
2511 .enable_reg = 0x39044,
2512 .enable_mask = BIT(0),
2528 .enable_reg = 0x39018,
2529 .enable_mask = BIT(0),
2538 .halt_reg = 0x41030,
2541 .enable_reg = 0x41030,
2542 .enable_mask = BIT(0),
2551 .halt_reg = 0x41004,
2554 .enable_reg = 0x41004,
2555 .enable_mask = BIT(0),
2569 .halt_reg = 0x1e004,
2572 .enable_reg = 0x1e004,
2573 .enable_mask = BIT(0),
2582 .halt_reg = 0x1e008,
2585 .enable_reg = 0x1e008,
2586 .enable_mask = BIT(0),
2595 .gdscr = 0x4d078,
2603 .gdscr = 0x5901c,
2766 [GCC_GENI_IR_BCR] = { 0x0F000 },
2767 [GCC_CDSP_RESTART] = { 0x18000 },
2768 [GCC_USB_HS_BCR] = { 0x41000 },
2769 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2770 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2771 [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2772 [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2773 [GCC_USB3_PHY_BCR] = { 0x39004 },
2774 [GCC_USB_30_BCR] = { 0x39000 },
2775 [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2776 [GCC_PCIE_0_BCR] = { 0x3e000 },
2777 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2778 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2779 [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2780 [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
2781 [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
2782 [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
2783 [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
2784 [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
2785 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2786 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2787 [GCC_EMAC_BCR] = { 0x4e000 },
2788 [GCC_WDSP_RESTART] = {0x19000},
2795 .max_register = 0x7f000,