Lines Matching +full:0 +full:x4e000
27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
107 .offset = 0x1000,
112 .enable_reg = 0x52000,
126 .offset = 0x1000,
139 .offset = 0x1000,
152 .offset = 0x1000,
165 .offset = 0x1000,
178 .offset = 0x2000,
183 .enable_reg = 0x52000,
197 .offset = 0x2000,
210 .offset = 0x2000,
223 .offset = 0x2000,
236 .offset = 0x2000,
249 .offset = 0x3000,
254 .enable_reg = 0x52000,
268 .offset = 0x3000,
281 .offset = 0x3000,
294 .offset = 0x3000,
307 .offset = 0x3000,
320 .offset = 0x77000,
325 .enable_reg = 0x52000,
339 .offset = 0x77000,
352 .offset = 0x77000,
365 .offset = 0x77000,
378 .offset = 0x77000,
400 { P_XO, 0 },
412 { P_XO, 0 },
422 { P_XO, 0 },
436 { P_XO, 0 },
446 { P_XO, 0 },
458 { P_XO, 0 },
470 F(19200000, P_XO, 1, 0, 0),
471 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
476 .cmd_rcgr = 0x19020,
477 .mnd_width = 0,
491 F(4800000, P_XO, 4, 0, 0),
492 F(9600000, P_XO, 2, 0, 0),
494 F(19200000, P_XO, 1, 0, 0),
496 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
501 .cmd_rcgr = 0x1900c,
515 .cmd_rcgr = 0x1b020,
516 .mnd_width = 0,
529 .cmd_rcgr = 0x1b00c,
543 .cmd_rcgr = 0x1d020,
544 .mnd_width = 0,
557 .cmd_rcgr = 0x1d00c,
571 .cmd_rcgr = 0x1f020,
572 .mnd_width = 0,
585 .cmd_rcgr = 0x1f00c,
599 .cmd_rcgr = 0x21020,
600 .mnd_width = 0,
613 .cmd_rcgr = 0x2100c,
627 .cmd_rcgr = 0x23020,
628 .mnd_width = 0,
641 .cmd_rcgr = 0x2300c,
659 F(19200000, P_XO, 1, 0, 0),
662 F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0),
664 F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
668 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
669 F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0),
674 .cmd_rcgr = 0x1a00c,
688 .cmd_rcgr = 0x1c00c,
702 .cmd_rcgr = 0x1e00c,
716 .cmd_rcgr = 0x26020,
717 .mnd_width = 0,
730 .cmd_rcgr = 0x2600c,
744 .cmd_rcgr = 0x28020,
745 .mnd_width = 0,
758 .cmd_rcgr = 0x2800c,
772 .cmd_rcgr = 0x2a020,
773 .mnd_width = 0,
786 .cmd_rcgr = 0x2a00c,
800 .cmd_rcgr = 0x2c020,
801 .mnd_width = 0,
814 .cmd_rcgr = 0x2c00c,
828 .cmd_rcgr = 0x2e020,
829 .mnd_width = 0,
842 .cmd_rcgr = 0x2e00c,
856 .cmd_rcgr = 0x30020,
857 .mnd_width = 0,
870 .cmd_rcgr = 0x3000c,
884 .cmd_rcgr = 0x2700c,
898 .cmd_rcgr = 0x2900c,
912 .cmd_rcgr = 0x2b00c,
926 F(19200000, P_XO, 1, 0, 0),
927 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
928 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
933 .cmd_rcgr = 0x64004,
947 .cmd_rcgr = 0x65004,
961 .cmd_rcgr = 0x66004,
975 F(19200000, P_XO, 1, 0, 0),
976 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
977 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
982 .cmd_rcgr = 0x48014,
983 .mnd_width = 0,
996 F(19200000, P_XO, 1, 0, 0),
1001 .cmd_rcgr = 0x48044,
1002 .mnd_width = 0,
1020 .cmd_rcgr = 0x6c000,
1034 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1039 .cmd_rcgr = 0x33010,
1040 .mnd_width = 0,
1057 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1058 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1059 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1064 .cmd_rcgr = 0x14010,
1082 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
1083 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1088 .cmd_rcgr = 0x16010,
1107 .cmd_rcgr = 0x36010,
1121 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
1122 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1123 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1128 .cmd_rcgr = 0x75018,
1142 F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1143 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1144 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1149 .cmd_rcgr = 0x76028,
1163 F(19200000, P_XO, 1, 0, 0),
1164 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1165 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1166 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1171 .cmd_rcgr = 0xf014,
1185 .cmd_rcgr = 0xf028,
1186 .mnd_width = 0,
1199 F(1200000, P_XO, 16, 0, 0),
1204 .cmd_rcgr = 0x5000c,
1205 .mnd_width = 0,
1218 .halt_reg = 0x8202c,
1221 .enable_reg = 0x8202c,
1222 .enable_mask = BIT(0),
1231 .halt_reg = 0x82028,
1234 .enable_reg = 0x82028,
1235 .enable_mask = BIT(0),
1249 .halt_reg = 0x82024,
1252 .enable_reg = 0x82024,
1253 .enable_mask = BIT(0),
1267 .halt_reg = 0x48090,
1270 .enable_reg = 0x48090,
1271 .enable_mask = BIT(0),
1280 .halt_reg = 0x48094,
1283 .enable_reg = 0x48094,
1284 .enable_mask = BIT(0),
1293 .halt_reg = 0x48004,
1296 .enable_reg = 0x52004,
1306 .halt_reg = 0x4401c,
1309 .enable_reg = 0x4401c,
1310 .enable_mask = BIT(0),
1319 .halt_reg = 0x8a000,
1322 .enable_reg = 0x8a000,
1323 .enable_mask = BIT(0),
1332 .halt_reg = 0x8a03c,
1335 .enable_reg = 0x8a03c,
1336 .enable_mask = BIT(0),
1345 .halt_reg = 0x8a004,
1348 .enable_reg = 0x8a004,
1349 .enable_mask = BIT(0),
1358 .halt_reg = 0x38004,
1360 .hwcg_reg = 0x38004,
1363 .enable_reg = 0x52004,
1375 .enable_reg = 0x5200c,
1376 .enable_mask = BIT(0),
1391 .enable_reg = 0x5200c,
1407 .enable_reg = 0x5200c,
1419 .enable_reg = 0x5200c,
1435 .enable_reg = 0x5200c,
1449 .halt_reg = 0x17004,
1452 .enable_reg = 0x52004,
1462 .halt_reg = 0x19008,
1465 .enable_reg = 0x19008,
1466 .enable_mask = BIT(0),
1480 .halt_reg = 0x19004,
1483 .enable_reg = 0x19004,
1484 .enable_mask = BIT(0),
1498 .halt_reg = 0x1b008,
1501 .enable_reg = 0x1b008,
1502 .enable_mask = BIT(0),
1516 .halt_reg = 0x1b004,
1519 .enable_reg = 0x1b004,
1520 .enable_mask = BIT(0),
1534 .halt_reg = 0x1d008,
1537 .enable_reg = 0x1d008,
1538 .enable_mask = BIT(0),
1552 .halt_reg = 0x1d004,
1555 .enable_reg = 0x1d004,
1556 .enable_mask = BIT(0),
1570 .halt_reg = 0x1f008,
1573 .enable_reg = 0x1f008,
1574 .enable_mask = BIT(0),
1588 .halt_reg = 0x1f004,
1591 .enable_reg = 0x1f004,
1592 .enable_mask = BIT(0),
1606 .halt_reg = 0x21008,
1609 .enable_reg = 0x21008,
1610 .enable_mask = BIT(0),
1624 .halt_reg = 0x21004,
1627 .enable_reg = 0x21004,
1628 .enable_mask = BIT(0),
1642 .halt_reg = 0x23008,
1645 .enable_reg = 0x23008,
1646 .enable_mask = BIT(0),
1660 .halt_reg = 0x23004,
1663 .enable_reg = 0x23004,
1664 .enable_mask = BIT(0),
1678 .halt_reg = 0x17008,
1681 .enable_reg = 0x52004,
1691 .halt_reg = 0x1a004,
1694 .enable_reg = 0x1a004,
1695 .enable_mask = BIT(0),
1709 .halt_reg = 0x1c004,
1712 .enable_reg = 0x1c004,
1713 .enable_mask = BIT(0),
1727 .halt_reg = 0x1e004,
1730 .enable_reg = 0x1e004,
1731 .enable_mask = BIT(0),
1745 .halt_reg = 0x25004,
1748 .enable_reg = 0x52004,
1758 .halt_reg = 0x26008,
1761 .enable_reg = 0x26008,
1762 .enable_mask = BIT(0),
1776 .halt_reg = 0x26004,
1779 .enable_reg = 0x26004,
1780 .enable_mask = BIT(0),
1794 .halt_reg = 0x28008,
1797 .enable_reg = 0x28008,
1798 .enable_mask = BIT(0),
1812 .halt_reg = 0x28004,
1815 .enable_reg = 0x28004,
1816 .enable_mask = BIT(0),
1830 .halt_reg = 0x2a008,
1833 .enable_reg = 0x2a008,
1834 .enable_mask = BIT(0),
1848 .halt_reg = 0x2a004,
1851 .enable_reg = 0x2a004,
1852 .enable_mask = BIT(0),
1866 .halt_reg = 0x2c008,
1869 .enable_reg = 0x2c008,
1870 .enable_mask = BIT(0),
1884 .halt_reg = 0x2c004,
1887 .enable_reg = 0x2c004,
1888 .enable_mask = BIT(0),
1902 .halt_reg = 0x2e008,
1905 .enable_reg = 0x2e008,
1906 .enable_mask = BIT(0),
1920 .halt_reg = 0x2e004,
1923 .enable_reg = 0x2e004,
1924 .enable_mask = BIT(0),
1938 .halt_reg = 0x30008,
1941 .enable_reg = 0x30008,
1942 .enable_mask = BIT(0),
1956 .halt_reg = 0x30004,
1959 .enable_reg = 0x30004,
1960 .enable_mask = BIT(0),
1974 .halt_reg = 0x25008,
1977 .enable_reg = 0x52004,
1987 .halt_reg = 0x27004,
1990 .enable_reg = 0x27004,
1991 .enable_mask = BIT(0),
2005 .halt_reg = 0x29004,
2008 .enable_reg = 0x29004,
2009 .enable_mask = BIT(0),
2023 .halt_reg = 0x2b004,
2026 .enable_reg = 0x2b004,
2027 .enable_mask = BIT(0),
2041 .halt_reg = 0x5018,
2044 .enable_reg = 0x5018,
2045 .enable_mask = BIT(0),
2059 .halt_reg = 0x64000,
2062 .enable_reg = 0x64000,
2063 .enable_mask = BIT(0),
2077 .halt_reg = 0x65000,
2080 .enable_reg = 0x65000,
2081 .enable_mask = BIT(0),
2095 .halt_reg = 0x66000,
2098 .enable_reg = 0x66000,
2099 .enable_mask = BIT(0),
2113 .halt_reg = 0x46040,
2116 .enable_reg = 0x46040,
2117 .enable_mask = BIT(0),
2126 .halt_reg = 0x71010,
2129 .enable_reg = 0x71010,
2130 .enable_mask = BIT(0),
2139 .halt_reg = 0x7100c,
2142 .enable_reg = 0x7100c,
2143 .enable_mask = BIT(0),
2152 .halt_reg = 0x71004,
2155 .enable_reg = 0x71004,
2156 .enable_mask = BIT(0),
2171 .halt_reg = 0x71018,
2174 .enable_reg = 0x71018,
2175 .enable_mask = BIT(0),
2184 .halt_reg = 0x48000,
2187 .enable_reg = 0x52004,
2202 .halt_reg = 0x48010,
2205 .enable_reg = 0x48010,
2206 .enable_mask = BIT(0),
2215 .halt_reg = 0x48008,
2218 .enable_reg = 0x48008,
2219 .enable_mask = BIT(0),
2233 .halt_reg = 0x4800c,
2236 .enable_reg = 0x4800c,
2237 .enable_mask = BIT(0),
2246 F( 300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
2247 F( 600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
2252 .cmd_rcgr = 0x4805c,
2265 .halt_reg = 0x9004,
2268 .enable_reg = 0x9004,
2269 .enable_mask = BIT(0),
2284 .halt_reg = 0x9030,
2287 .enable_reg = 0x9030,
2288 .enable_mask = BIT(0),
2297 .halt_reg = 0x900c,
2300 .enable_reg = 0x900c,
2301 .enable_mask = BIT(0),
2310 .halt_reg = 0x9000,
2313 .enable_reg = 0x9000,
2314 .enable_mask = BIT(0),
2323 .halt_reg = 0x8a00c,
2326 .enable_reg = 0x8a00c,
2327 .enable_mask = BIT(0),
2336 .halt_reg = 0x6b014,
2339 .enable_reg = 0x6b014,
2340 .enable_mask = BIT(0),
2354 .halt_reg = 0x6b010,
2357 .enable_reg = 0x6b010,
2358 .enable_mask = BIT(0),
2367 .halt_reg = 0x6b00c,
2370 .enable_reg = 0x6b00c,
2371 .enable_mask = BIT(0),
2380 .halt_reg = 0x6b018,
2383 .enable_reg = 0x6b018,
2384 .enable_mask = BIT(0),
2393 .halt_reg = 0x6b008,
2396 .enable_reg = 0x6b008,
2397 .enable_mask = BIT(0),
2406 .halt_reg = 0x6f004,
2409 .enable_reg = 0x6f004,
2410 .enable_mask = BIT(0),
2424 .halt_reg = 0x3300c,
2427 .enable_reg = 0x3300c,
2428 .enable_mask = BIT(0),
2442 .halt_reg = 0x33004,
2445 .enable_reg = 0x33004,
2446 .enable_mask = BIT(0),
2455 .halt_reg = 0x33008,
2458 .enable_reg = 0x33008,
2459 .enable_mask = BIT(0),
2468 .halt_reg = 0x34004,
2471 .enable_reg = 0x52004,
2481 .halt_reg = 0x14008,
2484 .enable_reg = 0x14008,
2485 .enable_mask = BIT(0),
2494 .halt_reg = 0x14004,
2497 .enable_reg = 0x14004,
2498 .enable_mask = BIT(0),
2512 .halt_reg = 0x16008,
2515 .enable_reg = 0x16008,
2516 .enable_mask = BIT(0),
2525 .halt_reg = 0x16004,
2528 .enable_reg = 0x16004,
2529 .enable_mask = BIT(0),
2543 .halt_reg = 0x36004,
2546 .enable_reg = 0x36004,
2547 .enable_mask = BIT(0),
2556 .halt_reg = 0x3600c,
2559 .enable_reg = 0x3600c,
2560 .enable_mask = BIT(0),
2569 .halt_reg = 0x36008,
2572 .enable_reg = 0x36008,
2573 .enable_mask = BIT(0),
2587 .halt_reg = 0x7500c,
2590 .enable_reg = 0x7500c,
2591 .enable_mask = BIT(0),
2600 .halt_reg = 0x75008,
2603 .enable_reg = 0x75008,
2604 .enable_mask = BIT(0),
2618 .halt_reg = 0x7600c,
2621 .enable_reg = 0x7600c,
2622 .enable_mask = BIT(0),
2631 .halt_reg = 0x76040,
2634 .enable_reg = 0x76040,
2635 .enable_mask = BIT(0),
2644 .halt_reg = 0x75014,
2647 .enable_reg = 0x75014,
2648 .enable_mask = BIT(0),
2657 .halt_reg = 0x7605c,
2660 .enable_reg = 0x7605c,
2661 .enable_mask = BIT(0),
2670 .halt_reg = 0x75010,
2673 .enable_reg = 0x75010,
2674 .enable_mask = BIT(0),
2683 .halt_reg = 0x76008,
2686 .enable_reg = 0x76008,
2687 .enable_mask = BIT(0),
2701 .halt_reg = 0xf008,
2704 .enable_reg = 0xf008,
2705 .enable_mask = BIT(0),
2719 .halt_reg = 0xf010,
2722 .enable_reg = 0xf010,
2723 .enable_mask = BIT(0),
2737 .halt_reg = 0xf00c,
2740 .enable_reg = 0xf00c,
2741 .enable_mask = BIT(0),
2750 .halt_reg = 0x50000,
2753 .enable_reg = 0x50000,
2754 .enable_mask = BIT(0),
2768 .halt_reg = 0x50004,
2771 .enable_reg = 0x50004,
2772 .enable_mask = BIT(0),
2781 .halt_reg = 0x6a004,
2784 .enable_reg = 0x6a004,
2785 .enable_mask = BIT(0),
2794 .halt_reg = 0x88000,
2796 .enable_reg = 0x88000,
2797 .enable_mask = BIT(0),
2810 .halt_reg = 0x88004,
2812 .enable_reg = 0x88004,
2813 .enable_mask = BIT(0),
2826 .halt_reg = 0x88008,
2828 .enable_reg = 0x88008,
2829 .enable_mask = BIT(0),
2842 .halt_reg = 0x8800c,
2844 .enable_reg = 0x8800c,
2845 .enable_mask = BIT(0),
2858 .halt_reg = 0x88014,
2860 .enable_reg = 0x88014,
2861 .enable_mask = BIT(0),
2874 .halt_reg = 0x4300c,
2877 .enable_reg = 0x4300c,
2878 .enable_mask = BIT(0),
2887 .halt_reg = 0x83010,
2890 .enable_reg = 0x83010,
2891 .enable_mask = BIT(0),
2900 .halt_reg = 0x63018,
2903 .enable_reg = 0x63018,
2904 .enable_mask = BIT(0),
2913 .halt_reg = 0x6300c,
2916 .enable_reg = 0x6300c,
2917 .enable_mask = BIT(0),
2926 .halt_reg = 0x7D010,
2928 .enable_reg = 0x7D010,
2929 .enable_mask = BIT(0),
2938 .halt_reg = 0x7D014,
2940 .enable_reg = 0x7D014,
2941 .enable_mask = BIT(0),
2950 .halt_reg = 0x8A040,
2952 .enable_reg = 0x8A040,
2953 .enable_mask = BIT(0),
2963 .gdscr = 0x6b004,
2964 .gds_hw_ctrl = 0x0,
2973 .gdscr = 0x75004,
2974 .gds_hw_ctrl = 0x0,
2983 .gdscr = 0xf004,
2984 .gds_hw_ctrl = 0x0,
2994 .gdscr = 0x7d034,
2995 .gds_hw_ctrl = 0x0,
3004 .gdscr = 0x7d038,
3005 .gds_hw_ctrl = 0x0,
3207 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3208 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3209 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3210 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3211 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3212 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3213 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3214 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3215 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3216 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3217 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3218 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3219 [GCC_PCIE_0_BCR] = { 0x6b000 },
3220 [GCC_PDM_BCR] = { 0x33000 },
3221 [GCC_SDCC2_BCR] = { 0x14000 },
3222 [GCC_SDCC4_BCR] = { 0x16000 },
3223 [GCC_TSIF_BCR] = { 0x36000 },
3224 [GCC_UFS_BCR] = { 0x75000 },
3225 [GCC_USB_30_BCR] = { 0xf000 },
3226 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3227 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3228 [GCC_AHB2PHY_EAST_BCR] = { 0x7000 },
3229 [GCC_IMEM_BCR] = { 0x8000 },
3230 [GCC_PIMEM_BCR] = { 0xa000 },
3231 [GCC_MMSS_BCR] = { 0xb000 },
3232 [GCC_QDSS_BCR] = { 0xc000 },
3233 [GCC_WCSS_BCR] = { 0x11000 },
3234 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3235 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3236 [GCC_BLSP1_BCR] = { 0x17000 },
3237 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3238 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3239 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3240 [GCC_CM_PHY_REFGEN1_BCR] = { 0x22000 },
3241 [GCC_CM_PHY_REFGEN2_BCR] = { 0x24000 },
3242 [GCC_BLSP2_BCR] = { 0x25000 },
3243 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3244 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3245 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3246 [GCC_SRAM_SENSOR_BCR] = { 0x2d000 },
3247 [GCC_PRNG_BCR] = { 0x34000 },
3248 [GCC_TSIF_0_RESET] = { 0x36024 },
3249 [GCC_TSIF_1_RESET] = { 0x36028 },
3250 [GCC_TCSR_BCR] = { 0x37000 },
3251 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3252 [GCC_MSG_RAM_BCR] = { 0x39000 },
3253 [GCC_TLMM_BCR] = { 0x3a000 },
3254 [GCC_MPM_BCR] = { 0x3b000 },
3255 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3256 [GCC_SPMI_BCR] = { 0x3f000 },
3257 [GCC_SPDM_BCR] = { 0x40000 },
3258 [GCC_CE1_BCR] = { 0x41000 },
3259 [GCC_BIMC_BCR] = { 0x44000 },
3260 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3261 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49008 },
3262 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49010 },
3263 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49018 },
3264 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3265 [GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR] = { 0x4a004 },
3266 [GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR] = { 0x4a00c },
3267 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3268 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3269 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3270 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3271 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3272 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3273 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3274 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3275 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3276 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3277 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3278 [GCC_USB3_PHY_BCR] = { 0x50020 },
3279 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3280 [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
3281 [GCC_SSC_BCR] = { 0x63000 },
3282 [GCC_SSC_RESET] = { 0x63020 },
3283 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3284 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
3285 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3286 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
3287 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3288 [GCC_PCIE_PHY_NOCSR_COM_PHY_BCR] = { 0x6f00c },
3289 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f010 },
3290 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3291 [GCC_GPU_BCR] = { 0x71000 },
3292 [GCC_SPSS_BCR] = { 0x72000 },
3293 [GCC_OBT_ODT_BCR] = { 0x73000 },
3294 [GCC_MSS_RESTART] = { 0x79000 },
3295 [GCC_VS_BCR] = { 0x7a000 },
3296 [GCC_MSS_VS_RESET] = { 0x7a100 },
3297 [GCC_GPU_VS_RESET] = { 0x7a104 },
3298 [GCC_APC0_VS_RESET] = { 0x7a108 },
3299 [GCC_APC1_VS_RESET] = { 0x7a10c },
3300 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3301 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3302 [GCC_CNOC_BUS_TIMEOUT10_BCR] = { 0x80010 },
3303 [GCC_CNOC_BUS_TIMEOUT11_BCR] = { 0x80018 },
3304 [GCC_CNOC_BUS_TIMEOUT12_BCR] = { 0x80020 },
3305 [GCC_CNOC_BUS_TIMEOUT13_BCR] = { 0x80028 },
3306 [GCC_CNOC_BUS_TIMEOUT14_BCR] = { 0x80030 },
3307 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80038 },
3308 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3309 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3310 [GCC_DCC_BCR] = { 0x84000 },
3311 [GCC_QREFS_VBG_CAL_BCR] = { 0x88028 },
3312 [GCC_IPA_BCR] = { 0x89000 },
3313 [GCC_GLM_BCR] = { 0x8b000 },
3314 [GCC_SKL_BCR] = { 0x8c000 },
3315 [GCC_MSMPU_BCR] = { 0x8d000 },
3322 .max_register = 0x8f000,
3349 ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); in gcc_msm8998_probe()
3354 regmap_write(regmap, GCC_MMSS_MISC, 0x10003); in gcc_msm8998_probe()
3355 regmap_write(regmap, GCC_GPU_MISC, 0x10003); in gcc_msm8998_probe()