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/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78230.dtsi26 #size-cells = <0>;
29 cpu@0 {
32 reg = <0>;
33 clocks = <&cpuclk 0>;
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
61 bus-range = <0x00 0xff>;
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
[all …]
H A Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-xp-mv78460.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Damlogic,g12a-mdio-mux.yaml53 reg = <0x4c000 0xa4>;
58 #size-cells = <0>;
60 mdio@0 {
61 reg = <0>;
63 #size-cells = <0>;
69 #size-cells = <0>;
/linux/arch/powerpc/boot/dts/fsl/
H A Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_color_regs.h12 #define _PALETTE_A 0xa000
13 #define _PALETTE_B 0xa800
14 #define _CHV_PALETTE_C 0xc000
18 #define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
22 #define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
32 #define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
40 #define _PIPEAGCMAX 0x70010
41 #define _PIPEBGCMAX 0x71010
45 #define _LGC_PALETTE_A 0x4a000
46 #define _LGC_PALETTE_B 0x4a800
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_main.c17 #define XTR_EOF_0 0x00000080U
18 #define XTR_EOF_1 0x01000080U
19 #define XTR_EOF_2 0x02000080U
20 #define XTR_EOF_3 0x03000080U
21 #define XTR_PRUNED 0x04000080U
22 #define XTR_ABORT 0x05000080U
23 #define XTR_ESCAPE 0x06000080U
24 #define XTR_NOT_READY 0x07000080U
42 { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */
43 { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-nord.c46 .offset = 0x0,
49 .enable_reg = 0x9d020,
50 .enable_mask = BIT(0),
63 { 0x1, 2 },
68 .offset = 0x0,
85 { P_BI_TCXO, 0 },
97 { P_BI_TCXO, 0 },
107 { P_BI_TCXO, 0 },
121 { P_BI_TCXO, 0 },
131 .reg = 0x49094,
[all …]
H A Dgcc-msm8909.c52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.c55 * at the time it indicated completion is stored there. Returns 0 if the
67 return 0; in t4_wait_op_done_val()
69 if (--attempts == 0) in t4_wait_op_done_val()
168 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a in t4_hw_pci_read_cfg4()
170 * ENABLE is 0 so a simple register write is easier than a in t4_hw_pci_read_cfg4()
173 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()
248 log->cursor = 0; in t4_record_mbox()
250 for (i = 0; i < size / 8; i++) in t4_record_mbox()
253 entry->cmd[i++] = 0; in t4_record_mbox()
278 * The return value is 0 on success or a negative errno on failure. A
[all …]