Lines Matching +full:0 +full:x4c000
54 .offset = 0x21000,
57 .enable_reg = 0x45008,
72 .offset = 0x21000,
75 .enable_reg = 0x45000,
76 .enable_mask = BIT(0),
89 .offset = 0x21000,
102 { 700000000, 1400000000, 0 },
107 .config_ctl_val = 0x4001055b,
108 .early_output_mask = 0,
114 .offset = 0x22000,
132 .offset = 0x22000,
146 .offset = 0x24000,
149 .enable_reg = 0x45000,
163 .offset = 0x24000,
176 .l_reg = 0x37004,
177 .m_reg = 0x37008,
178 .n_reg = 0x3700c,
179 .config_reg = 0x37014,
180 .mode_reg = 0x37000,
181 .status_reg = 0x3701c,
194 .enable_reg = 0x45000,
207 { P_XO, 0 },
212 { P_XO, 0 },
222 { P_XO, 0 },
236 { P_XO, 0 },
250 F(19200000, P_XO, 1, 0, 0),
251 F(50000000, P_GPLL0, 16, 0, 0),
252 F(100000000, P_GPLL0, 8, 0, 0),
253 F(133330000, P_GPLL0, 6, 0, 0),
258 .cmd_rcgr = 0x46000,
271 F(19200000, P_XO, 1, 0, 0),
272 F(50000000, P_GPLL0, 16, 0, 0),
277 .cmd_rcgr = 0x03000,
290 .cmd_rcgr = 0x04000,
303 .cmd_rcgr = 0x05000,
316 .cmd_rcgr = 0x0c00c,
329 .cmd_rcgr = 0x0d000,
342 .cmd_rcgr = 0x0f000,
356 F(4800000, P_XO, 4, 0, 0),
357 F(9600000, P_XO, 2, 0, 0),
359 F(19200000, P_XO, 1, 0, 0),
361 F(50000000, P_GPLL0, 16, 0, 0),
366 .cmd_rcgr = 0x03014,
380 .cmd_rcgr = 0x04024,
394 .cmd_rcgr = 0x05024,
408 .cmd_rcgr = 0x0c024,
422 .cmd_rcgr = 0x0d014,
436 .cmd_rcgr = 0x0f024,
454 F(19200000, P_XO, 1, 0, 0),
470 .cmd_rcgr = 0x02044,
484 .cmd_rcgr = 0x03034,
498 .cmd_rcgr = 0x0c044,
512 .cmd_rcgr = 0x0d034,
526 { P_XO, 0 },
536 .cmd_rcgr = 0x4d044,
549 F(100000000, P_GPLL0, 8, 0, 0),
550 F(160000000, P_GPLL0, 5, 0, 0),
551 F(200000000, P_GPLL0, 4, 0, 0),
556 .cmd_rcgr = 0x54000,
570 .cmd_rcgr = 0x55000,
585 F(61540000, P_GPLL0, 13, 0, 0),
586 F(80000000, P_GPLL0, 10, 0, 0),
591 .cmd_rcgr = 0x5a000,
604 F(19200000, P_XO, 1, 0, 0),
610 .cmd_rcgr = 0x51000,
624 { P_XO, 0 },
636 F(133330000, P_GPLL0, 6, 0, 0),
637 F(160000000, P_GPLL0, 5, 0, 0),
638 F(266670000, P_GPLL0, 3, 0, 0),
639 F(308570000, P_GPLL0, 3.5, 0, 0),
640 F(320000000, P_GPLL0, 2.5, 0, 0),
641 F(360000000, P_GPLL6, 3, 0, 0),
646 .cmd_rcgr = 0x58018,
659 F(50000000, P_GPLL0, 16, 0, 0),
660 F(80000000, P_GPLL0, 10, 0, 0),
661 F(100000000, P_GPLL0, 8, 0, 0),
662 F(160000000, P_GPLL0, 5, 0, 0),
667 .cmd_rcgr = 0x16004,
680 F(100000000, P_GPLL0, 8, 0, 0),
681 F(160000000, P_GPLL0, 5, 0, 0),
682 F(200000000, P_GPLL0, 4, 0, 0),
687 .cmd_rcgr = 0x4e020,
700 .cmd_rcgr = 0x4f020,
713 .cmd_rcgr = 0x3c020,
726 F(100000000, P_GPLL0, 8, 0, 0),
727 F(160000000, P_GPLL0, 5, 0, 0),
728 F(200000000, P_GPLL0, 4, 0, 0),
729 F(266670000, P_GPLL0, 3, 0, 0),
734 .cmd_rcgr = 0x4e000,
747 .cmd_rcgr = 0x4f000,
760 F(19200000, P_XO, 1, 0, 0),
765 .cmd_rcgr = 0x4d05c,
778 { P_XO, 0 },
785 { P_XO, 0 },
799 F(19200000, P_XO, 1, 0, 0),
800 F(50000000, P_GPLL0, 16, 0, 0),
801 F(80000000, P_GPLL0, 10, 0, 0),
802 F(100000000, P_GPLL0, 8, 0, 0),
803 F(160000000, P_GPLL0, 5, 0, 0),
804 F(200000000, P_GPLL0, 4, 0, 0),
805 F(228570000, P_GPLL0, 3.5, 0, 0),
806 F(240000000, P_GPLL6, 4.5, 0, 0),
807 F(266670000, P_GPLL0, 3, 0, 0),
808 F(270000000, P_GPLL6, 4, 0, 0),
809 F(320000000, P_GPLL0, 2.5, 0, 0),
810 F(400000000, P_GPLL0, 2, 0, 0),
811 F(465000000, P_GPLL3, 1, 0, 0),
812 F(484800000, P_GPLL3, 1, 0, 0),
813 F(500000000, P_GPLL3, 1, 0, 0),
814 F(523200000, P_GPLL3, 1, 0, 0),
815 F(550000000, P_GPLL3, 1, 0, 0),
816 F(598000000, P_GPLL3, 1, 0, 0),
821 .cmd_rcgr = 0x59000,
835 F(19200000, P_XO, 1, 0, 0),
840 .cmd_rcgr = 0x08004,
854 .cmd_rcgr = 0x09004,
868 .cmd_rcgr = 0x0a004,
882 F(133330000, P_GPLL0, 6, 0, 0),
883 F(266670000, P_GPLL0, 3, 0, 0),
884 F(320000000, P_GPLL0, 2.5, 0, 0),
889 .cmd_rcgr = 0x57000,
902 F(19200000, P_XO, 1, 0, 0),
904 F(66667000, P_GPLL0, 12, 0, 0),
909 .cmd_rcgr = 0x52000,
923 .cmd_rcgr = 0x53000,
937 .cmd_rcgr = 0x5c000,
951 F(50000000, P_GPLL0, 16, 0, 0),
952 F(80000000, P_GPLL0, 10, 0, 0),
953 F(100000000, P_GPLL0, 8, 0, 0),
954 F(145450000, P_GPLL0, 5.5, 0, 0),
955 F(160000000, P_GPLL0, 5, 0, 0),
956 F(177780000, P_GPLL0, 4.5, 0, 0),
957 F(200000000, P_GPLL0, 4, 0, 0),
958 F(266670000, P_GPLL0, 3, 0, 0),
959 F(320000000, P_GPLL0, 2.5, 0, 0),
964 .cmd_rcgr = 0x4d014,
977 { P_XO, 0 },
987 .cmd_rcgr = 0x4d000,
1001 F(64000000, P_GPLL0, 12.5, 0, 0),
1006 .cmd_rcgr = 0x44010,
1019 F(100000000, P_GPLL0, 8, 0, 0),
1020 F(200000000, P_GPLL0, 4, 0, 0),
1025 .cmd_rcgr = 0x5d000,
1038 { P_XO, 0 },
1054 F(50000000, P_GPLL0, 16, 0, 0),
1055 F(100000000, P_GPLL0, 8, 0, 0),
1056 F(177770000, P_GPLL0, 4.5, 0, 0),
1057 F(192000000, P_GPLL4, 6, 0, 0),
1058 F(200000000, P_GPLL0, 4, 0, 0),
1059 F(384000000, P_GPLL4, 3, 0, 0),
1064 .cmd_rcgr = 0x42004,
1082 F(50000000, P_GPLL0, 16, 0, 0),
1083 F(100000000, P_GPLL0, 8, 0, 0),
1084 F(177770000, P_GPLL0, 4.5, 0, 0),
1085 F(200000000, P_GPLL0, 4, 0, 0),
1090 .cmd_rcgr = 0x43004,
1104 F(80000000, P_GPLL0, 10, 0, 0),
1105 F(100000000, P_GPLL0, 8, 0, 0),
1106 F(133330000, P_GPLL0, 6, 0, 0),
1107 F(177780000, P_GPLL0, 4.5, 0, 0),
1112 .cmd_rcgr = 0x41010,
1125 F(133330000, P_GPLL0, 6, 0, 0),
1126 F(180000000, P_GPLL6, 6, 0, 0),
1127 F(228570000, P_GPLL0, 3.5, 0, 0),
1128 F(266670000, P_GPLL0, 3, 0, 0),
1129 F(308570000, P_GPLL6, 3.5, 0, 0),
1130 F(329140000, P_GPLL4, 3.5, 0, 0),
1131 F(360000000, P_GPLL6, 3, 0, 0),
1136 .cmd_rcgr = 0x4c000,
1149 F(50000000, P_GPLL0, 16, 0, 0),
1150 F(80000000, P_GPLL0, 10, 0, 0),
1151 F(100000000, P_GPLL0, 8, 0, 0),
1152 F(133330000, P_GPLL0, 6, 0, 0),
1153 F(160000000, P_GPLL0, 5, 0, 0),
1154 F(200000000, P_GPLL0, 4, 0, 0),
1155 F(266670000, P_GPLL0, 3, 0, 0),
1156 F(308570000, P_GPLL6, 3.5, 0, 0),
1157 F(320000000, P_GPLL0, 2.5, 0, 0),
1158 F(329140000, P_GPLL4, 3.5, 0, 0),
1159 F(360000000, P_GPLL6, 3, 0, 0),
1164 .cmd_rcgr = 0x58000,
1177 .cmd_rcgr = 0x58054,
1190 F(19200000, P_XO, 1, 0, 0),
1195 .cmd_rcgr = 0x4d02c,
1208 .halt_reg = 0x12018,
1211 .enable_reg = 0x4500c,
1221 .halt_reg = 0x59034,
1224 .enable_reg = 0x59034,
1225 .enable_mask = BIT(0),
1234 .halt_reg = 0x59030,
1237 .enable_reg = 0x59030,
1238 .enable_mask = BIT(0),
1247 .halt_reg = 0x01008,
1250 .enable_reg = 0x45004,
1260 .halt_reg = 0x0b008,
1263 .enable_reg = 0x45004,
1273 .halt_reg = 0x03010,
1276 .enable_reg = 0x03010,
1277 .enable_mask = BIT(0),
1291 .halt_reg = 0x04020,
1294 .enable_reg = 0x04020,
1295 .enable_mask = BIT(0),
1309 .halt_reg = 0x05020,
1312 .enable_reg = 0x05020,
1313 .enable_mask = BIT(0),
1327 .halt_reg = 0x0c008,
1330 .enable_reg = 0x0c008,
1331 .enable_mask = BIT(0),
1345 .halt_reg = 0x0d010,
1348 .enable_reg = 0x0d010,
1349 .enable_mask = BIT(0),
1363 .halt_reg = 0x0f020,
1366 .enable_reg = 0x0f020,
1367 .enable_mask = BIT(0),
1381 .halt_reg = 0x0300c,
1384 .enable_reg = 0x0300c,
1385 .enable_mask = BIT(0),
1399 .halt_reg = 0x0401c,
1402 .enable_reg = 0x0401c,
1403 .enable_mask = BIT(0),
1417 .halt_reg = 0x0501c,
1420 .enable_reg = 0x0501c,
1421 .enable_mask = BIT(0),
1435 .halt_reg = 0x0c004,
1438 .enable_reg = 0x0c004,
1439 .enable_mask = BIT(0),
1453 .halt_reg = 0x0d00c,
1456 .enable_reg = 0x0d00c,
1457 .enable_mask = BIT(0),
1471 .halt_reg = 0x0f01c,
1474 .enable_reg = 0x0f01c,
1475 .enable_mask = BIT(0),
1489 .halt_reg = 0x0203c,
1492 .enable_reg = 0x0203c,
1493 .enable_mask = BIT(0),
1507 .halt_reg = 0x0302c,
1510 .enable_reg = 0x0302c,
1511 .enable_mask = BIT(0),
1525 .halt_reg = 0x0c03c,
1528 .enable_reg = 0x0c03c,
1529 .enable_mask = BIT(0),
1543 .halt_reg = 0x0d02c,
1546 .enable_reg = 0x0d02c,
1547 .enable_mask = BIT(0),
1561 .halt_reg = 0x1300c,
1564 .enable_reg = 0x45004,
1574 .halt_reg = 0x56004,
1577 .enable_reg = 0x56004,
1578 .enable_mask = BIT(0),
1587 .halt_reg = 0x5101c,
1590 .enable_reg = 0x5101c,
1591 .enable_mask = BIT(0),
1605 .halt_reg = 0x51018,
1608 .enable_reg = 0x51018,
1609 .enable_mask = BIT(0),
1623 .halt_reg = 0x58040,
1626 .enable_reg = 0x58040,
1627 .enable_mask = BIT(0),
1641 .halt_reg = 0x5803c,
1644 .enable_reg = 0x5803c,
1645 .enable_mask = BIT(0),
1659 .halt_reg = 0x4e040,
1662 .enable_reg = 0x4e040,
1663 .enable_mask = BIT(0),
1677 .halt_reg = 0x4f040,
1680 .enable_reg = 0x4f040,
1681 .enable_mask = BIT(0),
1695 .halt_reg = 0x3c040,
1698 .enable_reg = 0x3c040,
1699 .enable_mask = BIT(0),
1713 .halt_reg = 0x4e03c,
1716 .enable_reg = 0x4e03c,
1717 .enable_mask = BIT(0),
1731 .halt_reg = 0x4f03c,
1734 .enable_reg = 0x4f03c,
1735 .enable_mask = BIT(0),
1749 .halt_reg = 0x3c03c,
1752 .enable_reg = 0x3c03c,
1753 .enable_mask = BIT(0),
1767 .halt_reg = 0x4e048,
1770 .enable_reg = 0x4e048,
1771 .enable_mask = BIT(0),
1785 .halt_reg = 0x4f048,
1788 .enable_reg = 0x4f048,
1789 .enable_mask = BIT(0),
1803 .halt_reg = 0x3c048,
1806 .enable_reg = 0x3c048,
1807 .enable_mask = BIT(0),
1821 .halt_reg = 0x4e01c,
1824 .enable_reg = 0x4e01c,
1825 .enable_mask = BIT(0),
1839 .halt_reg = 0x4f01c,
1842 .enable_reg = 0x4f01c,
1843 .enable_mask = BIT(0),
1857 .halt_reg = 0x4e058,
1860 .enable_reg = 0x4e058,
1861 .enable_mask = BIT(0),
1875 .halt_reg = 0x4f058,
1878 .enable_reg = 0x4f058,
1879 .enable_mask = BIT(0),
1893 .halt_reg = 0x3c058,
1896 .enable_reg = 0x3c058,
1897 .enable_mask = BIT(0),
1911 .halt_reg = 0x4e050,
1914 .enable_reg = 0x4e050,
1915 .enable_mask = BIT(0),
1929 .halt_reg = 0x4f050,
1932 .enable_reg = 0x4f050,
1933 .enable_mask = BIT(0),
1947 .halt_reg = 0x3c050,
1950 .enable_reg = 0x3c050,
1951 .enable_mask = BIT(0),
1965 .halt_reg = 0x58050,
1968 .enable_reg = 0x58050,
1969 .enable_mask = BIT(0),
1983 .halt_reg = 0x58074,
1986 .enable_reg = 0x58074,
1987 .enable_mask = BIT(0),
2001 .halt_reg = 0x54018,
2004 .enable_reg = 0x54018,
2005 .enable_mask = BIT(0),
2019 .halt_reg = 0x55018,
2022 .enable_reg = 0x55018,
2023 .enable_mask = BIT(0),
2037 .halt_reg = 0x50004,
2040 .enable_reg = 0x50004,
2041 .enable_mask = BIT(0),
2055 .halt_reg = 0x57020,
2058 .enable_reg = 0x57020,
2059 .enable_mask = BIT(0),
2073 .halt_reg = 0x57024,
2076 .enable_reg = 0x57024,
2077 .enable_mask = BIT(0),
2091 .halt_reg = 0x57028,
2094 .enable_reg = 0x57028,
2095 .enable_mask = BIT(0),
2104 .halt_reg = 0x52018,
2107 .enable_reg = 0x52018,
2108 .enable_mask = BIT(0),
2122 .halt_reg = 0x53018,
2125 .enable_reg = 0x53018,
2126 .enable_mask = BIT(0),
2140 .halt_reg = 0x5c018,
2143 .enable_reg = 0x5c018,
2144 .enable_mask = BIT(0),
2158 .halt_reg = 0x5600c,
2161 .enable_reg = 0x5600c,
2162 .enable_mask = BIT(0),
2176 .halt_reg = 0x5a014,
2179 .enable_reg = 0x5a014,
2180 .enable_mask = BIT(0),
2194 .halt_reg = 0x58044,
2197 .enable_reg = 0x58044,
2198 .enable_mask = BIT(0),
2212 .halt_reg = 0x58048,
2215 .enable_reg = 0x58048,
2216 .enable_mask = BIT(0),
2225 .halt_reg = 0x58038,
2228 .enable_reg = 0x58038,
2229 .enable_mask = BIT(0),
2243 .halt_reg = 0x58060,
2246 .enable_reg = 0x58060,
2247 .enable_mask = BIT(0),
2261 .halt_reg = 0x58068,
2264 .enable_reg = 0x58068,
2265 .enable_mask = BIT(0),
2274 .halt_reg = 0x5805c,
2277 .enable_reg = 0x5805c,
2278 .enable_mask = BIT(0),
2292 .halt_reg = 0x12040,
2295 .enable_reg = 0x4500c,
2305 .halt_reg = 0x16024,
2308 .enable_reg = 0x45004,
2309 .enable_mask = BIT(0),
2318 .halt_reg = 0x16020,
2321 .enable_reg = 0x45004,
2331 .halt_reg = 0x1601c,
2334 .enable_reg = 0x45004,
2349 .halt_reg = 0x77004,
2352 .enable_reg = 0x77004,
2353 .enable_mask = BIT(0),
2362 .halt_reg = 0x12010,
2365 .enable_reg = 0x4500c,
2375 .halt_reg = 0x12020,
2378 .enable_reg = 0x4500c,
2388 .halt_reg = 0x12044,
2391 .enable_reg = 0x4500c,
2401 .halt_reg = 0x08000,
2404 .enable_reg = 0x08000,
2405 .enable_mask = BIT(0),
2419 .halt_reg = 0x09000,
2422 .enable_reg = 0x09000,
2423 .enable_mask = BIT(0),
2437 .halt_reg = 0x0a000,
2440 .enable_reg = 0x0a000,
2441 .enable_mask = BIT(0),
2455 .halt_reg = 0x12034,
2458 .enable_reg = 0x4500c,
2468 .halt_reg = 0x1201c,
2471 .enable_reg = 0x4500c,
2481 .halt_reg = 0x4d07c,
2484 .enable_reg = 0x4d07c,
2485 .enable_mask = BIT(0),
2494 .halt_reg = 0x4d080,
2497 .enable_reg = 0x4d080,
2498 .enable_mask = BIT(0),
2507 .halt_reg = 0x4d094,
2510 .enable_reg = 0x4d094,
2511 .enable_mask = BIT(0),
2525 .halt_reg = 0x4d098,
2528 .enable_reg = 0x4d098,
2529 .enable_mask = BIT(0),
2543 .halt_reg = 0x4d088,
2546 .enable_reg = 0x4d088,
2547 .enable_mask = BIT(0),
2561 .halt_reg = 0x4d084,
2564 .enable_reg = 0x4d084,
2565 .enable_mask = BIT(0),
2579 .halt_reg = 0x4d090,
2582 .enable_reg = 0x4d090,
2583 .enable_mask = BIT(0),
2597 .halt_reg = 0x49000,
2600 .enable_reg = 0x49000,
2601 .enable_mask = BIT(0),
2610 .halt_reg = 0x49004,
2613 .enable_reg = 0x49004,
2614 .enable_mask = BIT(0),
2623 .halt_reg = 0x59028,
2626 .enable_reg = 0x59028,
2627 .enable_mask = BIT(0),
2636 .halt_reg = 0x59020,
2639 .enable_reg = 0x59020,
2640 .enable_mask = BIT(0),
2654 .halt_reg = 0x4400c,
2657 .enable_reg = 0x4400c,
2658 .enable_mask = BIT(0),
2672 .halt_reg = 0x44004,
2675 .enable_reg = 0x44004,
2676 .enable_mask = BIT(0),
2685 .halt_reg = 0x13004,
2688 .enable_reg = 0x45004,
2698 .halt_reg = 0x29084,
2701 .enable_reg = 0x45004,
2711 .halt_reg = 0x5d014,
2714 .enable_reg = 0x5d014,
2715 .enable_mask = BIT(0),
2729 .halt_reg = 0x4201c,
2732 .enable_reg = 0x4201c,
2733 .enable_mask = BIT(0),
2742 .halt_reg = 0x4301c,
2745 .enable_reg = 0x4301c,
2746 .enable_mask = BIT(0),
2755 .halt_reg = 0x42018,
2758 .enable_reg = 0x42018,
2759 .enable_mask = BIT(0),
2773 .halt_reg = 0x43018,
2776 .enable_reg = 0x43018,
2777 .enable_mask = BIT(0),
2791 .halt_reg = 0x12038,
2794 .enable_reg = 0x4500c,
2804 .halt_reg = 0x4102c,
2806 .enable_reg = 0x4102c,
2807 .enable_mask = BIT(0),
2816 .halt_reg = 0x41008,
2818 .enable_reg = 0x41008,
2819 .enable_mask = BIT(0),
2828 .halt_reg = 0x41030,
2830 .enable_reg = 0x41030,
2831 .enable_mask = BIT(0),
2840 .halt_reg = 0x41004,
2842 .enable_reg = 0x41004,
2843 .enable_mask = BIT(0),
2857 .halt_reg = 0x4c020,
2860 .enable_reg = 0x4c020,
2861 .enable_mask = BIT(0),
2870 .halt_reg = 0x4c024,
2873 .enable_reg = 0x4c024,
2874 .enable_mask = BIT(0),
2883 .halt_reg = 0x4c02c,
2886 .enable_reg = 0x4c02c,
2887 .enable_mask = BIT(0),
2901 .halt_reg = 0x4c01c,
2904 .enable_reg = 0x4c01c,
2905 .enable_mask = BIT(0),
2919 .halt_reg = 0x12014,
2922 .enable_reg = 0x4500c,
2932 .halt_reg = 0x12090,
2935 .enable_reg = 0x4500c,
2945 .halt_reg = 0x1203c,
2948 .enable_reg = 0x4500c,
2958 .gdscr = 0x4c018,
2959 .cxcs = (unsigned int []){ 0x4c024, 0x4c01c },
2968 .gdscr = 0x4c028,
2969 .cxcs = (unsigned int []){ 0x4c02c },
2979 .gdscr = 0x4d078,
2980 .cxcs = (unsigned int []){ 0x4d080, 0x4d088 },
2989 .gdscr = 0x5701c,
2990 .cxcs = (unsigned int []){ 0x57020, 0x57028 },
2999 .gdscr = 0x58034,
3000 .cxcs = (unsigned int []){ 0x58038, 0x58048, 0x5600c, 0x58050 },
3009 .gdscr = 0x5806c,
3010 .cxcs = (unsigned int []){ 0x5805c, 0x58068, 0x5600c, 0x58074 },
3019 .gdscr = 0x5901c,
3020 .clamp_io_ctrl = 0x5b00c,
3021 .cxcs = (unsigned int []){ 0x59000, 0x59020 },
3031 .gdscr = 0x58078,
3032 .cxcs = (unsigned int []){ 0x5803c, 0x58064 },
3211 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3212 [GCC_MSS_BCR] = { 0x71000 },
3213 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
3214 [GCC_USB_HS_BCR] = { 0x41000 },
3215 [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
3222 .max_register = 0x80000,