18 	{0x420, 0x00},	{0x422, 0x78},	{0x428, 0x0a},	{0x429, 0x10},
19 	{0x430, 0x00},	{0x431, 0x00},	{0x432, 0x00},	{0x433, 0x01},
20 	{0x434, 0x04},	{0x435, 0x05},	{0x436, 0x07},	{0x437, 0x08},
21 	{0x43c, 0x04},	{0x43d, 0x05},	{0x43e, 0x07},	{0x43f, 0x08},
22 	{0x440, 0x5d},	{0x441, 0x01},	{0x442, 0x00},	{0x444, 0x10},
23 	{0x445, 0xf0},	{0x446, 0x0e},	{0x447, 0x1f},	{0x448, 0x00},
24 	{0x449, 0x00},	{0x44a, 0x00},	{0x44b, 0x00},	{0x44c, 0x10},
25 	{0x44d, 0xf0},	{0x44e, 0x0e},	{0x44f, 0x00},	{0x450, 0x00},
26 	{0x451, 0x00},	{0x452, 0x00},	{0x453, 0x00},	{0x480, 0x20},
27 	{0x49c, 0x30},	{0x49d, 0xf0},	{0x49e, 0x03},	{0x49f, 0x3e},
28 	{0x4a0, 0x00},	{0x4a1, 0x00},	{0x4a2, 0x00},	{0x4a3, 0x00},
29 	{0x4a4, 0x15},	{0x4a5, 0xf0},	{0x4a6, 0x01},	{0x4a7, 0x0e},
30 	{0x4a8, 0xe0},	{0x4a9, 0x00},	{0x4aa, 0x00},	{0x4ab, 0x00},
31 	{0x2448, 0x06},	{0x244a, 0x06},	{0x244c, 0x06},	{0x244e, 0x06},
32 	{0x4c7, 0x80},	{0x4c8, 0xff},	{0x4c9, 0x08},	{0x4ca, 0x3c},
33 	{0x4cb, 0x3c},	{0x4cc, 0xff},	{0x4cd, 0xff},	{0x4ce, 0x01},
34 	{0x500, 0x26},	{0x501, 0xa2},	{0x502, 0x2f},	{0x503, 0x00},
35 	{0x504, 0x28},	{0x505, 0xa3},	{0x506, 0x5e},	{0x507, 0x00},
36 	{0x508, 0x2b},	{0x509, 0xa4},	{0x50a, 0x5e},	{0x50b, 0x00},
37 	{0x50c, 0x4f},	{0x50d, 0xa4},	{0x50e, 0x00},	{0x50f, 0x00},
38 	{0x512, 0x1c},	{0x514, 0x0a},	{0x516, 0x0a},	{0x521, 0x2f},
39 	{0x525, 0x0f},	{0x550, 0x10},	{0x551, 0x10},	{0x559, 0x02},
40 	{0x55c, 0x50},	{0x55d, 0xff},	{0x605, 0x30},	{0x608, 0x0e},
41 	{0x609, 0x2a},	{0x60c, 0x18},	{0x620, 0xff},	{0x621, 0xff},
42 	{0x622, 0xff},	{0x623, 0xff},	{0x624, 0xff},	{0x625, 0xff},
43 	{0x626, 0xff},	{0x627, 0xff},	{0x638, 0x50},	{0x63c, 0x0a},
44 	{0x63d, 0x0a},	{0x63e, 0x0e},	{0x63f, 0x0e},	{0x640, 0x40},
45 	{0x642, 0x40},	{0x643, 0x00},	{0x652, 0xc8},	{0x66e, 0x05},
46 	{0x6a0, 0xff},	{0x6a1, 0xff},	{0x6a2, 0xff},	{0x6a3, 0xff},
47 	{0x6a4, 0xff},	{0x6a5, 0xff},	{0x6de, 0x84},	{0x700, 0x21},
48 	{0x701, 0x43},	{0x702, 0x65},	{0x703, 0x87},	{0x708, 0x21},
49 	{0x709, 0x43},	{0x70a, 0x65},	{0x70b, 0x87},	{0x718, 0x40},
50 	{0x7c0, 0x38},	{0x7c2, 0x0f},	{0x7c3, 0xc0},	{0x073, 0x04},
51 	{0x7c4, 0x77},	{0x024, 0xc7},	{0x7ec, 0xff},	{0x7ed, 0xff},
52 	{0x7ee, 0xff},	{0x7ef, 0xff},
53 	{0xffff, 0xff},
58 	{0x800, 0x80006C00},	{0x804, 0x00004001},
59 	{0x808, 0x0000FC00},	{0x80C, 0x00000000},
60 	{0x810, 0x20200322},	{0x814, 0x020C3910},
61 	{0x818, 0x00000385},	{0x81C, 0x07000000},
62 	{0x820, 0x01000100},	{0x824, 0x00390204},
63 	{0x828, 0x01000100},	{0x82C, 0x00390204},
64 	{0x830, 0x25252525},	{0x834, 0x25252525},
65 	{0x838, 0x25252525},	{0x83C, 0x25252525},
66 	{0x840, 0x00010000},	{0x844, 0x00010000},
67 	{0x848, 0x25252525},	{0x84C, 0x25252525},
68 	{0x850, 0x00031FE0},	{0x854, 0x00000000},
69 	{0x858, 0x569A569A},	{0x85C, 0x00400040},
70 	{0x860, 0x66F60000},	{0x864, 0x061F0000},
71 	{0x868, 0x25252525},	{0x86C, 0x25252525},
72 	{0x870, 0x00000300},	{0x874, 0x04003400},
73 	{0x878, 0x08080808},	{0x87C, 0x004F0201},
74 	{0x880, 0xD8001402},	{0x884, 0xC0000120},
75 	{0x888, 0x00000000},	{0x88C, 0xCC0000C0},
76 	{0x890, 0x00000000},	{0x894, 0xFFFFFFFE},
77 	{0x898, 0x40302010},	{0x89C, 0x00706050},
78 	{0x900, 0x00000000},	{0x904, 0x00000023},
79 	{0x908, 0x00000F00},	{0x90C, 0x81121313},
80 	{0x910, 0x024C0000},	{0x914, 0x00000000},
81 	{0x918, 0x00000000},	{0x91C, 0x00000000},
82 	{0x920, 0x00000000},	{0x924, 0x00000000},
83 	{0x928, 0x00000000},	{0x92C, 0x00000000},
84 	{0x930, 0x88000000},	{0x934, 0x00000245},
85 	{0x938, 0x00024588},	{0x93C, 0x00000000},
86 	{0x940, 0x000007FF},	{0x944, 0x3F3F0000},
87 	{0x948, 0x000001A3},	{0x94C, 0x20200008},
88 	{0x950, 0x00338A98},	{0x954, 0x00000000},
89 	{0x958, 0xCBCAD87A},	{0x95C, 0x06EB5735},
90 	{0x960, 0x00000000},	{0x964, 0x00000000},
91 	{0x968, 0x00000000},	{0x96C, 0x00000003},
92 	{0x970, 0x00000000},	{0x974, 0x00000000},
93 	{0x978, 0x00000000},	{0x97C, 0x10030000},
94 	{0x980, 0x00000000},	{0x984, 0x02800280},
95 	{0x988, 0x020A5704},	{0x98C, 0x1461C826},
96 	{0x990, 0x0001469E},	{0x994, 0x008858D1},
97 	{0x998, 0x400086C9},	{0x99C, 0x44444242},
98 	{0x9A0, 0x00000000},	{0x9A4, 0x00000000},
99 	{0x9A8, 0x00000000},	{0x9AC, 0xC0000000},
100 	{0xA00, 0x00D047C8},	{0xA04, 0xC1FF0008},
101 	{0xA08, 0x88838300},	{0xA0C, 0x2E20100F},
102 	{0xA10, 0x9500BB78},	{0xA14, 0x11144028},
103 	{0xA18, 0x00881117},	{0xA1C, 0x89140F00},
104 	{0xA20, 0xE82C0001},	{0xA24, 0x64B80C1C},
105 	{0xA28, 0x00158810},	{0xA2C, 0x10BB8000},
106 	{0xA70, 0x00008000},	{0xA74, 0x80800100},
107 	{0xA78, 0x000089F0},	{0xA7C, 0x225B0606},
108 	{0xA80, 0x20803210},	{0xA84, 0x00200200},
109 	{0xA88, 0x00000000},	{0xA8C, 0x00000000},
110 	{0xA90, 0x00000000},	{0xA94, 0x00000000},
111 	{0xA98, 0x00000000},	{0xA9C, 0x00460000},
112 	{0xAA0, 0x00000000},	{0xAA4, 0x00020014},
113 	{0xAA8, 0xBA0A0008},	{0xAAC, 0x01235667},
114 	{0xAB0, 0x00000000},	{0xAB4, 0x00201402},
115 	{0xAB8, 0x0000001C},	{0xABC, 0x0000F7FF},
116 	{0xAC0, 0xD4C0A742},	{0xAC4, 0x00000000},
117 	{0xAC8, 0x00000F08},	{0xACC, 0x00000F07},
118 	{0xAD0, 0xA1052A10},	{0xAD4, 0x0D9D8452},
119 	{0xAD8, 0x9E024024},	{0xADC, 0x0023C001},
120 	{0xAE0, 0x00000391},	{0xB2C, 0x00000000},
121 	{0xC00, 0x00000080},	{0xC04, 0x6F005433},
122 	{0xC08, 0x000004E4},	{0xC0C, 0x6C6C6C6C},
123 	{0xC10, 0x22000000},	{0xC14, 0x40000100},
124 	{0xC18, 0x22000000},	{0xC1C, 0x40000100},
125 	{0xC20, 0x00000000},	{0xC24, 0x40000100},
126 	{0xC28, 0x00000000},	{0xC2C, 0x40000100},
127 	{0xC30, 0x0401E809},	{0xC34, 0x30000020},
128 	{0xC38, 0x23808080},	{0xC3C, 0x00002F44},
129 	{0xC40, 0x1CF8403F},	{0xC44, 0x000100C7},
130 	{0xC48, 0xEC060106},	{0xC4C, 0x007F037F},
131 	{0xC50, 0x00E48020},	{0xC54, 0x04008017},
132 	{0xC58, 0x00000020},	{0xC5C, 0x00708492},
133 	{0xC60, 0x09280200},	{0xC64, 0x5014838B},
134 	{0xC68, 0x47C006C7},	{0xC6C, 0x00000035},
135 	{0xC70, 0x00001007},	{0xC74, 0x02815269},
136 	{0xC78, 0x0FE07F1F},	{0xC7C, 0x00B91612},
137 	{0xC80, 0x40000100},	{0xC84, 0x32000000},
138 	{0xC88, 0x40000100},	{0xC8C, 0xA0240000},
139 	{0xC90, 0x400E161E},	{0xC94, 0x00000F00},
140 	{0xC98, 0x400E161E},	{0xC9C, 0x0000BDC8},
141 	{0xCA0, 0x00000000},	{0xCA4, 0x098300A0},
142 	{0xCA8, 0x00006B00},	{0xCAC, 0x87F45B1A},
143 	{0xCB0, 0x0000002D},	{0xCB4, 0x00000000},
144 	{0xCB8, 0x00000000},	{0xCBC, 0x28100200},
145 	{0xCC0, 0x0010A3D0},	{0xCC4, 0x00000F7D},
146 	{0xCC8, 0x00000000},	{0xCCC, 0x00000000},
147 	{0xCD0, 0x593659AD},	{0xCD4, 0xB7545121},
148 	{0xCD8, 0x64B22427},	{0xCDC, 0x00766932},
149 	{0xCE0, 0x40201000},	{0xCE4, 0x00000000},
150 	{0xCE8, 0x40E04407},	{0xCEC, 0x2E572000},
151 	{0xD00, 0x000D8780},	{0xD04, 0x40020403},
152 	{0xD08, 0x0002907F},	{0xD0C, 0x20010201},
153 	{0xD10, 0x06288888},	{0xD14, 0x8888367B},
154 	{0xD18, 0x7D806DB3},	{0xD1C, 0x0000007F},
155 	{0xD20, 0x567600B8},	{0xD24, 0x0000018B},
156 	{0xD28, 0xD513FF7D},	{0xD2C, 0xCC979975},
157 	{0xD30, 0x04928000},	{0xD34, 0x40608000},
158 	{0xD38, 0x88DDA000},	{0xD3C, 0x00026EE2},
159 	{0xD50, 0x67270001},	{0xD54, 0x20500000},
160 	{0xD58, 0x16161616},	{0xD5C, 0x71F20064},
161 	{0xD60, 0x4653DA60},	{0xD64, 0x3E718A3C},
162 	{0xD68, 0x00000183},	{0xD7C, 0x00000000},
163 	{0xD80, 0x50000000},	{0xD84, 0x31310400},
164 	{0xD88, 0xF5B50000},	{0xD8C, 0x00000000},
165 	{0xD90, 0x00000000},	{0xD94, 0x44BBBB44},
166 	{0xD98, 0x44BB44FF},	{0xD9C, 0x06033688},
167 	{0xE00, 0x25252525},	{0xE04, 0x25252525},
168 	{0xE08, 0x25252525},	{0xE10, 0x25252525},
169 	{0xE14, 0x25252525},	{0xE18, 0x25252525},
170 	{0xE1C, 0x25252525},	{0xE20, 0x00000000},
171 	{0xE24, 0x00200000},	{0xE28, 0x00000000},
172 	{0xE2C, 0x00000000},	{0xE30, 0x01007C00},
173 	{0xE34, 0x01004800},	{0xE38, 0x10008C0F},
174 	{0xE3C, 0x3C008C0F},	{0xE40, 0x01007C00},
175 	{0xE44, 0x00000000},	{0xE48, 0x00000000},
176 	{0xE4C, 0x00000000},	{0xE50, 0x01007C00},
177 	{0xE54, 0x01004800},	{0xE58, 0x10008C0F},
178 	{0xE5C, 0x3C008C0F},	{0xE60, 0x02100000},
179 	{0xE64, 0xBBBBBBBB},	{0xE68, 0x40404040},
180 	{0xE6C, 0x80408040},	{0xE70, 0x80408040},
181 	{0xE74, 0x40404040},	{0xE78, 0x00400040},
182 	{0xE7C, 0x40404040},	{0xE80, 0x00FF0000},
183 	{0xE84, 0x80408040},	{0xE88, 0x40404040},
184 	{0xE8C, 0x80408040},	{0xED0, 0x80408040},
185 	{0xED4, 0x80408040},	{0xED8, 0x80408040},
186 	{0xEDC, 0xC040C040},	{0xEE0, 0xC040C040},
187 	{0xEE4, 0x00400040},	{0xEE8, 0xD8001402},
188 	{0xEEC, 0xC0000120},	{0xEF0, 0x02000B09},
189 	{0xEF4, 0x00000001},	{0xEF8, 0x00000000},
190 	{0xF00, 0x00000300},	{0xF04, 0x00000002},
191 	{0xF08, 0x00007D0C},	{0xF0C, 0x0000A907},
192 	{0xF10, 0x00005807},	{0xF14, 0x00000003},
193 	{0xF18, 0x07D003E8},	{0xF1C, 0x8000001F},
194 	{0xF20, 0x00000000},	{0xF24, 0x00000000},
195 	{0xF28, 0x00000000},	{0xF2C, 0x00000000},
196 	{0xF30, 0x00000000},	{0xF34, 0x00000000},
197 	{0xF38, 0x00030055},	{0xF3C, 0x0000003A},
198 	{0xF40, 0x00000002},	{0xF44, 0x00000000},
199 	{0xF48, 0x00000000},	{0xF4C, 0x0B000000},
200 	{0xF50, 0x00000000},
201 	{0xffff, 0xffffffff},
205 	{0xC78, 0x0FA0001F}, {0xC78, 0x0FA0011F},
206 	{0xC78, 0x0FA0021F}, {0xC78, 0x0FA0031F},
207 	{0xC78, 0x0FA0041F}, {0xC78, 0x0FA0051F},
208 	{0xC78, 0x0F90061F}, {0xC78, 0x0F80071F},
209 	{0xC78, 0x0F70081F}, {0xC78, 0x0F60091F},
210 	{0xC78, 0x0F500A1F}, {0xC78, 0x0F400B1F},
211 	{0xC78, 0x0F300C1F}, {0xC78, 0x0F200D1F},
212 	{0xC78, 0x0F100E1F}, {0xC78, 0x0F000F1F},
213 	{0xC78, 0x0EF0101F}, {0xC78, 0x0EE0111F},
214 	{0xC78, 0x0ED0121F}, {0xC78, 0x0EC0131F},
215 	{0xC78, 0x0EB0141F}, {0xC78, 0x0EA0151F},
216 	{0xC78, 0x0E90161F}, {0xC78, 0x0E80171F},
217 	{0xC78, 0x0E70181F}, {0xC78, 0x0E60191F},
218 	{0xC78, 0x0E501A1F}, {0xC78, 0x0E401B1F},
219 	{0xC78, 0x0E301C1F}, {0xC78, 0x0C701D1F},
220 	{0xC78, 0x0C601E1F}, {0xC78, 0x0C501F1F},
221 	{0xC78, 0x0C40201F}, {0xC78, 0x0C30211F},
222 	{0xC78, 0x0A60221F}, {0xC78, 0x0A50231F},
223 	{0xC78, 0x0A40241F}, {0xC78, 0x0A30251F},
224 	{0xC78, 0x0860261F}, {0xC78, 0x0850271F},
225 	{0xC78, 0x0840281F}, {0xC78, 0x0830291F},
226 	{0xC78, 0x06702A1F}, {0xC78, 0x06602B1F},
227 	{0xC78, 0x06502C1F}, {0xC78, 0x06402D1F},
228 	{0xC78, 0x06302E1F}, {0xC78, 0x04602F1F},
229 	{0xC78, 0x0450301F}, {0xC78, 0x0440311F},
230 	{0xC78, 0x0430321F}, {0xC78, 0x0260331F},
231 	{0xC78, 0x0250341F}, {0xC78, 0x0240351F},
232 	{0xC78, 0x0230361F}, {0xC78, 0x0050371F},
233 	{0xC78, 0x0040381F}, {0xC78, 0x0030391F},
234 	{0xC78, 0x00203A1F}, {0xC78, 0x00103B1F},
235 	{0xC78, 0x00003C1F}, {0xC78, 0x00003D1F},
236 	{0xC78, 0x00003E1F}, {0xC78, 0x00003F1F},
238 	{0xC78, 0x0FA0401F}, {0xC78, 0x0FA0411F},
239 	{0xC78, 0x0FA0421F}, {0xC78, 0x0FA0431F},
240 	{0xC78, 0x0F90441F}, {0xC78, 0x0F80451F},
241 	{0xC78, 0x0F70461F}, {0xC78, 0x0F60471F},
242 	{0xC78, 0x0F50481F}, {0xC78, 0x0F40491F},
243 	{0xC78, 0x0F304A1F}, {0xC78, 0x0F204B1F},
244 	{0xC78, 0x0F104C1F}, {0xC78, 0x0F004D1F},
245 	{0xC78, 0x0EF04E1F}, {0xC78, 0x0EE04F1F},
246 	{0xC78, 0x0ED0501F}, {0xC78, 0x0EC0511F},
247 	{0xC78, 0x0EB0521F}, {0xC78, 0x0EA0531F},
248 	{0xC78, 0x0E90541F}, {0xC78, 0x0E80551F},
249 	{0xC78, 0x0E70561F}, {0xC78, 0x0E60571F},
250 	{0xC78, 0x0E50581F}, {0xC78, 0x0E40591F},
251 	{0xC78, 0x0E305A1F}, {0xC78, 0x0E205B1F},
252 	{0xC78, 0x0E105C1F}, {0xC78, 0x0C505D1F},
253 	{0xC78, 0x0C405E1F}, {0xC78, 0x0C305F1F},
254 	{0xC78, 0x0C20601F}, {0xC78, 0x0C10611F},
255 	{0xC78, 0x0A40621F}, {0xC78, 0x0A30631F},
256 	{0xC78, 0x0A20641F}, {0xC78, 0x0A10651F},
257 	{0xC78, 0x0840661F}, {0xC78, 0x0830671F},
258 	{0xC78, 0x0820681F}, {0xC78, 0x0810691F},
259 	{0xC78, 0x06506A1F}, {0xC78, 0x06406B1F},
260 	{0xC78, 0x06306C1F}, {0xC78, 0x06206D1F},
261 	{0xC78, 0x06106E1F}, {0xC78, 0x04406F1F},
262 	{0xC78, 0x0430701F}, {0xC78, 0x0420711F},
263 	{0xC78, 0x0410721F}, {0xC78, 0x0240731F},
264 	{0xC78, 0x0230741F}, {0xC78, 0x0220751F},
265 	{0xC78, 0x0210761F}, {0xC78, 0x0030771F},
266 	{0xC78, 0x0020781F}, {0xC78, 0x0010791F},
267 	{0xC78, 0x00007A1F}, {0xC78, 0x00007B1F},
268 	{0xC78, 0x00007C1F}, {0xC78, 0x00007D1F},
269 	{0xC78, 0x00007E1F}, {0xC78, 0x00007F1F},
271 	{0xC78, 0x0FA0801F}, {0xC78, 0x0FA0811F},
272 	{0xC78, 0x0FA0821F}, {0xC78, 0x0FA0831F},
273 	{0xC78, 0x0FA0841F}, {0xC78, 0x0FA0851F},
274 	{0xC78, 0x0F90861F}, {0xC78, 0x0F80871F},
275 	{0xC78, 0x0F70881F}, {0xC78, 0x0F60891F},
276 	{0xC78, 0x0F508A1F}, {0xC78, 0x0F408B1F},
277 	{0xC78, 0x0F308C1F}, {0xC78, 0x0F208D1F},
278 	{0xC78, 0x0F108E1F}, {0xC78, 0x0B908F1F},
279 	{0xC78, 0x0B80901F}, {0xC78, 0x0B70911F},
280 	{0xC78, 0x0B60921F}, {0xC78, 0x0B50931F},
281 	{0xC78, 0x0B40941F}, {0xC78, 0x0B30951F},
282 	{0xC78, 0x0B20961F}, {0xC78, 0x0B10971F},
283 	{0xC78, 0x0B00981F}, {0xC78, 0x0AF0991F},
284 	{0xC78, 0x0AE09A1F}, {0xC78, 0x0AD09B1F},
285 	{0xC78, 0x0AC09C1F}, {0xC78, 0x0AB09D1F},
286 	{0xC78, 0x0AA09E1F}, {0xC78, 0x0A909F1F},
287 	{0xC78, 0x0A80A01F}, {0xC78, 0x0A70A11F},
288 	{0xC78, 0x0A60A21F}, {0xC78, 0x0A50A31F},
289 	{0xC78, 0x0A40A41F}, {0xC78, 0x0A30A51F},
290 	{0xC78, 0x0A20A61F}, {0xC78, 0x0A10A71F},
291 	{0xC78, 0x0A00A81F}, {0xC78, 0x0830A91F},
292 	{0xC78, 0x0820AA1F}, {0xC78, 0x0810AB1F},
293 	{0xC78, 0x0800AC1F}, {0xC78, 0x0640AD1F},
294 	{0xC78, 0x0630AE1F}, {0xC78, 0x0620AF1F},
295 	{0xC78, 0x0610B01F}, {0xC78, 0x0600B11F},
296 	{0xC78, 0x0430B21F}, {0xC78, 0x0420B31F},
297 	{0xC78, 0x0410B41F}, {0xC78, 0x0400B51F},
298 	{0xC78, 0x0230B61F}, {0xC78, 0x0220B71F},
299 	{0xC78, 0x0210B81F}, {0xC78, 0x0200B91F},
300 	{0xC78, 0x0000BA1F}, {0xC78, 0x0000BB1F},
301 	{0xC78, 0x0000BC1F}, {0xC78, 0x0000BD1F},
302 	{0xC78, 0x0000BE1F}, {0xC78, 0x0000BF1F},
303 	{0xC50, 0x00E48024}, {0xC50, 0x00E48020},
304 	{0xffff, 0xffffffff}
308 	{0x00, 0x30000}, {0x18, 0x0FC07}, {0x81, 0x0FC00}, {0x82, 0x003C0},
309 	{0x84, 0x00005}, {0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010},
310 	{0x8E, 0x64540}, {0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007},
311 	{0x53, 0x10061}, {0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6},
312 	{0x57, 0x2CC00}, {0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006},
313 	{0x5C, 0x00015}, {0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180},
314 	{0xEF, 0x00002}, {0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A},
315 	{0xEF, 0x00000}, {0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008},
316 	{0xEF, 0x00800}, {0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848},
317 	{0x33, 0x0C84B}, {0x33, 0x1088A}, {0x33, 0x14C50}, {0x33, 0x18C8E},
318 	{0x33, 0x1CCCD}, {0x33, 0x20CD0}, {0x33, 0x24CD3}, {0x33, 0x28CD6},
319 	{0x33, 0x4002B}, {0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849},
320 	{0x33, 0x50888}, {0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC},
321 	{0x33, 0x60CCF}, {0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000},
322 	{0xEF, 0x00400}, {0x33, 0x01C23}, {0x33, 0x05C23}, {0x33, 0x09D23},
323 	{0x33, 0x0DD23}, {0x33, 0x11FA3}, {0x33, 0x15FA3}, {0x33, 0x19FAB},
324 	{0x33, 0x1DFAB}, {0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030},
325 	{0x33, 0x04030}, {0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030},
326 	{0x33, 0x14030}, {0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030},
327 	{0x33, 0x24030}, {0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030},
328 	{0x33, 0x34030}, {0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000},
329 	{0xEF, 0x00100}, {0x33, 0x44001}, {0x33, 0x48001}, {0x33, 0x4C001},
330 	{0x33, 0x50001}, {0x33, 0x54001}, {0x33, 0x58001}, {0x33, 0x5C001},
331 	{0x33, 0x60001}, {0x33, 0x64001}, {0x33, 0x68001}, {0x33, 0x6C001},
332 	{0x33, 0x70001}, {0x33, 0x74001}, {0x33, 0x78001}, {0x33, 0x04000},
333 	{0x33, 0x08000}, {0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000},
334 	{0x33, 0x18001}, {0x33, 0x1C002}, {0x33, 0x20002}, {0x33, 0x24002},
335 	{0x33, 0x28002}, {0x33, 0x2C002}, {0x33, 0x30002}, {0x33, 0x34002},
336 	{0x33, 0x38002}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010},
337 	{0x30, 0x20000}, {0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000},
338 	{0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F},
339 	{0x32, 0xF1DF3}, {0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000},
340 	{0x30, 0x38000}, {0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000},
341 	{0x1B, 0x746CE}, {0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000},
342 	{0x33, 0x70000}, {0x33, 0x78000}, {0xEF, 0x00000}, {0xDF, 0x08000},
343 	{0xB0, 0xFFBCB}, {0xB3, 0x06000}, {0xB7, 0x18DF0}, {0xB8, 0x38FF0},
344 	{0xC9, 0x00600}, {0xDF, 0x00000}, {0xB1, 0x33B8F}, {0xB2, 0x33762},
345 	{0xB4, 0x141F0}, {0xB5, 0x14080}, {0xB6, 0x12425}, {0xB9, 0xC0008},
346 	{0xBA, 0x40005}, {0xC2, 0x02C01}, {0xC3, 0x0000B}, {0xC4, 0x81E2F},
347 	{0xC5, 0x5C28F}, {0xC6, 0x000A0}, {0xCA, 0x02000}, {0xFE, 0x00000},
348 	{0x18, 0x08C07}, {0xFE, 0x00000}, {0xFE, 0x00000}, {0xFE, 0x00000},
349 	{0x00, 0x31DD5},
350 	{0xff, 0xffffffff}
354 	{0x00, 0x30000}, {0x81, 0x0FC00}, {0x82, 0x003C0}, {0x84, 0x00005},
355 	{0x86, 0xA33A5}, {0x87, 0x00000}, {0x88, 0x58010}, {0x8E, 0x64540},
356 	{0x8F, 0x282D8}, {0x51, 0x02C06}, {0x52, 0x7A007}, {0x53, 0x10061},
357 	{0x54, 0x60018}, {0x55, 0x82020}, {0x56, 0x08CC6}, {0x57, 0x2CC00},
358 	{0x58, 0x00000}, {0x5A, 0x50000}, {0x5B, 0x00006}, {0x5C, 0x00015},
359 	{0x65, 0x20000}, {0x6E, 0x38319}, {0xF5, 0x43180}, {0xEF, 0x00002},
360 	{0x33, 0x00301}, {0x33, 0x1032A}, {0x33, 0x2032A}, {0xEF, 0x00000},
361 	{0xDF, 0x00002}, {0x35, 0x00000}, {0xF0, 0x08008}, {0xEF, 0x00800},
362 	{0x33, 0x0040E}, {0x33, 0x04845}, {0x33, 0x08848}, {0x33, 0x0C84B},
363 	{0x33, 0x1088A}, {0x33, 0x14CC8}, {0x33, 0x18CCB}, {0x33, 0x1CCCE},
364 	{0x33, 0x20CD1}, {0x33, 0x24CD4}, {0x33, 0x28CD7}, {0x33, 0x4002B},
365 	{0x33, 0x4402E}, {0x33, 0x48846}, {0x33, 0x4C849}, {0x33, 0x50888},
366 	{0x33, 0x54CC6}, {0x33, 0x58CC9}, {0x33, 0x5CCCC}, {0x33, 0x60CCF},
367 	{0x33, 0x64CD2}, {0x33, 0x68CD5}, {0xEF, 0x00000}, {0xEF, 0x00400},
368 	{0x33, 0x01D23}, {0x33, 0x05D23}, {0x33, 0x09FA3}, {0x33, 0x0DFA3},
369 	{0x33, 0x11D2B}, {0x33, 0x15D2B}, {0x33, 0x19FAB}, {0x33, 0x1DFAB},
370 	{0xEF, 0x00000}, {0xEF, 0x00200}, {0x33, 0x00030}, {0x33, 0x04030},
371 	{0x33, 0x08030}, {0x33, 0x0C030}, {0x33, 0x10030}, {0x33, 0x14030},
372 	{0x33, 0x18030}, {0x33, 0x1C030}, {0x33, 0x20030}, {0x33, 0x24030},
373 	{0x33, 0x28030}, {0x33, 0x2C030}, {0x33, 0x30030}, {0x33, 0x34030},
374 	{0x33, 0x38030}, {0x33, 0x3C030}, {0xEF, 0x00000}, {0xEF, 0x00100},
375 	{0x33, 0x44000}, {0x33, 0x48000}, {0x33, 0x4C000}, {0x33, 0x50000},
376 	{0x33, 0x54000}, {0x33, 0x58000}, {0x33, 0x5C000}, {0x33, 0x60000},
377 	{0x33, 0x64000}, {0x33, 0x68000}, {0x33, 0x6C000}, {0x33, 0x70000},
378 	{0x33, 0x74000}, {0x33, 0x78000}, {0x33, 0x04000}, {0x33, 0x08000},
379 	{0x33, 0x0C000}, {0x33, 0x10000}, {0x33, 0x14000}, {0x33, 0x18000},
380 	{0x33, 0x1C001}, {0x33, 0x20001}, {0x33, 0x24001}, {0x33, 0x28001},
381 	{0x33, 0x2C001}, {0x33, 0x30001}, {0x33, 0x34001}, {0x33, 0x38001},
382 	{0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80010}, {0x30, 0x20000},
383 	{0x31, 0x0006F}, {0x32, 0x01FF7}, {0xEF, 0x00000}, {0x84, 0x00000},
384 	{0xEF, 0x80000}, {0x30, 0x30000}, {0x31, 0x0006F}, {0x32, 0xF1DF3},
385 	{0xEF, 0x00000}, {0x84, 0x00000}, {0xEF, 0x80000}, {0x30, 0x38000},
386 	{0x31, 0x0006F}, {0x32, 0xF1FF2}, {0xEF, 0x00000}, {0x1B, 0x746CE},
387 	{0xEF, 0x20000}, {0x33, 0x30000}, {0x33, 0x38000}, {0x33, 0x70000},
388 	{0x33, 0x78000}, {0xEF, 0x00000}, {0x00, 0x31DD5},
389 	{0xff, 0xffffffff}
436 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_CCK1_MCS32, 0x00007f00, cck);  in rtl8192f_set_tx_power()
440 			      0x7f7f7f00, val32);  in rtl8192f_set_tx_power()
446 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE18_06, 0x7f7f7f7f, ofdm);  in rtl8192f_set_tx_power()
447 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_RATE54_24, 0x7f7f7f7f, ofdm);  in rtl8192f_set_tx_power()
456 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS03_MCS00, 0x7f7f7f7f, mcs);  in rtl8192f_set_tx_power()
457 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS07_MCS04, 0x7f7f7f7f, mcs);  in rtl8192f_set_tx_power()
458 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS11_MCS08, 0x7f7f7f7f, mcs);  in rtl8192f_set_tx_power()
459 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_A_MCS15_MCS12, 0x7f7f7f7f, mcs);  in rtl8192f_set_tx_power()
468 			      0x7f7f7f00, val32);  in rtl8192f_set_tx_power()
471 			      0x0000007f, cck);  in rtl8192f_set_tx_power()
477 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE18_06, 0x7f7f7f7f, ofdm);  in rtl8192f_set_tx_power()
478 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_RATE54_24, 0x7f7f7f7f, ofdm);  in rtl8192f_set_tx_power()
487 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS03_MCS00, 0x7f7f7f7f, mcs);  in rtl8192f_set_tx_power()
488 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS07_MCS04, 0x7f7f7f7f, mcs);  in rtl8192f_set_tx_power()
489 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS11_MCS08, 0x7f7f7f7f, mcs);  in rtl8192f_set_tx_power()
490 	rtl8xxxu_write32_mask(priv, REG_TX_AGC_B_MCS15_MCS12, 0x7f7f7f7f, mcs);  in rtl8192f_set_tx_power()
497 		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xf8fe0001);  in rtl8192f_revise_cck_tx_psf()
499 		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);  in rtl8192f_revise_cck_tx_psf()
500 		rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810);  in rtl8192f_revise_cck_tx_psf()
501 		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);  in rtl8192f_revise_cck_tx_psf()
504 		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);  in rtl8192f_revise_cck_tx_psf()
506 		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C);  in rtl8192f_revise_cck_tx_psf()
507 		rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x0000);  in rtl8192f_revise_cck_tx_psf()
508 		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667);  in rtl8192f_revise_cck_tx_psf()
511 		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);  in rtl8192f_revise_cck_tx_psf()
512 		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);  in rtl8192f_revise_cck_tx_psf()
513 		rtl8xxxu_write16(priv, REG_CCK0_DEBUG_PORT, 0x8810);  in rtl8192f_revise_cck_tx_psf()
514 		rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);  in rtl8192f_revise_cck_tx_psf()
521 	u8 bb_gain_path_mask[2] = { 0x0f, 0xf0 };  in rtl8192fu_config_kfree()
524 	u8 channel_idx = 0;  in rtl8192fu_config_kfree()
527 		channel_idx = 0;  in rtl8192fu_config_kfree()
533 	rtl8xxxu_read_efuse8(priv, 0x1ee, &bb_gain[1]);  in rtl8192fu_config_kfree()
534 	rtl8xxxu_read_efuse8(priv, 0x1ec, &bb_gain[0]);  in rtl8192fu_config_kfree()
535 	rtl8xxxu_read_efuse8(priv, 0x1ea, &bb_gain[2]);  in rtl8192fu_config_kfree()
540 	if (bb_gain[0] == EFUSE_UNDEFINED)  in rtl8192fu_config_kfree()
541 		bb_gain[0] = bb_gain[1];  in rtl8192fu_config_kfree()
566 					  0x70000, channel_idx * 2);  in rtl8192fu_config_kfree()
568 					  0x3f, bb_gain_for_path);  in rtl8192fu_config_kfree()
571 					  0x70000, channel_idx * 2 + 1);  in rtl8192fu_config_kfree()
573 					  0x3f, bb_gain_for_path);  in rtl8192fu_config_kfree()
577 					  BIT(7), 0);  in rtl8192fu_config_kfree()
580 		rtl8xxxu_write_rfreg_mask(priv, rfpath, RF6052_REG_WE_LUT, BIT(7), 0);  in rtl8192fu_config_kfree()
588 	u8 channel, subchannel = 0;  in rtl8192fu_config_channel()
589 	bool sec_ch_above = 0;  in rtl8192fu_config_channel()
599 		sec_ch_above = 0;  in rtl8192fu_config_channel()
610 	u32p_replace_bits(&val32, channel, 0xff);  in rtl8192fu_config_channel()
659 		val32 = 0x3;  in rtl8192fu_config_channel()
661 		val32 = 0x1a3;  in rtl8192fu_config_channel()
662 	rtl8xxxu_write32_mask(priv, REG_RX_DFIR_MOD_97F, 0x1ff, val32);  in rtl8192fu_config_channel()
676 	agg_rx &= ~0xFF0F; /* reset agg size and timeout */  in rtl8192fu_init_aggregation()
687 	if (efuse->rtl_id != cpu_to_le16(0x8129))  in rtl8192fu_parse_efuse()
704 	priv->ht20_tx_power_diff[0].a =  in rtl8192fu_parse_efuse()
706 	priv->ht20_tx_power_diff[0].b =  in rtl8192fu_parse_efuse()
709 	priv->ht40_tx_power_diff[0].a = 0;  in rtl8192fu_parse_efuse()
710 	priv->ht40_tx_power_diff[0].b = 0;  in rtl8192fu_parse_efuse()
729 	priv->default_crystal_cap = efuse->xtal_k & 0x3f;  in rtl8192fu_parse_efuse()
731 	priv->rfe_type = efuse->rfe_option & 0x1f;  in rtl8192fu_parse_efuse()
738 	return 0;  in rtl8192fu_parse_efuse()
755 	rtl8xxxu_write8(priv, REG_LDOHCI12_CTRL, 0xf);  in rtl8192fu_init_phy_bb()
756 	rtl8xxxu_write8(priv, REG_SYS_SWR_CTRL2 + 1, 0xe9);  in rtl8192fu_init_phy_bb()
784 	u32p_replace_bits(&val32, 0, backup_mask);  in rtl8192f_phy_lc_calibrate()
804 	int result = 0;  in rtl8192fu_iqk_path_a()
808 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_iqk_path_a()
810 	rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);  in rtl8192fu_iqk_path_a()
811 	rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);  in rtl8192fu_iqk_path_a()
812 	rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);  in rtl8192fu_iqk_path_a()
813 	rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);  in rtl8192fu_iqk_path_a()
814 	rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);  in rtl8192fu_iqk_path_a()
815 	rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);  in rtl8192fu_iqk_path_a()
816 	rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);  in rtl8192fu_iqk_path_a()
821 		val32 = 0x30;  in rtl8192fu_iqk_path_a()
823 		val32 = 0xe9;  in rtl8192fu_iqk_path_a()
824 	rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, val32);  in rtl8192fu_iqk_path_a()
826 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_iqk_path_a()
829 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);  in rtl8192fu_iqk_path_a()
830 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);  in rtl8192fu_iqk_path_a()
831 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtl8192fu_iqk_path_a()
832 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtl8192fu_iqk_path_a()
834 	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8214000f);  in rtl8192fu_iqk_path_a()
835 	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28140000);  in rtl8192fu_iqk_path_a()
837 	rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);  in rtl8192fu_iqk_path_a()
838 	rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);  in rtl8192fu_iqk_path_a()
841 	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911);  in rtl8192fu_iqk_path_a()
844 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);  in rtl8192fu_iqk_path_a()
845 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);  in rtl8192fu_iqk_path_a()
849 	ktime = 0;  in rtl8192fu_iqk_path_a()
850 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) {  in rtl8192fu_iqk_path_a()
860 	/* reload 0xdf and CCK_IND off */  in rtl8192fu_iqk_path_a()
861 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_iqk_path_a()
866 	rf_0x58_i = u32_get_bits(val32, 0xfc000);  in rtl8192fu_iqk_path_a()
867 	rf_0x58_q = u32_get_bits(val32, 0x003f0);  in rtl8192fu_iqk_path_a()
869 	for (i = 0; i < 8; i++) {  in rtl8192fu_iqk_path_a()
871 					  0x1c000, i);  in rtl8192fu_iqk_path_a()
873 					  0x00fc0, rf_0x58_i);  in rtl8192fu_iqk_path_a()
875 					  0x0003f, rf_0x58_q);  in rtl8192fu_iqk_path_a()
878 	rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_AC, BIT(14), 0);  in rtl8192fu_iqk_path_a()
879 	rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_WE_LUT, BIT(4), 0);  in rtl8192fu_iqk_path_a()
880 	rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00810, 0);  in rtl8192fu_iqk_path_a()
883 	    ((reg_e94 & 0x03ff0000) != 0x01420000) &&  in rtl8192fu_iqk_path_a()
884 	    ((reg_e9c & 0x03ff0000) != 0x00420000))  in rtl8192fu_iqk_path_a()
885 		result |= 0x01;  in rtl8192fu_iqk_path_a()
893 	int result = 0;  in rtl8192fu_rx_iqk_path_a()
897 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_a()
899 	/* PA/PAD control by 0x56, and set = 0x0 */  in rtl8192fu_rx_iqk_path_a()
901 	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0);  in rtl8192fu_rx_iqk_path_a()
903 	rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x27);  in rtl8192fu_rx_iqk_path_a()
906 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_rx_iqk_path_a()
909 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);  in rtl8192fu_rx_iqk_path_a()
910 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);  in rtl8192fu_rx_iqk_path_a()
911 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtl8192fu_rx_iqk_path_a()
912 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtl8192fu_rx_iqk_path_a()
914 	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160027);  in rtl8192fu_rx_iqk_path_a()
915 	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160000);  in rtl8192fu_rx_iqk_path_a()
918 	rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);  in rtl8192fu_rx_iqk_path_a()
919 	rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);  in rtl8192fu_rx_iqk_path_a()
922 	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911);  in rtl8192fu_rx_iqk_path_a()
925 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);  in rtl8192fu_rx_iqk_path_a()
926 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);  in rtl8192fu_rx_iqk_path_a()
930 	ktime = 0;  in rtl8192fu_rx_iqk_path_a()
931 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) {  in rtl8192fu_rx_iqk_path_a()
942 	    ((reg_e94 & 0x03ff0000) != 0x01420000) &&  in rtl8192fu_rx_iqk_path_a()
943 	    ((reg_e9c & 0x03ff0000) != 0x00420000)) {  in rtl8192fu_rx_iqk_path_a()
944 		result |= 0x01;  in rtl8192fu_rx_iqk_path_a()
946 		/* PA/PAD controlled by 0x0 */  in rtl8192fu_rx_iqk_path_a()
947 		rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_a()
950 					  BIT(11), 0);  in rtl8192fu_rx_iqk_path_a()
955 	val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16);  in rtl8192fu_rx_iqk_path_a()
959 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_a()
961 	/* PA/PAD control by 0x56, and set = 0x0 */  in rtl8192fu_rx_iqk_path_a()
963 	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0);  in rtl8192fu_rx_iqk_path_a()
965 	rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0);  in rtl8192fu_rx_iqk_path_a()
967 	rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);  in rtl8192fu_rx_iqk_path_a()
968 	rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);  in rtl8192fu_rx_iqk_path_a()
969 	rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);  in rtl8192fu_rx_iqk_path_a()
970 	rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);  in rtl8192fu_rx_iqk_path_a()
971 	rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);  in rtl8192fu_rx_iqk_path_a()
972 	rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);  in rtl8192fu_rx_iqk_path_a()
973 	rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);  in rtl8192fu_rx_iqk_path_a()
976 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_rx_iqk_path_a()
979 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);  in rtl8192fu_rx_iqk_path_a()
980 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);  in rtl8192fu_rx_iqk_path_a()
981 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtl8192fu_rx_iqk_path_a()
982 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtl8192fu_rx_iqk_path_a()
984 	rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82170000);  in rtl8192fu_rx_iqk_path_a()
985 	rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28170000);  in rtl8192fu_rx_iqk_path_a()
988 	rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);  in rtl8192fu_rx_iqk_path_a()
991 	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);  in rtl8192fu_rx_iqk_path_a()
994 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);  in rtl8192fu_rx_iqk_path_a()
995 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);  in rtl8192fu_rx_iqk_path_a()
999 	ktime = 0;  in rtl8192fu_rx_iqk_path_a()
1000 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXA) == 0 && ktime < 21) {  in rtl8192fu_rx_iqk_path_a()
1010 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_a()
1012 	rtl8xxxu_write_rfreg_mask(priv, RF_A, RF6052_REG_GAIN_CCA, BIT(11), 0);  in rtl8192fu_rx_iqk_path_a()
1013 	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_P1, 0x02000);  in rtl8192fu_rx_iqk_path_a()
1016 	    ((reg_ea4 & 0x03ff0000) != 0x01320000) &&  in rtl8192fu_rx_iqk_path_a()
1017 	    ((reg_eac & 0x03ff0000) != 0x00360000))  in rtl8192fu_rx_iqk_path_a()
1018 		result |= 0x02;  in rtl8192fu_rx_iqk_path_a()
1028 	int result = 0;  in rtl8192fu_iqk_path_b()
1031 	/* PA/PAD controlled by 0x0 */  in rtl8192fu_iqk_path_b()
1032 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_iqk_path_b()
1034 	rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);  in rtl8192fu_iqk_path_b()
1035 	rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);  in rtl8192fu_iqk_path_b()
1036 	rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);  in rtl8192fu_iqk_path_b()
1037 	rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);  in rtl8192fu_iqk_path_b()
1038 	rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);  in rtl8192fu_iqk_path_b()
1039 	rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);  in rtl8192fu_iqk_path_b()
1040 	rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000);  in rtl8192fu_iqk_path_b()
1046 					  0x003ff, 0x30);  in rtl8192fu_iqk_path_b()
1049 					  0x00fff, 0xe9);  in rtl8192fu_iqk_path_b()
1051 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_iqk_path_b()
1054 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);  in rtl8192fu_iqk_path_b()
1055 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);  in rtl8192fu_iqk_path_b()
1056 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);  in rtl8192fu_iqk_path_b()
1057 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtl8192fu_iqk_path_b()
1059 	rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8214000F);  in rtl8192fu_iqk_path_b()
1060 	rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28140000);  in rtl8192fu_iqk_path_b()
1062 	rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);  in rtl8192fu_iqk_path_b()
1063 	rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);  in rtl8192fu_iqk_path_b()
1066 	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00e62911);  in rtl8192fu_iqk_path_b()
1069 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);  in rtl8192fu_iqk_path_b()
1070 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);  in rtl8192fu_iqk_path_b()
1074 	ktime = 0;  in rtl8192fu_iqk_path_b()
1075 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) {  in rtl8192fu_iqk_path_b()
1085 	/* reload 0xdf and CCK_IND off */  in rtl8192fu_iqk_path_b()
1086 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_iqk_path_b()
1091 	rf_0x58_i = u32_get_bits(val32, 0xfc000);  in rtl8192fu_iqk_path_b()
1092 	rf_0x58_q = u32_get_bits(val32, 0x003f0);  in rtl8192fu_iqk_path_b()
1094 	for (i = 0; i < 8; i++) {  in rtl8192fu_iqk_path_b()
1096 					  0x1c000, i);  in rtl8192fu_iqk_path_b()
1098 					  0x00fc0, rf_0x58_i);  in rtl8192fu_iqk_path_b()
1100 					  0x0003f, rf_0x58_q);  in rtl8192fu_iqk_path_b()
1103 	rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_AC, BIT(14), 0);  in rtl8192fu_iqk_path_b()
1104 	rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_WE_LUT, BIT(4), 0);  in rtl8192fu_iqk_path_b()
1105 	rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00810, 0);  in rtl8192fu_iqk_path_b()
1108 	    ((reg_eb4 & 0x03ff0000) != 0x01420000) &&  in rtl8192fu_iqk_path_b()
1109 	    ((reg_ebc & 0x03ff0000) != 0x00420000))  in rtl8192fu_iqk_path_b()
1110 		result |= 0x01;  in rtl8192fu_iqk_path_b()
1121 	int result = 0;  in rtl8192fu_rx_iqk_path_b()
1125 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_b()
1128 	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0);  in rtl8192fu_rx_iqk_path_b()
1130 	rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x67);  in rtl8192fu_rx_iqk_path_b()
1132 	rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);  in rtl8192fu_rx_iqk_path_b()
1133 	rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);  in rtl8192fu_rx_iqk_path_b()
1134 	rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);  in rtl8192fu_rx_iqk_path_b()
1135 	rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);  in rtl8192fu_rx_iqk_path_b()
1136 	rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);  in rtl8192fu_rx_iqk_path_b()
1137 	rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);  in rtl8192fu_rx_iqk_path_b()
1138 	rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000);  in rtl8192fu_rx_iqk_path_b()
1140 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_rx_iqk_path_b()
1143 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);  in rtl8192fu_rx_iqk_path_b()
1144 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);  in rtl8192fu_rx_iqk_path_b()
1145 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);  in rtl8192fu_rx_iqk_path_b()
1146 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);  in rtl8192fu_rx_iqk_path_b()
1148 	rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160027);  in rtl8192fu_rx_iqk_path_b()
1149 	rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160000);  in rtl8192fu_rx_iqk_path_b()
1152 	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0086a911);  in rtl8192fu_rx_iqk_path_b()
1155 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);  in rtl8192fu_rx_iqk_path_b()
1156 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);  in rtl8192fu_rx_iqk_path_b()
1160 	ktime = 0;  in rtl8192fu_rx_iqk_path_b()
1161 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) {  in rtl8192fu_rx_iqk_path_b()
1172 	    ((reg_eb4 & 0x03ff0000) != 0x01420000) &&  in rtl8192fu_rx_iqk_path_b()
1173 	    ((reg_ebc & 0x03ff0000) != 0x00420000)) {  in rtl8192fu_rx_iqk_path_b()
1174 		result |= 0x01;  in rtl8192fu_rx_iqk_path_b()
1176 		/* PA/PAD controlled by 0x0 */  in rtl8192fu_rx_iqk_path_b()
1177 		rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_b()
1180 					  BIT(11), 0);  in rtl8192fu_rx_iqk_path_b()
1185 	val32 = 0x80007c00 | (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);  in rtl8192fu_rx_iqk_path_b()
1189 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_b()
1192 	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0);  in rtl8192fu_rx_iqk_path_b()
1194 	rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_PAD_TXG, 0x003ff, 0x1e0);  in rtl8192fu_rx_iqk_path_b()
1196 	rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xccf000c0);  in rtl8192fu_rx_iqk_path_b()
1197 	rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44ffbb44);  in rtl8192fu_rx_iqk_path_b()
1198 	rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00400040);  in rtl8192fu_rx_iqk_path_b()
1199 	rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005403);  in rtl8192fu_rx_iqk_path_b()
1200 	rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000804e4);  in rtl8192fu_rx_iqk_path_b()
1201 	rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400);  in rtl8192fu_rx_iqk_path_b()
1202 	rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000000);  in rtl8192fu_rx_iqk_path_b()
1204 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_rx_iqk_path_b()
1207 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);  in rtl8192fu_rx_iqk_path_b()
1208 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);  in rtl8192fu_rx_iqk_path_b()
1209 	rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);  in rtl8192fu_rx_iqk_path_b()
1210 	rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);  in rtl8192fu_rx_iqk_path_b()
1212 	rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82170000);  in rtl8192fu_rx_iqk_path_b()
1213 	rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28170000);  in rtl8192fu_rx_iqk_path_b()
1216 	rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);  in rtl8192fu_rx_iqk_path_b()
1219 	rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);  in rtl8192fu_rx_iqk_path_b()
1222 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa005800);  in rtl8192fu_rx_iqk_path_b()
1223 	rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8005800);  in rtl8192fu_rx_iqk_path_b()
1227 	ktime = 0;  in rtl8192fu_rx_iqk_path_b()
1228 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXB) == 0 && ktime < 21) {  in rtl8192fu_rx_iqk_path_b()
1237 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_b()
1238 	rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);  in rtl8192fu_rx_iqk_path_b()
1240 	rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(11), 0);  in rtl8192fu_rx_iqk_path_b()
1241 	rtl8xxxu_write_rfreg_mask(priv, RF_B, RF6052_REG_GAIN_CCA, BIT(1), 0);  in rtl8192fu_rx_iqk_path_b()
1242 	rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_P1, 0x02000);  in rtl8192fu_rx_iqk_path_b()
1245 	    ((reg_ec4 & 0x03ff0000) != 0x01320000) &&  in rtl8192fu_rx_iqk_path_b()
1246 	    ((reg_ecc & 0x03ff0000) != 0x00360000))  in rtl8192fu_rx_iqk_path_b()
1247 		result |= 0x02;  in rtl8192fu_rx_iqk_path_b()
1283 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_phy_iqcalibrate()
1288 	if (t == 0) {  in rtl8192fu_phy_iqcalibrate()
1301 	rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);  in rtl8192fu_phy_iqcalibrate()
1307 		rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF, 0x7);  in rtl8192fu_phy_iqcalibrate()
1308 		rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x1, 0x0);  in rtl8192fu_phy_iqcalibrate()
1310 		rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF00, 0x7);  in rtl8192fu_phy_iqcalibrate()
1311 		rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x4, 0x0);  in rtl8192fu_phy_iqcalibrate()
1313 		rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANTA_SRC, 0xF000, 0x7);  in rtl8192fu_phy_iqcalibrate()
1314 		rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8, 0x0);  in rtl8192fu_phy_iqcalibrate()
1317 		rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0, 0x7);  in rtl8192fu_phy_iqcalibrate()
1318 		rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x20000, 0x0);  in rtl8192fu_phy_iqcalibrate()
1320 		rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC2, 0xF0000, 0x7);  in rtl8192fu_phy_iqcalibrate()
1321 		rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x100000, 0x0);  in rtl8192fu_phy_iqcalibrate()
1323 		rtl8xxxu_write32_mask(priv, REG_RFE_CTRL_ANT_SRC3, 0xF000, 0x7);  in rtl8192fu_phy_iqcalibrate()
1324 		rtl8xxxu_write32_mask(priv, REG_DPDT_CTRL, 0x8000000, 0x0);  in rtl8192fu_phy_iqcalibrate()
1329 		rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x000000);  in rtl8192fu_phy_iqcalibrate()
1330 		rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);  in rtl8192fu_phy_iqcalibrate()
1331 		rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_phy_iqcalibrate()
1334 	for (i = 0; i < retry; i++) {  in rtl8192fu_phy_iqcalibrate()
1337 		if (path_a_ok == 0x01) {  in rtl8192fu_phy_iqcalibrate()
1339 			result[t][0] = (val32 >> 16) & 0x3ff;  in rtl8192fu_phy_iqcalibrate()
1342 			result[t][1] = (val32 >> 16) & 0x3ff;  in rtl8192fu_phy_iqcalibrate()
1345 			result[t][0] = 0x100;  in rtl8192fu_phy_iqcalibrate()
1346 			result[t][1] = 0x0;  in rtl8192fu_phy_iqcalibrate()
1350 	for (i = 0; i < retry; i++) {  in rtl8192fu_phy_iqcalibrate()
1353 		if (path_a_ok == 0x03) {  in rtl8192fu_phy_iqcalibrate()
1355 			result[t][2] = (val32 >> 16) & 0x3ff;  in rtl8192fu_phy_iqcalibrate()
1358 			result[t][3] = (val32 >> 16) & 0x3ff;  in rtl8192fu_phy_iqcalibrate()
1361 			result[t][2] = 0x100;  in rtl8192fu_phy_iqcalibrate()
1362 			result[t][3] = 0x0;  in rtl8192fu_phy_iqcalibrate()
1370 		for (i = 0; i < retry; i++) {  in rtl8192fu_phy_iqcalibrate()
1373 			if (path_b_ok == 0x01) {  in rtl8192fu_phy_iqcalibrate()
1375 				result[t][4] = (val32 >> 16) & 0x3ff;  in rtl8192fu_phy_iqcalibrate()
1378 				result[t][5] = (val32 >> 16) & 0x3ff;  in rtl8192fu_phy_iqcalibrate()
1381 				result[t][4] = 0x100;  in rtl8192fu_phy_iqcalibrate()
1382 				result[t][5] = 0x0;  in rtl8192fu_phy_iqcalibrate()
1386 		for (i = 0; i < retry; i++) {  in rtl8192fu_phy_iqcalibrate()
1389 			if (path_b_ok == 0x03) {  in rtl8192fu_phy_iqcalibrate()
1391 				result[t][6] = (val32 >> 16) & 0x3ff;  in rtl8192fu_phy_iqcalibrate()
1394 				result[t][7] = (val32 >> 16) & 0x3ff;  in rtl8192fu_phy_iqcalibrate()
1397 				result[t][6] = 0x100;  in rtl8192fu_phy_iqcalibrate()
1398 				result[t][7] = 0x0;  in rtl8192fu_phy_iqcalibrate()
1407 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_phy_iqcalibrate()
1409 	rtl8xxxu_write32(priv, REG_FPGA0_ANALOG4, 0xcc0000c0);  in rtl8192fu_phy_iqcalibrate()
1411 	rtl8xxxu_write32(priv, REG_ANAPWR1, 0x44bbbb44);  in rtl8192fu_phy_iqcalibrate()
1412 	rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x80408040);  in rtl8192fu_phy_iqcalibrate()
1413 	rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x6f005433);  in rtl8192fu_phy_iqcalibrate()
1414 	rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000004e4);  in rtl8192fu_phy_iqcalibrate()
1415 	rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04003400);  in rtl8192fu_phy_iqcalibrate()
1416 	rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);  in rtl8192fu_phy_iqcalibrate()
1431 	rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff, 0x50);  in rtl8192fu_phy_iqcalibrate()
1432 	rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1, 0xff,  in rtl8192fu_phy_iqcalibrate()
1433 			      rx_initial_gain_a & 0xff);  in rtl8192fu_phy_iqcalibrate()
1435 		rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff, 0x50);  in rtl8192fu_phy_iqcalibrate()
1436 		rtl8xxxu_write32_mask(priv, REG_OFDM0_XB_AGC_CORE1, 0xff,  in rtl8192fu_phy_iqcalibrate()
1437 				      rx_initial_gain_b & 0xff);  in rtl8192fu_phy_iqcalibrate()
1453 	s32 reg_tmp = 0;  in rtl8192fu_phy_iq_calibrate()
1464 	memset(result, 0, sizeof(result));  in rtl8192fu_phy_iq_calibrate()
1470 	for (i = 0; i < 3; i++) {  in rtl8192fu_phy_iq_calibrate()
1474 			simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1);  in rtl8192fu_phy_iq_calibrate()
1476 				candidate = 0;  in rtl8192fu_phy_iq_calibrate()
1482 			simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2);  in rtl8192fu_phy_iq_calibrate()
1484 				candidate = 0;  in rtl8192fu_phy_iq_calibrate()
1492 				for (i = 0; i < 8; i++)  in rtl8192fu_phy_iq_calibrate()
1503 	if (candidate >= 0) {  in rtl8192fu_phy_iq_calibrate()
1504 		reg_e94 = result[candidate][0];  in rtl8192fu_phy_iq_calibrate()
1522 	rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_A, 0x3ff00000, 0x100);  in rtl8192fu_phy_iq_calibrate()
1523 	rtl8xxxu_write32_mask(priv, REG_NP_ANTA, 0x3ff, 0);  in rtl8192fu_phy_iq_calibrate()
1524 	rtl8xxxu_write32_mask(priv, REG_TX_IQK_TONE_B, 0x3ff00000, 0x100);  in rtl8192fu_phy_iq_calibrate()
1525 	rtl8xxxu_write32_mask(priv, REG_TAP_UPD_97F, 0x3ff, 0);  in rtl8192fu_phy_iq_calibrate()
1527 	if (candidate >= 0) {  in rtl8192fu_phy_iq_calibrate()
1530 						   candidate, (reg_ea4 == 0));  in rtl8192fu_phy_iq_calibrate()
1534 						   candidate, (reg_ec4 == 0));  in rtl8192fu_phy_iq_calibrate()
1543 		rtl8xxxu_write32_set(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x70000);  in rtl8192fu_phy_iq_calibrate()
1544 		rtl8xxxu_write32_clear(priv, REG_LEDCFG0, 0x6c00000);  in rtl8192fu_phy_iq_calibrate()
1547 				       0x600000 | BIT(4));  in rtl8192fu_phy_iq_calibrate()
1551 		 * odm_set_bb_reg(dm, R_0x944, BIT(11) | 0x1F, 0x3F);  in rtl8192fu_phy_iq_calibrate()
1553 		 * It clears bit 11 and sets bits 0..4. The mask doesn't cover  in rtl8192fu_phy_iq_calibrate()
1559 		val32 |= 0x1f;  in rtl8192fu_phy_iq_calibrate()
1564 					      0xfffff, 0x23200);  in rtl8192fu_phy_iq_calibrate()
1566 					      0xfffff, 0x23200);  in rtl8192fu_phy_iq_calibrate()
1568 					      0xf000, 0x3);  in rtl8192fu_phy_iq_calibrate()
1570 					      0xf000, 0x3);  in rtl8192fu_phy_iq_calibrate()
1573 					      0xfffff, 0x22200);  in rtl8192fu_phy_iq_calibrate()
1575 					      0xfffff, 0x22200);  in rtl8192fu_phy_iq_calibrate()
1577 					      0xf000, 0x2);  in rtl8192fu_phy_iq_calibrate()
1579 					      0xf000, 0x2);  in rtl8192fu_phy_iq_calibrate()
1585 			rtl8xxxu_write32(priv, REG_RFE_OPT, 0x03000003);  in rtl8192fu_phy_iq_calibrate()
1622 	/* wait till 0x04[17] = 1 power ready */  in rtl8192fu_emu_to_active()
1638 		if ((val32 & (APS_FSMCO_MAC_ENABLE | APS_FSMCO_MAC_OFF)) == 0)  in rtl8192fu_emu_to_active()
1655 	/* 0x7c[31]=1, LDO has max output capability */  in rtl8192fu_emu_to_active()
1662 		if ((val32 & APS_FSMCO_MAC_ENABLE) == 0)  in rtl8192fu_emu_to_active()
1683 	/* Enable HSISR GPIO[C:0] interrupt */  in rtl8192fu_emu_to_active()
1684 	rtl8xxxu_write8_set(priv, REG_HSIMR, BIT(0));  in rtl8192fu_emu_to_active()
1696 	rtl8xxxu_write8(priv, REG_RF_CTRL, 0);  in rtl8192fu_emu_to_active()
1699 	rtl8xxxu_write8(priv, REG_AFE_CTRL4 + 3, 0);  in rtl8192fu_emu_to_active()
1711 	rtl8xxxu_write8(priv, REG_RSVD_4, 0xcc);  in rtl8192fu_emu_to_active()
1713 	/* AFE_Ctrl 0x24[4:3]=00 for xtal gmn */  in rtl8192fu_emu_to_active()
1716 	/* GPIO_A[31:0] Pull down software register */  in rtl8192fu_emu_to_active()
1717 	rtl8xxxu_write32(priv, REG_GPIO_A0, 0xffffffff);  in rtl8192fu_emu_to_active()
1719 	/* GPIO_B[7:0] Pull down software register */  in rtl8192fu_emu_to_active()
1720 	rtl8xxxu_write8(priv, REG_GPIO_B0, 0xff);  in rtl8192fu_emu_to_active()
1725 	return 0;  in rtl8192fu_emu_to_active()
1747 		if ((val32 & APS_FSMCO_MAC_OFF) == 0)  in rtl8192fu_active_to_emu()
1762 	return 0;  in rtl8192fu_active_to_emu()
1770 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);  in rtl8192fu_emu_to_disabled()
1772 	/* 0x04[12:11] = 2b'01 enable WL suspend */  in rtl8192fu_emu_to_disabled()
1781 	return 0;  in rtl8192fu_emu_to_disabled()
1792 	rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);  in rtl8192fu_active_to_lps()
1796 	/* Poll 32 bit wide REG_SCH_TX_CMD for 0 to ensure no TX is pending. */  in rtl8192fu_active_to_lps()
1820 	val16 &= 0xff00;  in rtl8192fu_active_to_lps()
1828 	return 0;  in rtl8192fu_active_to_lps()
1836 	rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80);  in rtl8192fu_power_on()
1844 	rtl8xxxu_write16(priv, REG_CR, 0);  in rtl8192fu_power_on()
1854 	return 0;  in rtl8192fu_power_on()
1861 	/* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */  in rtl8192fu_power_off()
1866 	rtl8xxxu_write8(priv, REG_CR, 0x00);  in rtl8192fu_power_off()
1878 	rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);  in rtl8192fu_power_off()
1888 	rtl8xxxu_write8_clear(priv, REG_RSV_CTRL + 1, BIT(0));  in rtl8192f_reset_8051()
1894 	rtl8xxxu_write8_set(priv, REG_RSV_CTRL + 1, BIT(0));  in rtl8192f_reset_8051()
1911 	rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);  in rtl8192f_enable_rf()
1923 	rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);  in rtl8192f_disable_rf()
1952 		"%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n",  in rtl8192f_set_crystal_cap()
1984 	case 0:  in rtl8192f_cck_rssi()
1988 		rx_pwr_all = 0;  in rtl8192f_cck_rssi()
2004 	rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_0, 0x20080);  in rtl8192fu_led_brightness_set()
2005 	rtl8xxxu_write32(priv, REG_SW_GPIO_SHARE_CTRL_1, 0x1b0000);  in rtl8192fu_led_brightness_set()
2036 	return 0;  in rtl8192fu_led_brightness_set()
2077 	.ampdu_max_time = 0x5e,
2078 	.ustime_tsf_edca = 0x50,
2079 	.max_aggr_num = 0x1f1f,
2083 	.trxff_boundary = 0x3f3f,