Lines Matching +full:0 +full:x4c000
52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
99 .status_reg = 0x2001c,
110 .enable_reg = 0x45000,
123 .offset = 0x25000,
126 .enable_reg = 0x45000,
139 .offset = 0x25000,
153 .offset = 0x23000,
156 .enable_reg = 0x45000,
169 .offset = 0x23000,
183 { P_XO, 0 },
193 { P_XO, 0 },
205 F(19200000, P_XO, 1, 0, 0),
206 F(50000000, P_GPLL0, 16, 0, 0),
207 F(100000000, P_GPLL0, 8, 0, 0),
212 .cmd_rcgr = 0x46000,
225 .cmd_rcgr = 0x32004,
238 .cmd_rcgr = 0x31028,
251 F(19200000, P_XO, 1, 0, 0),
252 F(50000000, P_GPLL0, 16, 0, 0),
257 .cmd_rcgr = 0x0200c,
270 .cmd_rcgr = 0x03000,
283 .cmd_rcgr = 0x04000,
296 .cmd_rcgr = 0x05000,
309 .cmd_rcgr = 0x06000,
322 .cmd_rcgr = 0x07000,
336 F(4800000, P_XO, 4, 0, 0),
337 F(9600000, P_XO, 2, 0, 0),
339 F(19200000, P_XO, 1, 0, 0),
341 F(50000000, P_GPLL0, 16, 0, 0),
346 .cmd_rcgr = 0x02024,
360 .cmd_rcgr = 0x03014,
374 .cmd_rcgr = 0x04024,
388 .cmd_rcgr = 0x05024,
402 .cmd_rcgr = 0x06024,
416 .cmd_rcgr = 0x07024,
434 F(19200000, P_XO, 1, 0, 0),
449 .cmd_rcgr = 0x02044,
463 .cmd_rcgr = 0x03034,
477 { P_XO, 0 },
487 .cmd_rcgr = 0x4d044,
500 F(100000000, P_GPLL0, 8, 0, 0),
501 F(200000000, P_GPLL0, 4, 0, 0),
506 .cmd_rcgr = 0x54000,
520 .cmd_rcgr = 0x55000,
535 F(80000000, P_GPLL0, 10, 0, 0),
540 .cmd_rcgr = 0x5a000,
554 F(50000000, P_GPLL0, 16, 0, 0),
555 F(80000000, P_GPLL0, 10, 0, 0),
556 F(100000000, P_GPLL0, 8, 0, 0),
557 F(160000000, P_GPLL0, 5, 0, 0),
562 .cmd_rcgr = 0x16004,
575 F(100000000, P_GPLL0, 8, 0, 0),
576 F(200000000, P_GPLL0, 4, 0, 0),
581 .cmd_rcgr = 0x4e020,
594 .cmd_rcgr = 0x4f020,
607 F(100000000, P_GPLL0, 8, 0, 0),
608 F(200000000, P_GPLL0, 4, 0, 0),
613 .cmd_rcgr = 0x4e000,
626 F(19200000, P_XO, 1, 0, 0),
631 .cmd_rcgr = 0x4d05c,
644 { P_XO, 0 },
656 F(19200000, P_XO, 1, 0, 0),
657 F(50000000, P_GPLL0, 16, 0, 0),
658 F(80000000, P_GPLL0, 10, 0, 0),
659 F(100000000, P_GPLL0, 8, 0, 0),
660 F(160000000, P_GPLL0, 5, 0, 0),
661 F(177780000, P_GPLL0, 4.5, 0, 0),
662 F(200000000, P_GPLL0, 4, 0, 0),
663 F(266670000, P_GPLL0, 3, 0, 0),
664 F(307200000, P_GPLL1, 4, 0, 0),
665 F(409600000, P_GPLL1, 3, 0, 0),
670 .cmd_rcgr = 0x59000,
684 F(19200000, P_XO, 1, 0, 0),
689 .cmd_rcgr = 0x08004,
703 .cmd_rcgr = 0x09004,
717 .cmd_rcgr = 0x0a004,
731 { P_XO, 0 },
744 F(66667000, P_GPLL0, 12, 0, 0),
749 .cmd_rcgr = 0x52000,
763 .cmd_rcgr = 0x53000,
777 { P_XO, 0 },
789 F(50000000, P_GPLL0, 16, 0, 0),
790 F(80000000, P_GPLL0, 10, 0, 0),
791 F(100000000, P_GPLL0, 8, 0, 0),
792 F(160000000, P_GPLL0, 5, 0, 0),
793 F(177780000, P_GPLL0, 4.5, 0, 0),
794 F(200000000, P_GPLL0, 4, 0, 0),
795 F(266670000, P_GPLL0, 3, 0, 0),
796 F(307200000, P_GPLL1, 4, 0, 0),
801 .cmd_rcgr = 0x4d014,
814 { P_XO, 0 },
824 .cmd_rcgr = 0x4d000,
838 .cmd_rcgr = 0x27000,
850 F(64000000, P_GPLL0, 12.5, 0, 0),
855 .cmd_rcgr = 0x44010,
872 F(50000000, P_GPLL0, 16, 0, 0),
873 F(100000000, P_GPLL0, 8, 0, 0),
874 F(177770000, P_GPLL0, 4.5, 0, 0),
875 F(200000000, P_GPLL0, 4, 0, 0),
880 .cmd_rcgr = 0x42004,
894 .cmd_rcgr = 0x43004,
908 .cmd_rcgr = 0x26004,
920 F(57140000, P_GPLL0, 14, 0, 0),
921 F(80000000, P_GPLL0, 10, 0, 0),
922 F(100000000, P_GPLL0, 8, 0, 0),
927 .cmd_rcgr = 0x41010,
940 { P_XO, 0 },
952 F(133330000, P_GPLL0, 6, 0, 0),
953 F(266670000, P_GPLL0, 3, 0, 0),
954 F(307200000, P_GPLL1, 4, 0, 0),
959 .cmd_rcgr = 0x4c000,
973 F(50000000, P_GPLL0, 16, 0, 0),
974 F(80000000, P_GPLL0, 10, 0, 0),
975 F(100000000, P_GPLL0, 8, 0, 0),
976 F(133330000, P_GPLL0, 6, 0, 0),
977 F(160000000, P_GPLL0, 5, 0, 0),
978 F(177780000, P_GPLL0, 4.5, 0, 0),
979 F(200000000, P_GPLL0, 4, 0, 0),
980 F(266670000, P_GPLL0, 3, 0, 0),
981 F(320000000, P_GPLL0, 2.5, 0, 0),
986 .cmd_rcgr = 0x58000,
999 F(19200000, P_XO, 1, 0, 0),
1004 .cmd_rcgr = 0x4d02c,
1017 .halt_reg = 0x12018,
1020 .enable_reg = 0x4500c,
1034 .halt_reg = 0x01008,
1037 .enable_reg = 0x45004,
1051 .halt_reg = 0x01004,
1054 .enable_reg = 0x45004,
1066 .halt_reg = 0x1300c,
1069 .enable_reg = 0x45004,
1083 .halt_reg = 0x1601c,
1086 .enable_reg = 0x45004,
1101 .halt_reg = 0x16024,
1104 .enable_reg = 0x45004,
1105 .enable_mask = BIT(0),
1118 .halt_reg = 0x16020,
1121 .enable_reg = 0x45004,
1135 .halt_reg = 0x12010,
1138 .enable_reg = 0x4500c,
1152 .halt_reg = 0x12020,
1155 .enable_reg = 0x4500c,
1169 .halt_reg = 0x12044,
1172 .enable_reg = 0x4500c,
1186 .halt_reg = 0x1201c,
1189 .enable_reg = 0x4500c,
1203 .halt_reg = 0x13004,
1206 .enable_reg = 0x45004,
1220 .halt_reg = 0x12038,
1223 .enable_reg = 0x4500c,
1237 .halt_reg = 0x12014,
1240 .enable_reg = 0x4500c,
1254 .halt_reg = 0x1203c,
1257 .enable_reg = 0x4500c,
1271 .halt_reg = 0x31024,
1274 .enable_reg = 0x31024,
1275 .enable_mask = BIT(0),
1288 .halt_reg = 0x31040,
1291 .enable_reg = 0x31040,
1292 .enable_mask = BIT(0),
1305 .halt_reg = 0x02008,
1308 .enable_reg = 0x02008,
1309 .enable_mask = BIT(0),
1323 .halt_reg = 0x03010,
1326 .enable_reg = 0x03010,
1327 .enable_mask = BIT(0),
1341 .halt_reg = 0x04020,
1344 .enable_reg = 0x04020,
1345 .enable_mask = BIT(0),
1359 .halt_reg = 0x05020,
1362 .enable_reg = 0x05020,
1363 .enable_mask = BIT(0),
1377 .halt_reg = 0x06020,
1380 .enable_reg = 0x06020,
1381 .enable_mask = BIT(0),
1395 .halt_reg = 0x07020,
1398 .enable_reg = 0x07020,
1399 .enable_mask = BIT(0),
1413 .halt_reg = 0x02004,
1416 .enable_reg = 0x02004,
1417 .enable_mask = BIT(0),
1431 .halt_reg = 0x0300c,
1434 .enable_reg = 0x0300c,
1435 .enable_mask = BIT(0),
1449 .halt_reg = 0x0401c,
1452 .enable_reg = 0x0401c,
1453 .enable_mask = BIT(0),
1467 .halt_reg = 0x0501c,
1470 .enable_reg = 0x0501c,
1471 .enable_mask = BIT(0),
1485 .halt_reg = 0x0601c,
1488 .enable_reg = 0x0601c,
1489 .enable_mask = BIT(0),
1503 .halt_reg = 0x0701c,
1506 .enable_reg = 0x0701c,
1507 .enable_mask = BIT(0),
1521 .halt_reg = 0x0203c,
1524 .enable_reg = 0x0203c,
1525 .enable_mask = BIT(0),
1539 .halt_reg = 0x0302c,
1542 .enable_reg = 0x0302c,
1543 .enable_mask = BIT(0),
1557 .halt_reg = 0x5a014,
1560 .enable_reg = 0x5a014,
1561 .enable_mask = BIT(0),
1574 .halt_reg = 0x4e03c,
1577 .enable_reg = 0x4e03c,
1578 .enable_mask = BIT(0),
1592 .halt_reg = 0x4e040,
1595 .enable_reg = 0x4e040,
1596 .enable_mask = BIT(0),
1610 .halt_reg = 0x4e048,
1613 .enable_reg = 0x4e048,
1614 .enable_mask = BIT(0),
1628 .halt_reg = 0x4e01c,
1631 .enable_reg = 0x4e01c,
1632 .enable_mask = BIT(0),
1646 .halt_reg = 0x4e058,
1649 .enable_reg = 0x4e058,
1650 .enable_mask = BIT(0),
1664 .halt_reg = 0x4e050,
1667 .enable_reg = 0x4e050,
1668 .enable_mask = BIT(0),
1682 .halt_reg = 0x4f03c,
1685 .enable_reg = 0x4f03c,
1686 .enable_mask = BIT(0),
1700 .halt_reg = 0x4f040,
1703 .enable_reg = 0x4f040,
1704 .enable_mask = BIT(0),
1718 .halt_reg = 0x4f048,
1721 .enable_reg = 0x4f048,
1722 .enable_mask = BIT(0),
1736 .halt_reg = 0x4f058,
1739 .enable_reg = 0x4f058,
1740 .enable_mask = BIT(0),
1754 .halt_reg = 0x4f050,
1757 .enable_reg = 0x4f050,
1758 .enable_mask = BIT(0),
1772 .halt_reg = 0x58050,
1775 .enable_reg = 0x58050,
1776 .enable_mask = BIT(0),
1790 .halt_reg = 0x54018,
1793 .enable_reg = 0x54018,
1794 .enable_mask = BIT(0),
1808 .halt_reg = 0x55018,
1811 .enable_reg = 0x55018,
1812 .enable_mask = BIT(0),
1826 .halt_reg = 0x50004,
1829 .enable_reg = 0x50004,
1830 .enable_mask = BIT(0),
1844 .halt_reg = 0x52018,
1847 .enable_reg = 0x52018,
1848 .enable_mask = BIT(0),
1862 .halt_reg = 0x53018,
1865 .enable_reg = 0x53018,
1866 .enable_mask = BIT(0),
1880 .halt_reg = 0x56004,
1883 .enable_reg = 0x56004,
1884 .enable_mask = BIT(0),
1898 .halt_reg = 0x58038,
1901 .enable_reg = 0x58038,
1902 .enable_mask = BIT(0),
1916 .halt_reg = 0x58044,
1919 .enable_reg = 0x58044,
1920 .enable_mask = BIT(0),
1934 .halt_reg = 0x58048,
1937 .enable_reg = 0x58048,
1938 .enable_mask = BIT(0),
1951 .halt_reg = 0x08000,
1954 .enable_reg = 0x08000,
1955 .enable_mask = BIT(0),
1969 .halt_reg = 0x09000,
1972 .enable_reg = 0x09000,
1973 .enable_mask = BIT(0),
1987 .halt_reg = 0x0a000,
1990 .enable_reg = 0x0a000,
1991 .enable_mask = BIT(0),
2005 .halt_reg = 0x4d07c,
2008 .enable_reg = 0x4d07c,
2009 .enable_mask = BIT(0),
2022 .halt_reg = 0x4d080,
2025 .enable_reg = 0x4d080,
2026 .enable_mask = BIT(0),
2039 .halt_reg = 0x4d094,
2042 .enable_reg = 0x4d094,
2043 .enable_mask = BIT(0),
2057 .halt_reg = 0x4d098,
2060 .enable_reg = 0x4d098,
2061 .enable_mask = BIT(0),
2075 .halt_reg = 0x4d088,
2078 .enable_reg = 0x4d088,
2079 .enable_mask = BIT(0),
2093 .halt_reg = 0x4d084,
2096 .enable_reg = 0x4d084,
2097 .enable_mask = BIT(0),
2111 .halt_reg = 0x4d090,
2114 .enable_reg = 0x4d090,
2115 .enable_mask = BIT(0),
2129 .halt_reg = 0x49000,
2132 .enable_reg = 0x49000,
2133 .enable_mask = BIT(0),
2146 .halt_reg = 0x49004,
2149 .enable_reg = 0x49004,
2150 .enable_mask = BIT(0),
2163 .halt_reg = 0x59028,
2166 .enable_reg = 0x59028,
2167 .enable_mask = BIT(0),
2180 .halt_reg = 0x59020,
2183 .enable_reg = 0x59020,
2184 .enable_mask = BIT(0),
2198 .halt_reg = 0x4400c,
2201 .enable_reg = 0x4400c,
2202 .enable_mask = BIT(0),
2216 .halt_reg = 0x44004,
2219 .enable_reg = 0x44004,
2220 .enable_mask = BIT(0),
2233 .halt_reg = 0x4201c,
2236 .enable_reg = 0x4201c,
2237 .enable_mask = BIT(0),
2250 .halt_reg = 0x42018,
2253 .enable_reg = 0x42018,
2254 .enable_mask = BIT(0),
2268 .halt_reg = 0x4301c,
2271 .enable_reg = 0x4301c,
2272 .enable_mask = BIT(0),
2285 .halt_reg = 0x43018,
2288 .enable_reg = 0x43018,
2289 .enable_mask = BIT(0),
2303 .halt_reg = 0x4102c,
2306 .enable_reg = 0x4102c,
2307 .enable_mask = BIT(0),
2318 .halt_reg = 0x41008,
2321 .enable_reg = 0x41008,
2322 .enable_mask = BIT(0),
2335 .halt_reg = 0x41030,
2338 .enable_reg = 0x41030,
2339 .enable_mask = BIT(0),
2352 .halt_reg = 0x41004,
2355 .enable_reg = 0x41004,
2356 .enable_mask = BIT(0),
2370 .halt_reg = 0x4c020,
2373 .enable_reg = 0x4c020,
2374 .enable_mask = BIT(0),
2387 .halt_reg = 0x4c024,
2390 .enable_reg = 0x4c024,
2391 .enable_mask = BIT(0),
2404 .halt_reg = 0x4c02c,
2407 .enable_reg = 0x4c02c,
2408 .enable_mask = BIT(0),
2422 .halt_reg = 0x4c01c,
2425 .enable_reg = 0x4c01c,
2426 .enable_mask = BIT(0),
2440 .gdscr = 0x4d078,
2441 .cxcs = (unsigned int []) { 0x4d080, 0x4d088 },
2450 .gdscr = 0x5901c,
2451 .cxcs = (unsigned int []) { 0x59020 },
2460 .gdscr = 0x4c018,
2461 .cxcs = (unsigned int []) { 0x4c024, 0x4c01c },
2470 .gdscr = 0x4c028,
2471 .cxcs = (unsigned int []) { 0x4c02c },
2481 .gdscr = 0x58034,
2482 .cxcs = (unsigned int []) { 0x58038, 0x58048, 0x58050 },
2634 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
2635 [GCC_BLSP1_BCR] = { 0x01000 },
2636 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
2637 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
2638 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
2639 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
2640 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
2641 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
2642 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
2643 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
2644 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
2645 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
2646 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
2647 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
2648 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
2649 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
2650 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
2651 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
2652 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
2653 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
2654 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
2655 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
2656 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
2657 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
2658 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
2659 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
2660 [GCC_CAMSS_TOP_AHB_BCR] = { 0x5a018 },
2661 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
2662 [GCC_CRYPTO_BCR] = { 0x16000 },
2663 [GCC_MDSS_BCR] = { 0x4d074 },
2664 [GCC_OXILI_BCR] = { 0x59018 },
2665 [GCC_PDM_BCR] = { 0x44000 },
2666 [GCC_PRNG_BCR] = { 0x13000 },
2667 [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2668 [GCC_SDCC1_BCR] = { 0x42000 },
2669 [GCC_SDCC2_BCR] = { 0x43000 },
2670 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
2671 [GCC_USB2A_PHY_BCR] = { 0x41028 },
2672 [GCC_USB2_HS_PHY_ONLY_BCR] = { .reg = 0x41034, .udelay = 15 },
2673 [GCC_USB_HS_BCR] = { 0x41000 },
2674 [GCC_VENUS0_BCR] = { 0x4c014 },
2676 [GCC_MSS_RESTART] = { 0x3e000 },
2683 .max_register = 0x80000,