Lines Matching +full:0 +full:x4c000
14 #define MBS_CHECKSUM_ERROR 0x4010
15 #define MBS_INVALID_PRODUCT_KEY 0x4020
55 #define PDS_PLOGI_PENDING 0x03
56 #define PDS_PLOGI_COMPLETE 0x04
57 #define PDS_PRLI_PENDING 0x05
58 #define PDS_PRLI_COMPLETE 0x06
59 #define PDS_PORT_UNAVAILABLE 0x07
60 #define PDS_PRLO_PENDING 0x09
61 #define PDS_LOGO_PENDING 0x11
62 #define PDS_PRLI2_PENDING 0x12
78 /* Bits 15-0 of word 0 */
80 /* Bits 15-0 of word 3 */
87 uint16_t prli_nvme_svc_param_word_0; /* Bits 15-0 of word 0 */
88 uint16_t prli_nvme_svc_param_word_3; /* Bits 15-0 of word 3 */
111 u8 prli_svc_param_word_0[2]; /* Bits 15-0 of word 0 */
112 u8 prli_svc_param_word_3[2]; /* Bits 15-0 of word 3 */
163 * BIT 0 = Control Enable
166 * BIT 0-7 = Reserved
171 * BIT 0-7 = Reserved
176 * BIT 0-7 = Reserved
201 * BIT 0 = Enable spinup delay
243 * BIT 0 = Selective Login
363 * BIT 0 = Enable Hard Loop Id
384 * BIT 0 = Operation Mode bit 0
388 * BIT 4 = Connection Options bit 0
405 * BIT 0 = Reserved
409 * BIT 4 = FCP RSP Payload bit 0
419 * BIT 13 = Data Rate bit 0
424 * BIT 29 = Enable response queue 0 in index shadowing
425 * BIT 30 = Enable request queue 0 out index shadowing
437 #define COMMAND_BIDIRECTIONAL 0x75
474 #define COMMAND_TYPE_6 0x48 /* Command Type 6 entry */
515 #define COMMAND_TYPE_7 0x18 /* Command Type 7 entry */
526 #define FW_MAX_TIMEOUT 0x1999
544 #define TSK_SIMPLE 0
561 #define COMMAND_TYPE_CRC_2 0x6A /* Command Type CRC_2 (Type 6)
594 uint16_t reserved_1; /* MUST be set to 0. */
601 #define STATUS_TYPE 0x03 /* Status entry. */
661 #define CS_DATA_REASSEMBLY_ERROR 0x11 /* Data Reassembly Error.. */
662 #define CS_ABTS_BY_TARGET 0x13 /* Target send ABTS to abort IOCB. */
663 #define CS_FW_RESOURCE 0x2C /* Firmware Resource Unavailable. */
664 #define CS_TASK_MGMT_OVERRUN 0x30 /* Task management overrun (8+). */
665 #define CS_ABORT_BY_TARGET 0x47 /* Abort By Target. */
670 #define MARKER_TYPE 0x04 /* Marker entry. */
681 uint8_t modifier; /* Modifier (7-0). */
682 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
699 #define CT_IOCB_TYPE 0x29 /* CT Pass-Through IOCB entry */
730 #define PURX_ELS_HEADER_SIZE 0x18
735 #define PUREX_IOCB_TYPE 0x51 /* CT Pass Through IOCB entry */
777 #define ELS_IOCB_TYPE 0x53 /* ELS Pass-Through IOCB entry */
807 #define EPD_ELS_COMMAND (0 << 13)
820 __le64 tx_address __packed; /* DSD 0 address. */
821 __le32 tx_len; /* DSD 0 length. */
872 #define MBX_IOCB_TYPE 0x39
885 #define LOGINOUT_PORT_IOCB_TYPE 0x52 /* Login/Logout Port entry. */
895 #define CS_LOGIO_ERROR 0x31 /* Login/Logout IOCB error. */
914 #define LCF_COMMAND_PLOGI 0x00 /* PLOGI. */
915 #define LCF_COMMAND_PRLI 0x01 /* PRLI. */
916 #define LCF_COMMAND_PDISC 0x02 /* PDISC. */
917 #define LCF_COMMAND_ADISC 0x03 /* ADISC. */
918 #define LCF_COMMAND_LOGO 0x08 /* LOGO. */
919 #define LCF_COMMAND_PRLO 0x09 /* PRLO. */
920 #define LCF_COMMAND_TPRLO 0x0A /* TPRLO. */
932 #define LSC_SCODE_NOLINK 0x01
933 #define LSC_SCODE_NOIOCB 0x02
934 #define LSC_SCODE_NOXCB 0x03
935 #define LSC_SCODE_CMD_FAILED 0x04
936 #define LSC_SCODE_NOFABRIC 0x05
937 #define LSC_SCODE_FW_NOT_READY 0x07
938 #define LSC_SCODE_NOT_LOGGED_IN 0x09
939 #define LSC_SCODE_NOPCB 0x0A
941 #define LSC_SCODE_ELS_REJECT 0x18
942 #define LSC_SCODE_CMD_PARAM_ERR 0x19
943 #define LSC_SCODE_PORTID_USED 0x1A
944 #define LSC_SCODE_NPORT_USED 0x1B
945 #define LSC_SCODE_NONPORT 0x1C
946 #define LSC_SCODE_LOGGED_IN 0x1D
947 #define LSC_SCODE_NOFLOGI_ACC 0x1F
950 #define TSK_MGMT_IOCB_TYPE 0x14
985 #define ABORT_IOCB_TYPE 0x33
1030 #define ABTS_RCV_TYPE 0x54
1031 #define ABTS_RSP_TYPE 0x55
1038 __le32 handle; /* type 0x55 only */
1040 __le16 comp_status; /* type 0x55 only */
1041 __le16 nport_handle; /* type 0x54 only */
1043 __le16 control_flags; /* type 0x55 only */
1094 #define BA_RJT_EXP_NO_ADDITIONAL 0
1104 #define BA_RJT_RSN_VENDOR_SPECIFIC 0xff
1107 #define FC_TYPE_BLD 0x000 /* Basic link data */
1108 #define FC_F_CTL_RSP_CNTXT 0x800000 /* Responder of exchange */
1109 #define FC_F_CTL_LAST_SEQ 0x100000 /* Last sequence */
1110 #define FC_F_CTL_END_SEQ 0x80000 /* Last sequence */
1111 #define FC_F_CTL_SEQ_INIT 0x010000 /* Sequence initiative */
1112 #define FC_ROUTING_BLD 0x80 /* Basic link data frame */
1113 #define FC_R_CTL_BLD_BA_ACC 0x04 /* BA_ACC (basic accept) */
1121 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000
1122 #define FARX_ACCESS_FLASH_DATA 0x7FF00000
1123 #define FARX_ACCESS_NVRAM_CONF 0x7FFF0000
1124 #define FARX_ACCESS_NVRAM_DATA 0x7FFE0000
1126 #define FA_NVRAM_FUNC0_ADDR 0x80
1127 #define FA_NVRAM_FUNC1_ADDR 0x180
1129 #define FA_NVRAM_VPD_SIZE 0x200
1130 #define FA_NVRAM_VPD0_ADDR 0x00
1131 #define FA_NVRAM_VPD1_ADDR 0x100
1133 #define FA_BOOT_CODE_ADDR 0x00000
1139 #define FA_RISC_CODE_ADDR 0x20000
1142 #define FA_FLASH_DESCR_ADDR_24 0x11000
1143 #define FA_FLASH_LAYOUT_ADDR_24 0x11400
1144 #define FA_NPIV_CONF0_ADDR_24 0x16000
1145 #define FA_NPIV_CONF1_ADDR_24 0x17000
1147 #define FA_FW_AREA_ADDR 0x40000
1148 #define FA_VPD_NVRAM_ADDR 0x48000
1149 #define FA_FEATURE_ADDR 0x4C000
1150 #define FA_FLASH_DESCR_ADDR 0x50000
1151 #define FA_FLASH_LAYOUT_ADDR 0x50400
1152 #define FA_HW_EVENT0_ADDR 0x54000
1153 #define FA_HW_EVENT1_ADDR 0x54400
1154 #define FA_HW_EVENT_SIZE 0x200
1156 #define FA_NPIV_CONF0_ADDR 0x5C000
1157 #define FA_NPIV_CONF1_ADDR 0x5D000
1158 #define FA_FCP_PRIO0_ADDR 0x10000
1159 #define FA_FCP_PRIO1_ADDR 0x12000
1164 #define HW_EVENT_RESET_ERR 0xF00B
1165 #define HW_EVENT_ISP_ERR 0xF020
1166 #define HW_EVENT_PARITY_ERR 0xF022
1167 #define HW_EVENT_NVRAM_CHKSUM_ERR 0xF023
1168 #define HW_EVENT_FLASH_FW_ERR 0xF024
1179 #define PBM_PCI_33MHZ (0 << 8)
1189 #define MWB_512_BYTES (0 << 4)
1232 #define HCCRX_NOOP 0x00000000
1234 #define HCCRX_SET_RISC_RESET 0x10000000
1236 #define HCCRX_CLR_RISC_RESET 0x20000000
1238 #define HCCRX_SET_RISC_PAUSE 0x30000000
1240 #define HCCRX_REL_RISC_PAUSE 0x40000000
1242 #define HCCRX_SET_HOST_INT 0x50000000
1244 #define HCCRX_CLR_HOST_INT 0x60000000
1246 #define HCCRX_CLR_RISC_INT 0xA0000000
1323 #define RISC_REGISTER_BASE_OFFSET 0x7010
1324 #define RISC_REGISTER_WINDOW_OFFSET 0x6
1326 /* RISC-RISC semaphore/flag register (risc address 0x7016) */
1328 #define RISC_SEMAPHORE 0x1UL
1330 #define RISC_SEMAPHORE_CLR (RISC_SEMAPHORE_WE | 0x0UL)
1333 #define RISC_SEMAPHORE_FORCE 0x8000UL
1335 #define RISC_SEMAPHORE_FORCE_CLR (RISC_SEMAPHORE_FORCE_WE | 0x0UL)
1346 #define TC_AEN_DISABLE 0
1352 #define TC_FCE_OPTIONS 0
1367 * BIT 0 = Enable Hard Loop Id
1412 #define VP_CTRL_IOCB_TYPE 0x30 /* Virtual Port Control entry. */
1424 #define CS_VCE_IOCB_ERROR 0x01 /* Error processing IOCB */
1425 #define CS_VCE_ACQ_ID_ERROR 0x02 /* Error while acquireing ID. */
1426 #define CS_VCE_BUSY 0x05 /* Firmware not ready to accept cmd. */
1429 #define VCE_COMMAND_ENABLE_VPS 0x00 /* Enable VPs. */
1430 #define VCE_COMMAND_DISABLE_VPS 0x08 /* Disable VPs. */
1431 #define VCE_COMMAND_DISABLE_VPS_REINIT 0x09 /* Disable VPs and reinit link. */
1432 #define VCE_COMMAND_DISABLE_VPS_LOGO 0x0a /* Disable VPs and LOGO ports. */
1433 #define VCE_COMMAND_DISABLE_VPS_LOGO_ALL 0x0b /* Disable VPs and LOGO ports. */
1448 #define VP_CONFIG_IOCB_TYPE 0x31 /* Virtual Port Config entry. */
1463 #define CS_VCT_STS_ERROR 0x01 /* Specified VPs were not disabled. */
1464 #define CS_VCT_CNT_ERROR 0x02 /* Invalid VP count. */
1465 #define CS_VCT_ERROR 0x03 /* Unknown error. */
1466 #define CS_VCT_IDX_ERROR 0x02 /* Invalid VP index. */
1467 #define CS_VCT_BUSY 0x05 /* Firmware not ready to accept cmd. */
1470 #define VCT_COMMAND_MOD_VPS 0x00 /* Modify VP configurations. */
1471 #define VCT_COMMAND_MOD_ENABLE_VPS 0x01 /* Modify configuration & enable VPs. */
1495 #define VP_RPT_ID_IOCB_TYPE 0x32 /* Report ID Acquisition entry. */
1521 uint8_t vp_idx; /* Format 0=reserved */
1522 uint8_t vp_status; /* Format 0=reserved */
1528 /* format 0 loop */
1536 #define TOPO_MASK 0xE
1537 #define TOPO_FL 0x2
1538 #define TOPO_N2N 0x4
1539 #define TOPO_F 0x6
1574 #define VF_EVFP_IOCB_TYPE 0x26 /* Exchange Virtual Fabric Parameters entry. */
1593 __le64 tx_address __packed; /* Data segment 0 address. */
1594 uint32_t tx_len; /* Data segment 0 length. */
1644 #define FLT_REG_FW 0x01
1645 #define FLT_REG_BOOT_CODE 0x07
1646 #define FLT_REG_VPD_0 0x14
1647 #define FLT_REG_NVRAM_0 0x15
1648 #define FLT_REG_VPD_1 0x16
1649 #define FLT_REG_NVRAM_1 0x17
1650 #define FLT_REG_VPD_2 0xD4
1651 #define FLT_REG_NVRAM_2 0xD5
1652 #define FLT_REG_VPD_3 0xD6
1653 #define FLT_REG_NVRAM_3 0xD7
1654 #define FLT_REG_FDT 0x1a
1655 #define FLT_REG_FLT 0x1c
1656 #define FLT_REG_HW_EVENT_0 0x1d
1657 #define FLT_REG_HW_EVENT_1 0x1f
1658 #define FLT_REG_NPIV_CONF_0 0x29
1659 #define FLT_REG_NPIV_CONF_1 0x2a
1660 #define FLT_REG_GOLD_FW 0x2f
1661 #define FLT_REG_FCP_PRIO_0 0x87
1662 #define FLT_REG_FCP_PRIO_1 0x88
1663 #define FLT_REG_CNA_FW 0x97
1664 #define FLT_REG_BOOT_CODE_8044 0xA2
1665 #define FLT_REG_FCOE_FW 0xA4
1666 #define FLT_REG_FCOE_NVRAM_0 0xAA
1667 #define FLT_REG_FCOE_NVRAM_1 0xAC
1670 #define FLT_REG_IMG_PRI_27XX 0x95
1671 #define FLT_REG_IMG_SEC_27XX 0x96
1672 #define FLT_REG_FW_SEC_27XX 0x02
1673 #define FLT_REG_BOOTLOAD_SEC_27XX 0x9
1674 #define FLT_REG_VPD_SEC_27XX_0 0x50
1675 #define FLT_REG_VPD_SEC_27XX_1 0x52
1676 #define FLT_REG_VPD_SEC_27XX_2 0xD8
1677 #define FLT_REG_VPD_SEC_27XX_3 0xDA
1678 #define FLT_REG_NVME_PARAMS_27XX 0x21
1681 #define FLT_REG_AUX_IMG_PRI_28XX 0x125
1682 #define FLT_REG_AUX_IMG_SEC_28XX 0x126
1683 #define FLT_REG_VPD_SEC_28XX_0 0x10C
1684 #define FLT_REG_VPD_SEC_28XX_1 0x10E
1685 #define FLT_REG_VPD_SEC_28XX_2 0x110
1686 #define FLT_REG_VPD_SEC_28XX_3 0x112
1687 #define FLT_REG_NVRAM_SEC_28XX_0 0x10D
1688 #define FLT_REG_NVRAM_SEC_28XX_1 0x10F
1689 #define FLT_REG_NVRAM_SEC_28XX_2 0x111
1690 #define FLT_REG_NVRAM_SEC_28XX_3 0x113
1691 #define FLT_REG_MPI_PRI_28XX 0xD3
1692 #define FLT_REG_MPI_SEC_28XX 0xF0
1693 #define FLT_REG_PEP_PRI_28XX 0xD1
1694 #define FLT_REG_PEP_SEC_28XX 0xF1
1695 #define FLT_REG_NVME_PARAMS_PRI_28XX 0x14E
1696 #define FLT_REG_NVME_PARAMS_SEC_28XX 0x179
1716 #define FLT_MAX_REGIONS 0xFF
1741 #define MBA_ISP84XX_ALERT 0x800f /* Alert Notification. */
1742 #define A84_PANIC_RECOVERY 0x1
1743 #define A84_OP_LOGIN_COMPLETE 0x2
1744 #define A84_DIAG_LOGIN_COMPLETE 0x3
1745 #define A84_GOLD_LOGIN_COMPLETE 0x4
1747 #define MBC_ISP84XX_RESET 0x3a /* Reset. */
1755 #define VERIFY_CHIP_IOCB_TYPE 0x1B
1797 #define CS_VCS_CHIP_FAILURE 0x3
1798 #define CS_VCS_BAD_EXCHANGE 0x8
1799 #define CS_VCS_SEQ_COMPLETEi 0x40
1802 #define VFC_CHECKSUM_ERROR 0x1
1803 #define VFC_INVALID_LEN 0x2
1804 #define VFC_ALREADY_IN_PROGRESS 0x8
1814 #define ACCESS_CHIP_IOCB_TYPE 0x2B
1824 #define ACO_DUMP_MEMORY 0x0
1825 #define ACO_LOAD_MEMORY 0x1
1826 #define ACO_CHANGE_CONFIG_PARAM 0x2
1827 #define ACO_REQUEST_INFO 0x3
1862 #define MBA_DCBX_START 0x8016
1863 #define MBA_DCBX_COMPLETE 0x8030
1864 #define MBA_FCF_CONF_ERR 0x8031
1865 #define MBA_DCBX_PARAM_UPDATE 0x8032
1866 #define MBA_IDC_COMPLETE 0x8100
1867 #define MBA_IDC_NOTIFY 0x8101
1868 #define MBA_IDC_TIME_EXT 0x8102
1870 #define MBC_IDC_ACK 0x101
1871 #define MBC_RESTART_MPI_FW 0x3d
1872 #define MBC_FLASH_ACCESS_CTRL 0x3e /* Control flash access. */
1873 #define MBC_GET_XGMAC_STATS 0x7a
1874 #define MBC_GET_DCBX_PARAMS 0x51
1879 #define MBC_WRITE_REMOTE_REG 0x0001 /* Write remote register */
1880 #define MBC_READ_REMOTE_REG 0x0009 /* Read remote register */
1881 #define MBC_RESTART_NIC_FIRMWARE 0x003d /* Restart NIC firmware */
1882 #define MBC_SET_ACCESS_CONTROL 0x003e /* Access control command */
1887 #define FAC_OPT_CMD_SUBCODE 0xff
1890 #define FAC_OPT_CMD_WRITE_PROTECT 0x00
1891 #define FAC_OPT_CMD_WRITE_ENABLE 0x01
1892 #define FAC_OPT_CMD_ERASE_SECTOR 0x02
1893 #define FAC_OPT_CMD_LOCK_SEMAPHORE 0x03
1894 #define FAC_OPT_CMD_UNLOCK_SEMAPHORE 0x04
1895 #define FAC_OPT_CMD_GET_SECTOR_SIZE 0x05
1902 #define LR_DIST_NV_MASK 0xf
1906 #define FAC_SEMAPHORE_UNLOCK 0
1960 * BIT 0 = Enable spinup delay
2012 * BIT 0 = Selective Login
2051 /* Offset 406 (0x196) Enhanced Features
2052 * BIT 0 = Extended BB credits for LR
2054 * BIT 2-5 = Distance Support if BIT 0 is on
2126 * BIT 0-3 = Reserved
2139 * BIT 0 = Operation Mode bit 0
2157 * BIT 0-3 = Reserved
2158 * BIT 4 = FCP RSP Payload bit 0
2171 * BIT 28 = SPMA selection bit 0
2204 #define FARX_ACCESS_FLASH_CONF_81XX 0x7FFD0000
2205 #define FARX_ACCESS_FLASH_DATA_81XX 0x7F800000
2206 #define FARX_ACCESS_FLASH_CONF_28XX 0x7FFD0000
2207 #define FARX_ACCESS_FLASH_DATA_28XX 0x7F7D0000
2211 #define QLFC_FCP_PRIO_DISABLE 0x0
2212 #define QLFC_FCP_PRIO_ENABLE 0x1
2213 #define QLFC_FCP_PRIO_GET_CONFIG 0x2
2214 #define QLFC_FCP_PRIO_SET_CONFIG 0x3
2219 #define FCP_PRIO_ENTRY_VALID 0x1
2220 #define FCP_PRIO_ENTRY_TAG_VALID 0x2
2221 #define FCP_PRIO_ENTRY_SPID_VALID 0x4
2222 #define FCP_PRIO_ENTRY_DPID_VALID 0x8
2223 #define FCP_PRIO_ENTRY_LUNB_VALID 0x10
2224 #define FCP_PRIO_ENTRY_LUNE_VALID 0x20
2225 #define FCP_PRIO_ENTRY_SWWN_VALID 0x40
2226 #define FCP_PRIO_ENTRY_DWWN_VALID 0x80
2249 #define FCP_PRIO_ATTR_DISABLE 0x0
2250 #define FCP_PRIO_ATTR_ENABLE 0x1
2251 #define FCP_PRIO_ATTR_PERSIST 0x2
2261 #define FA_FCP_PRIO0_ADDR_25 0x3C000
2262 #define FA_FCP_PRIO1_ADDR_25 0x3E000
2265 #define FA_BOOT_CODE_ADDR_81 0x80000
2266 #define FA_RISC_CODE_ADDR_81 0xA0000
2267 #define FA_FW_AREA_ADDR_81 0xC0000
2268 #define FA_VPD_NVRAM_ADDR_81 0xD0000
2269 #define FA_VPD0_ADDR_81 0xD0000
2270 #define FA_VPD1_ADDR_81 0xD0400
2271 #define FA_NVRAM0_ADDR_81 0xD0080
2272 #define FA_NVRAM1_ADDR_81 0xD0180
2273 #define FA_FEATURE_ADDR_81 0xD4000
2274 #define FA_FLASH_DESCR_ADDR_81 0xD8000
2275 #define FA_FLASH_LAYOUT_ADDR_81 0xD8400
2276 #define FA_HW_EVENT0_ADDR_81 0xDC000
2277 #define FA_HW_EVENT1_ADDR_81 0xDC400
2278 #define FA_NPIV_CONF0_ADDR_81 0xD1000
2279 #define FA_NPIV_CONF1_ADDR_81 0xD2000
2282 #define FA_FLASH_LAYOUT_ADDR_83 (0x3F1000/4)
2283 #define FA_FLASH_LAYOUT_ADDR_28 (0x11000/4)
2285 #define NVRAM_DUAL_FCP_NVME_FLAG_OFFSET 0x196