Lines Matching +full:0 +full:x4c000
45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
78 .n_reg = 0x2000c,
79 .config_reg = 0x20010,
80 .mode_reg = 0x20000,
81 .status_reg = 0x2001c,
94 .enable_reg = 0x45000,
107 .l_reg = 0x4a004,
108 .m_reg = 0x4a008,
109 .n_reg = 0x4a00c,
110 .config_reg = 0x4a010,
111 .mode_reg = 0x4a000,
112 .status_reg = 0x4a01c,
125 .enable_reg = 0x45000,
138 .l_reg = 0x23004,
139 .m_reg = 0x23008,
140 .n_reg = 0x2300c,
141 .config_reg = 0x23010,
142 .mode_reg = 0x23000,
143 .status_reg = 0x2301c,
156 .enable_reg = 0x45000,
169 { P_XO, 0 },
179 { P_XO, 0 },
191 { P_XO, 0 },
205 { P_XO, 0 },
217 { P_XO, 0 },
227 { P_XO, 0 },
241 { P_XO, 0 },
253 { P_XO, 0, },
263 { P_XO, 0 },
275 { P_XO, 0 },
287 { P_XO, 0 },
299 { P_XO, 0 },
313 { P_XO, 0 },
327 { P_XO, 0 },
343 { P_XO, 0 },
359 { P_XO, 0 },
369 { P_XO, 0 },
383 .cmd_rcgr = 0x27000,
395 .cmd_rcgr = 0x26004,
408 F(80000000, P_GPLL0, 10, 0, 0),
413 .cmd_rcgr = 0x5a000,
427 F(19200000, P_XO, 1, 0, 0),
428 F(50000000, P_GPLL0, 16, 0, 0),
429 F(100000000, P_GPLL0, 8, 0, 0),
430 F(133330000, P_GPLL0, 6, 0, 0),
435 .cmd_rcgr = 0x46000,
448 F(100000000, P_GPLL0, 8, 0, 0),
449 F(200000000, P_GPLL0, 4, 0, 0),
454 .cmd_rcgr = 0x4e020,
467 .cmd_rcgr = 0x4f020,
480 F(19200000, P_XO, 1, 0, 0),
481 F(50000000, P_GPLL0_AUX, 16, 0, 0),
482 F(80000000, P_GPLL0_AUX, 10, 0, 0),
483 F(100000000, P_GPLL0_AUX, 8, 0, 0),
484 F(160000000, P_GPLL0_AUX, 5, 0, 0),
485 F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
486 F(200000000, P_GPLL0_AUX, 4, 0, 0),
487 F(266670000, P_GPLL0_AUX, 3, 0, 0),
488 F(294912000, P_GPLL1, 3, 0, 0),
489 F(310000000, P_GPLL2, 3, 0, 0),
490 F(400000000, P_GPLL0_AUX, 2, 0, 0),
495 .cmd_rcgr = 0x59000,
508 F(50000000, P_GPLL0, 16, 0, 0),
509 F(80000000, P_GPLL0, 10, 0, 0),
510 F(100000000, P_GPLL0, 8, 0, 0),
511 F(160000000, P_GPLL0, 5, 0, 0),
512 F(177780000, P_GPLL0, 4.5, 0, 0),
513 F(200000000, P_GPLL0, 4, 0, 0),
514 F(266670000, P_GPLL0, 3, 0, 0),
515 F(320000000, P_GPLL0, 2.5, 0, 0),
516 F(400000000, P_GPLL0, 2, 0, 0),
517 F(465000000, P_GPLL2, 2, 0, 0),
522 .cmd_rcgr = 0x58000,
535 F(19200000, P_XO, 1, 0, 0),
536 F(50000000, P_GPLL0, 16, 0, 0),
541 .cmd_rcgr = 0x0200c,
559 F(4800000, P_XO, 4, 0, 0),
560 F(9600000, P_XO, 2, 0, 0),
562 F(19200000, P_XO, 1, 0, 0),
564 F(50000000, P_GPLL0, 16, 0, 0),
569 .cmd_rcgr = 0x02024,
583 .cmd_rcgr = 0x03000,
596 .cmd_rcgr = 0x03014,
610 .cmd_rcgr = 0x04000,
623 .cmd_rcgr = 0x04024,
637 .cmd_rcgr = 0x05000,
650 .cmd_rcgr = 0x05024,
664 .cmd_rcgr = 0x06000,
677 .cmd_rcgr = 0x06024,
691 .cmd_rcgr = 0x07000,
704 .cmd_rcgr = 0x07024,
722 F(19200000, P_XO, 1, 0, 0),
737 .cmd_rcgr = 0x02044,
751 .cmd_rcgr = 0x03034,
765 F(19200000, P_XO, 1, 0, 0),
770 .cmd_rcgr = 0x51000,
797 F(100000000, P_GPLL0, 8, 0, 0),
798 F(200000000, P_GPLL0, 4, 0, 0),
803 .cmd_rcgr = 0x54000,
817 .cmd_rcgr = 0x55000,
831 F(133330000, P_GPLL0, 6, 0, 0),
832 F(266670000, P_GPLL0, 3, 0, 0),
833 F(320000000, P_GPLL0, 2.5, 0, 0),
838 .cmd_rcgr = 0x57000,
851 F(9600000, P_XO, 2, 0, 0),
853 F(66670000, P_GPLL0, 12, 0, 0),
858 .cmd_rcgr = 0x52000,
872 .cmd_rcgr = 0x53000,
886 F(100000000, P_GPLL0, 8, 0, 0),
887 F(200000000, P_GPLL0, 4, 0, 0),
892 .cmd_rcgr = 0x4e000,
905 .cmd_rcgr = 0x4f000,
918 F(160000000, P_GPLL0, 5, 0, 0),
919 F(320000000, P_GPLL0, 2.5, 0, 0),
920 F(465000000, P_GPLL2, 2, 0, 0),
925 .cmd_rcgr = 0x58018,
938 F(50000000, P_GPLL0, 16, 0, 0),
939 F(80000000, P_GPLL0, 10, 0, 0),
940 F(100000000, P_GPLL0, 8, 0, 0),
941 F(160000000, P_GPLL0, 5, 0, 0),
946 .cmd_rcgr = 0x16004,
981 F(19200000, P_XO, 1, 0, 0),
986 .cmd_rcgr = 0x08004,
1000 .cmd_rcgr = 0x09004,
1014 .cmd_rcgr = 0x0a004,
1028 .cmd_rcgr = 0x4d044,
1041 F(19200000, P_XO, 1, 0, 0),
1046 .cmd_rcgr = 0x4d05c,
1059 F(50000000, P_GPLL0, 16, 0, 0),
1060 F(80000000, P_GPLL0, 10, 0, 0),
1061 F(100000000, P_GPLL0, 8, 0, 0),
1062 F(160000000, P_GPLL0, 5, 0, 0),
1063 F(177780000, P_GPLL0, 4.5, 0, 0),
1064 F(200000000, P_GPLL0, 4, 0, 0),
1065 F(266670000, P_GPLL0, 3, 0, 0),
1066 F(320000000, P_GPLL0, 2.5, 0, 0),
1071 .cmd_rcgr = 0x4d014,
1084 .cmd_rcgr = 0x4d000,
1098 F(19200000, P_XO, 1, 0, 0),
1103 .cmd_rcgr = 0x4d02c,
1116 F(64000000, P_GPLL0, 12.5, 0, 0),
1121 .cmd_rcgr = 0x44010,
1138 F(50000000, P_GPLL0, 16, 0, 0),
1139 F(100000000, P_GPLL0, 8, 0, 0),
1140 F(177770000, P_GPLL0, 4.5, 0, 0),
1145 .cmd_rcgr = 0x42004,
1163 F(50000000, P_GPLL0, 16, 0, 0),
1164 F(100000000, P_GPLL0, 8, 0, 0),
1165 F(200000000, P_GPLL0, 4, 0, 0),
1170 .cmd_rcgr = 0x43004,
1184 F(155000000, P_GPLL2, 6, 0, 0),
1185 F(310000000, P_GPLL2, 3, 0, 0),
1186 F(400000000, P_GPLL0, 2, 0, 0),
1191 .cmd_rcgr = 0x1207c,
1204 F(19200000, P_XO, 1, 0, 0),
1205 F(100000000, P_GPLL0, 8, 0, 0),
1206 F(200000000, P_GPLL0, 4, 0, 0),
1207 F(266500000, P_BIMC, 4, 0, 0),
1208 F(400000000, P_GPLL0, 2, 0, 0),
1209 F(533000000, P_BIMC, 2, 0, 0),
1214 .cmd_rcgr = 0x31028,
1228 F(80000000, P_GPLL0, 10, 0, 0),
1233 .cmd_rcgr = 0x41010,
1246 F(3200000, P_XO, 6, 0, 0),
1247 F(6400000, P_XO, 3, 0, 0),
1248 F(9600000, P_XO, 2, 0, 0),
1249 F(19200000, P_XO, 1, 0, 0),
1251 F(66670000, P_GPLL0, 12, 0, 0),
1252 F(80000000, P_GPLL0, 10, 0, 0),
1253 F(100000000, P_GPLL0, 8, 0, 0),
1258 .cmd_rcgr = 0x1c010,
1272 .halt_reg = 0x1c028,
1274 .enable_reg = 0x1c028,
1275 .enable_mask = BIT(0),
1289 .halt_reg = 0x1c024,
1291 .enable_reg = 0x1c024,
1292 .enable_mask = BIT(0),
1318 F(1600000, P_XO, 12, 0, 0),
1322 F(2400000, P_XO, 8, 0, 0),
1326 F(4800000, P_XO, 4, 0, 0),
1330 F(9600000, P_XO, 2, 0, 0),
1337 .cmd_rcgr = 0x1c054,
1351 .halt_reg = 0x1c068,
1353 .enable_reg = 0x1c068,
1354 .enable_mask = BIT(0),
1368 .cmd_rcgr = 0x1c06c,
1382 .halt_reg = 0x1c080,
1384 .enable_reg = 0x1c080,
1385 .enable_mask = BIT(0),
1399 .cmd_rcgr = 0x1c084,
1413 .halt_reg = 0x1c098,
1415 .enable_reg = 0x1c098,
1416 .enable_mask = BIT(0),
1430 F(19200000, P_XO, 1, 0, 0),
1435 .cmd_rcgr = 0x1c034,
1448 .halt_reg = 0x1c04c,
1450 .enable_reg = 0x1c04c,
1451 .enable_mask = BIT(0),
1465 .halt_reg = 0x1c050,
1467 .enable_reg = 0x1c050,
1468 .enable_mask = BIT(0),
1482 F(9600000, P_XO, 2, 0, 0),
1484 F(19200000, P_XO, 1, 0, 0),
1485 F(11289600, P_EXT_MCLK, 1, 0, 0),
1490 .cmd_rcgr = 0x1c09c,
1504 .halt_reg = 0x1c0b0,
1506 .enable_reg = 0x1c0b0,
1507 .enable_mask = BIT(0),
1521 .halt_reg = 0x1c000,
1523 .enable_reg = 0x1c000,
1524 .enable_mask = BIT(0),
1537 .halt_reg = 0x1c004,
1539 .enable_reg = 0x1c004,
1540 .enable_mask = BIT(0),
1553 F(100000000, P_GPLL0, 8, 0, 0),
1554 F(160000000, P_GPLL0, 5, 0, 0),
1555 F(228570000, P_GPLL0, 3.5, 0, 0),
1560 .cmd_rcgr = 0x4C000,
1574 .halt_reg = 0x01008,
1577 .enable_reg = 0x45004,
1591 .halt_reg = 0x01004,
1593 .enable_reg = 0x01004,
1594 .enable_mask = BIT(0),
1608 .halt_reg = 0x02008,
1610 .enable_reg = 0x02008,
1611 .enable_mask = BIT(0),
1625 .halt_reg = 0x02004,
1627 .enable_reg = 0x02004,
1628 .enable_mask = BIT(0),
1642 .halt_reg = 0x03010,
1644 .enable_reg = 0x03010,
1645 .enable_mask = BIT(0),
1659 .halt_reg = 0x0300c,
1661 .enable_reg = 0x0300c,
1662 .enable_mask = BIT(0),
1676 .halt_reg = 0x04020,
1678 .enable_reg = 0x04020,
1679 .enable_mask = BIT(0),
1693 .halt_reg = 0x0401c,
1695 .enable_reg = 0x0401c,
1696 .enable_mask = BIT(0),
1710 .halt_reg = 0x05020,
1712 .enable_reg = 0x05020,
1713 .enable_mask = BIT(0),
1727 .halt_reg = 0x0501c,
1729 .enable_reg = 0x0501c,
1730 .enable_mask = BIT(0),
1744 .halt_reg = 0x06020,
1746 .enable_reg = 0x06020,
1747 .enable_mask = BIT(0),
1761 .halt_reg = 0x0601c,
1763 .enable_reg = 0x0601c,
1764 .enable_mask = BIT(0),
1778 .halt_reg = 0x07020,
1780 .enable_reg = 0x07020,
1781 .enable_mask = BIT(0),
1795 .halt_reg = 0x0701c,
1797 .enable_reg = 0x0701c,
1798 .enable_mask = BIT(0),
1812 .halt_reg = 0x0203c,
1814 .enable_reg = 0x0203c,
1815 .enable_mask = BIT(0),
1829 .halt_reg = 0x0302c,
1831 .enable_reg = 0x0302c,
1832 .enable_mask = BIT(0),
1846 .halt_reg = 0x1300c,
1849 .enable_reg = 0x45004,
1863 .halt_reg = 0x5101c,
1865 .enable_reg = 0x5101c,
1866 .enable_mask = BIT(0),
1880 .halt_reg = 0x51018,
1882 .enable_reg = 0x51018,
1883 .enable_mask = BIT(0),
1897 .halt_reg = 0x4e040,
1899 .enable_reg = 0x4e040,
1900 .enable_mask = BIT(0),
1914 .halt_reg = 0x4e03c,
1916 .enable_reg = 0x4e03c,
1917 .enable_mask = BIT(0),
1931 .halt_reg = 0x4e048,
1933 .enable_reg = 0x4e048,
1934 .enable_mask = BIT(0),
1948 .halt_reg = 0x4e058,
1950 .enable_reg = 0x4e058,
1951 .enable_mask = BIT(0),
1965 .halt_reg = 0x4e050,
1967 .enable_reg = 0x4e050,
1968 .enable_mask = BIT(0),
1982 .halt_reg = 0x4f040,
1984 .enable_reg = 0x4f040,
1985 .enable_mask = BIT(0),
1999 .halt_reg = 0x4f03c,
2001 .enable_reg = 0x4f03c,
2002 .enable_mask = BIT(0),
2016 .halt_reg = 0x4f048,
2018 .enable_reg = 0x4f048,
2019 .enable_mask = BIT(0),
2033 .halt_reg = 0x4f058,
2035 .enable_reg = 0x4f058,
2036 .enable_mask = BIT(0),
2050 .halt_reg = 0x4f050,
2052 .enable_reg = 0x4f050,
2053 .enable_mask = BIT(0),
2067 .halt_reg = 0x58050,
2069 .enable_reg = 0x58050,
2070 .enable_mask = BIT(0),
2084 .halt_reg = 0x54018,
2086 .enable_reg = 0x54018,
2087 .enable_mask = BIT(0),
2101 .halt_reg = 0x55018,
2103 .enable_reg = 0x55018,
2104 .enable_mask = BIT(0),
2118 .halt_reg = 0x50004,
2120 .enable_reg = 0x50004,
2121 .enable_mask = BIT(0),
2135 .halt_reg = 0x57020,
2137 .enable_reg = 0x57020,
2138 .enable_mask = BIT(0),
2152 .halt_reg = 0x57024,
2154 .enable_reg = 0x57024,
2155 .enable_mask = BIT(0),
2169 .halt_reg = 0x57028,
2171 .enable_reg = 0x57028,
2172 .enable_mask = BIT(0),
2186 .halt_reg = 0x52018,
2188 .enable_reg = 0x52018,
2189 .enable_mask = BIT(0),
2203 .halt_reg = 0x53018,
2205 .enable_reg = 0x53018,
2206 .enable_mask = BIT(0),
2220 .halt_reg = 0x5600c,
2222 .enable_reg = 0x5600c,
2223 .enable_mask = BIT(0),
2237 .halt_reg = 0x4e01c,
2239 .enable_reg = 0x4e01c,
2240 .enable_mask = BIT(0),
2254 .halt_reg = 0x4f01c,
2256 .enable_reg = 0x4f01c,
2257 .enable_mask = BIT(0),
2271 .halt_reg = 0x5a014,
2273 .enable_reg = 0x5a014,
2274 .enable_mask = BIT(0),
2288 .halt_reg = 0x56004,
2290 .enable_reg = 0x56004,
2291 .enable_mask = BIT(0),
2305 .halt_reg = 0x58040,
2307 .enable_reg = 0x58040,
2308 .enable_mask = BIT(0),
2322 .halt_reg = 0x5803c,
2324 .enable_reg = 0x5803c,
2325 .enable_mask = BIT(0),
2339 .halt_reg = 0x58038,
2341 .enable_reg = 0x58038,
2342 .enable_mask = BIT(0),
2356 .halt_reg = 0x58044,
2358 .enable_reg = 0x58044,
2359 .enable_mask = BIT(0),
2373 .halt_reg = 0x58048,
2375 .enable_reg = 0x58048,
2376 .enable_mask = BIT(0),
2390 .halt_reg = 0x16024,
2393 .enable_reg = 0x45004,
2394 .enable_mask = BIT(0),
2408 .halt_reg = 0x16020,
2411 .enable_reg = 0x45004,
2426 .halt_reg = 0x1601c,
2429 .enable_reg = 0x45004,
2444 .halt_reg = 0x59024,
2446 .enable_reg = 0x59024,
2447 .enable_mask = BIT(0),
2461 .halt_reg = 0x08000,
2463 .enable_reg = 0x08000,
2464 .enable_mask = BIT(0),
2478 .halt_reg = 0x09000,
2480 .enable_reg = 0x09000,
2481 .enable_mask = BIT(0),
2495 .halt_reg = 0x0a000,
2497 .enable_reg = 0x0a000,
2498 .enable_mask = BIT(0),
2512 .halt_reg = 0x4d07c,
2514 .enable_reg = 0x4d07c,
2515 .enable_mask = BIT(0),
2529 .halt_reg = 0x4d080,
2531 .enable_reg = 0x4d080,
2532 .enable_mask = BIT(0),
2546 .halt_reg = 0x4d094,
2548 .enable_reg = 0x4d094,
2549 .enable_mask = BIT(0),
2563 .halt_reg = 0x4d098,
2565 .enable_reg = 0x4d098,
2566 .enable_mask = BIT(0),
2580 .halt_reg = 0x4D088,
2582 .enable_reg = 0x4D088,
2583 .enable_mask = BIT(0),
2597 .halt_reg = 0x4d084,
2599 .enable_reg = 0x4d084,
2600 .enable_mask = BIT(0),
2614 .halt_reg = 0x4d090,
2616 .enable_reg = 0x4d090,
2617 .enable_mask = BIT(0),
2631 .halt_reg = 0x49000,
2633 .enable_reg = 0x49000,
2634 .enable_mask = BIT(0),
2648 .halt_reg = 0x59028,
2650 .enable_reg = 0x59028,
2651 .enable_mask = BIT(0),
2665 .halt_reg = 0x59020,
2667 .enable_reg = 0x59020,
2668 .enable_mask = BIT(0),
2682 .halt_reg = 0x4400c,
2684 .enable_reg = 0x4400c,
2685 .enable_mask = BIT(0),
2699 .halt_reg = 0x44004,
2701 .enable_reg = 0x44004,
2702 .enable_mask = BIT(0),
2716 .halt_reg = 0x13004,
2719 .enable_reg = 0x45004,
2733 .halt_reg = 0x4201c,
2735 .enable_reg = 0x4201c,
2736 .enable_mask = BIT(0),
2750 .halt_reg = 0x42018,
2752 .enable_reg = 0x42018,
2753 .enable_mask = BIT(0),
2767 .halt_reg = 0x4301c,
2769 .enable_reg = 0x4301c,
2770 .enable_mask = BIT(0),
2784 .halt_reg = 0x43018,
2786 .enable_reg = 0x43018,
2787 .enable_mask = BIT(0),
2801 .cmd_rcgr = 0x32004,
2814 .halt_reg = 0x49004,
2816 .enable_reg = 0x49004,
2817 .enable_mask = BIT(0),
2831 .halt_reg = 0x12018,
2833 .enable_reg = 0x4500c,
2847 .halt_reg = 0x12020,
2849 .enable_reg = 0x4500c,
2863 .halt_reg = 0x12044,
2865 .enable_reg = 0x4500c,
2880 .halt_reg = 0x31024,
2882 .enable_reg = 0x31024,
2883 .enable_mask = BIT(0),
2897 .halt_reg = 0x31040,
2899 .enable_reg = 0x31040,
2900 .enable_mask = BIT(0),
2914 .halt_reg = 0x12034,
2916 .enable_reg = 0x4500c,
2931 .halt_reg = 0x1201c,
2933 .enable_reg = 0x4500c,
2948 .halt_reg = 0x12038,
2950 .enable_reg = 0x4500c,
2965 .halt_reg = 0x12014,
2967 .enable_reg = 0x4500c,
2982 .halt_reg = 0x1203c,
2984 .enable_reg = 0x4500c,
2999 .halt_reg = 0x4102c,
3001 .enable_reg = 0x4102c,
3002 .enable_mask = BIT(0),
3016 .halt_reg = 0x41008,
3018 .enable_reg = 0x41008,
3019 .enable_mask = BIT(0),
3033 .halt_reg = 0x41004,
3035 .enable_reg = 0x41004,
3036 .enable_mask = BIT(0),
3050 .halt_reg = 0x4c020,
3052 .enable_reg = 0x4c020,
3053 .enable_mask = BIT(0),
3067 .halt_reg = 0x4c024,
3069 .enable_reg = 0x4c024,
3070 .enable_mask = BIT(0),
3084 .halt_reg = 0x4c01c,
3086 .enable_reg = 0x4c01c,
3087 .enable_mask = BIT(0),
3101 .gdscr = 0x4c018,
3109 .gdscr = 0x4d078,
3117 .gdscr = 0x5701c,
3125 .gdscr = 0x58034,
3133 .gdscr = 0x5901c,
3313 [GCC_BLSP1_BCR] = { 0x01000 },
3314 [GCC_BLSP1_QUP1_BCR] = { 0x02000 },
3315 [GCC_BLSP1_UART1_BCR] = { 0x02038 },
3316 [GCC_BLSP1_QUP2_BCR] = { 0x03008 },
3317 [GCC_BLSP1_UART2_BCR] = { 0x03028 },
3318 [GCC_BLSP1_QUP3_BCR] = { 0x04018 },
3319 [GCC_BLSP1_QUP4_BCR] = { 0x05018 },
3320 [GCC_BLSP1_QUP5_BCR] = { 0x06018 },
3321 [GCC_BLSP1_QUP6_BCR] = { 0x07018 },
3322 [GCC_IMEM_BCR] = { 0x0e000 },
3323 [GCC_SMMU_BCR] = { 0x12000 },
3324 [GCC_APSS_TCU_BCR] = { 0x12050 },
3325 [GCC_SMMU_XPU_BCR] = { 0x12054 },
3326 [GCC_PCNOC_TBU_BCR] = { 0x12058 },
3327 [GCC_PRNG_BCR] = { 0x13000 },
3328 [GCC_BOOT_ROM_BCR] = { 0x13008 },
3329 [GCC_CRYPTO_BCR] = { 0x16000 },
3330 [GCC_SEC_CTRL_BCR] = { 0x1a000 },
3331 [GCC_AUDIO_CORE_BCR] = { 0x1c008 },
3332 [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 },
3333 [GCC_DEHR_BCR] = { 0x1f000 },
3334 [GCC_SYSTEM_NOC_BCR] = { 0x26000 },
3335 [GCC_PCNOC_BCR] = { 0x27018 },
3336 [GCC_TCSR_BCR] = { 0x28000 },
3337 [GCC_QDSS_BCR] = { 0x29000 },
3338 [GCC_DCD_BCR] = { 0x2a000 },
3339 [GCC_MSG_RAM_BCR] = { 0x2b000 },
3340 [GCC_MPM_BCR] = { 0x2c000 },
3341 [GCC_SPMI_BCR] = { 0x2e000 },
3342 [GCC_SPDM_BCR] = { 0x2f000 },
3343 [GCC_MM_SPDM_BCR] = { 0x2f024 },
3344 [GCC_BIMC_BCR] = { 0x31000 },
3345 [GCC_RBCPR_BCR] = { 0x33000 },
3346 [GCC_TLMM_BCR] = { 0x34000 },
3347 [GCC_USB_HS_BCR] = { 0x41000 },
3348 [GCC_USB2A_PHY_BCR] = { 0x41028 },
3349 [GCC_SDCC1_BCR] = { 0x42000 },
3350 [GCC_SDCC2_BCR] = { 0x43000 },
3351 [GCC_PDM_BCR] = { 0x44000 },
3352 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000 },
3353 [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000 },
3354 [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008 },
3355 [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010 },
3356 [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018 },
3357 [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020 },
3358 [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028 },
3359 [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030 },
3360 [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038 },
3361 [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040 },
3362 [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048 },
3363 [GCC_MMSS_BCR] = { 0x4b000 },
3364 [GCC_VENUS0_BCR] = { 0x4c014 },
3365 [GCC_MDSS_BCR] = { 0x4d074 },
3366 [GCC_CAMSS_PHY0_BCR] = { 0x4e018 },
3367 [GCC_CAMSS_CSI0_BCR] = { 0x4e038 },
3368 [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 },
3369 [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c },
3370 [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 },
3371 [GCC_CAMSS_PHY1_BCR] = { 0x4f018 },
3372 [GCC_CAMSS_CSI1_BCR] = { 0x4f038 },
3373 [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 },
3374 [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c },
3375 [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 },
3376 [GCC_CAMSS_ISPIF_BCR] = { 0x50000 },
3377 [GCC_CAMSS_CCI_BCR] = { 0x51014 },
3378 [GCC_CAMSS_MCLK0_BCR] = { 0x52014 },
3379 [GCC_CAMSS_MCLK1_BCR] = { 0x53014 },
3380 [GCC_CAMSS_GP0_BCR] = { 0x54014 },
3381 [GCC_CAMSS_GP1_BCR] = { 0x55014 },
3382 [GCC_CAMSS_TOP_BCR] = { 0x56000 },
3383 [GCC_CAMSS_MICRO_BCR] = { 0x56008 },
3384 [GCC_CAMSS_JPEG_BCR] = { 0x57018 },
3385 [GCC_CAMSS_VFE_BCR] = { 0x58030 },
3386 [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c },
3387 [GCC_OXILI_BCR] = { 0x59018 },
3388 [GCC_GMEM_BCR] = { 0x5902c },
3389 [GCC_CAMSS_AHB_BCR] = { 0x5a018 },
3390 [GCC_MDP_TBU_BCR] = { 0x62000 },
3391 [GCC_GFX_TBU_BCR] = { 0x63000 },
3392 [GCC_GFX_TCU_BCR] = { 0x64000 },
3393 [GCC_MSS_TBU_AXI_BCR] = { 0x65000 },
3394 [GCC_MSS_TBU_GSS_AXI_BCR] = { 0x66000 },
3395 [GCC_MSS_TBU_Q6_AXI_BCR] = { 0x67000 },
3396 [GCC_GTCU_AHB_BCR] = { 0x68000 },
3397 [GCC_SMMU_CFG_BCR] = { 0x69000 },
3398 [GCC_VFE_TBU_BCR] = { 0x6a000 },
3399 [GCC_VENUS_TBU_BCR] = { 0x6b000 },
3400 [GCC_JPEG_TBU_BCR] = { 0x6c000 },
3401 [GCC_PRONTO_TBU_BCR] = { 0x6d000 },
3402 [GCC_SMMU_CATS_BCR] = { 0x7c000 },
3409 .max_register = 0x80000,