Lines Matching +full:0 +full:x4c000
49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
164 { P_XO, 0 },
174 { P_XO, 0 },
184 { P_XO, 0 },
196 { P_XO, 0 },
208 { P_XO, 0 },
220 { P_XO, 0 },
234 { P_XO, 0 },
248 F(19200000, P_XO, 1, 0, 0),
249 F(120000000, P_GPLL0, 5, 0, 0),
250 F(150000000, P_GPLL0, 4, 0, 0),
255 .cmd_rcgr = 0x0f014,
269 F(19200000, P_XO, 1, 0, 0),
274 .cmd_rcgr = 0x0f028,
287 F(1200000, P_XO, 16, 0, 0),
292 .cmd_rcgr = 0x5000c,
305 F(120000000, P_GPLL0, 5, 0, 0),
310 .cmd_rcgr = 0x12010,
324 .cmd_rcgr = 0x12024,
341 F(50000000, P_GPLL0, 12, 0, 0),
342 F(96000000, P_GPLL4, 4, 0, 0),
343 F(192000000, P_GPLL4, 2, 0, 0),
344 F(384000000, P_GPLL4, 1, 0, 0),
349 .cmd_rcgr = 0x13010,
363 F(19200000, P_XO, 1, 0, 0),
364 F(150000000, P_GPLL0, 4, 0, 0),
365 F(300000000, P_GPLL0, 2, 0, 0),
370 .cmd_rcgr = 0x13024,
387 F(50000000, P_GPLL0, 12, 0, 0),
388 F(100000000, P_GPLL0, 6, 0, 0),
389 F(200000000, P_GPLL0, 3, 0, 0),
394 .cmd_rcgr = 0x14010,
408 .cmd_rcgr = 0x15010,
426 F(50000000, P_GPLL0, 12, 0, 0),
427 F(100000000, P_GPLL0, 6, 0, 0),
432 .cmd_rcgr = 0x16010,
447 F(4800000, P_XO, 4, 0, 0),
448 F(9600000, P_XO, 2, 0, 0),
450 F(19200000, P_XO, 1, 0, 0),
452 F(50000000, P_GPLL0, 12, 0, 0),
457 .cmd_rcgr = 0x1900c,
471 F(19200000, P_XO, 1, 0, 0),
472 F(50000000, P_GPLL0, 12, 0, 0),
477 .cmd_rcgr = 0x19020,
494 F(19200000, P_XO, 1, 0, 0),
497 F(40000000, P_GPLL0, 15, 0, 0),
499 F(48000000, P_GPLL0, 12.5, 0, 0),
503 F(60000000, P_GPLL0, 10, 0, 0),
504 F(63157895, P_GPLL0, 9.5, 0, 0),
509 .cmd_rcgr = 0x1a00c,
523 .cmd_rcgr = 0x1b00c,
537 .cmd_rcgr = 0x1b020,
550 .cmd_rcgr = 0x1c00c,
564 .cmd_rcgr = 0x1d00c,
578 .cmd_rcgr = 0x1d020,
591 .cmd_rcgr = 0x1e00c,
605 .cmd_rcgr = 0x1f00c,
619 .cmd_rcgr = 0x1f020,
632 .cmd_rcgr = 0x2000c,
646 .cmd_rcgr = 0x2100c,
660 .cmd_rcgr = 0x21020,
673 .cmd_rcgr = 0x2200c,
687 .cmd_rcgr = 0x2300c,
701 .cmd_rcgr = 0x23020,
714 .cmd_rcgr = 0x2400c,
728 .cmd_rcgr = 0x2600c,
742 .cmd_rcgr = 0x26020,
755 .cmd_rcgr = 0x2700c,
769 .cmd_rcgr = 0x2800c,
783 .cmd_rcgr = 0x28020,
796 .cmd_rcgr = 0x2900c,
810 .cmd_rcgr = 0x2a00c,
824 .cmd_rcgr = 0x2a020,
837 .cmd_rcgr = 0x2b00c,
851 .cmd_rcgr = 0x2c00c,
865 .cmd_rcgr = 0x2c020,
878 .cmd_rcgr = 0x2d00c,
892 .cmd_rcgr = 0x2e00c,
906 .cmd_rcgr = 0x2e020,
919 .cmd_rcgr = 0x2f00c,
933 .cmd_rcgr = 0x3000c,
947 .cmd_rcgr = 0x30020,
960 .cmd_rcgr = 0x3100c,
974 F(60000000, P_GPLL0, 10, 0, 0),
979 .cmd_rcgr = 0x33010,
997 .cmd_rcgr = 0x36010,
1011 .cmd_rcgr = 0x43014,
1023 .cmd_rcgr = 0x48040,
1036 .cmd_rcgr = 0x48058,
1048 F(19200000, P_XO, 1, 0, 0),
1049 F(100000000, P_GPLL0, 6, 0, 0),
1050 F(200000000, P_GPLL0, 3, 0, 0),
1055 .cmd_rcgr = 0x64004,
1069 .cmd_rcgr = 0x65004,
1083 .cmd_rcgr = 0x66004,
1102 .cmd_rcgr = 0x6c000,
1116 F(100000000, P_GPLL0, 6, 0, 0),
1117 F(200000000, P_GPLL0, 3, 0, 0),
1118 F(240000000, P_GPLL0, 2.5, 0, 0),
1123 .cmd_rcgr = 0x75024,
1137 F(19200000, P_XO, 1, 0, 0),
1138 F(150000000, P_GPLL0, 4, 0, 0),
1139 F(300000000, P_GPLL0, 2, 0, 0),
1144 .cmd_rcgr = 0x76014,
1157 F(75000000, P_GPLL0, 8, 0, 0),
1158 F(150000000, P_GPLL0, 4, 0, 0),
1159 F(256000000, P_GPLL4, 1.5, 0, 0),
1160 F(300000000, P_GPLL0, 2, 0, 0),
1165 .cmd_rcgr = 0x8b00c,
1178 .halt_reg = 0x0f03c,
1180 .enable_reg = 0x0f03c,
1181 .enable_mask = BIT(0),
1195 .halt_reg = 0x75038,
1197 .enable_reg = 0x75038,
1198 .enable_mask = BIT(0),
1212 .halt_reg = 0x6010,
1214 .enable_reg = 0x6010,
1215 .enable_mask = BIT(0),
1229 .halt_reg = 0x9008,
1231 .enable_reg = 0x9008,
1232 .enable_mask = BIT(0),
1242 .halt_reg = 0x9010,
1244 .enable_reg = 0x9010,
1245 .enable_mask = BIT(0),
1255 .halt_reg = 0x0f008,
1257 .enable_reg = 0x0f008,
1258 .enable_mask = BIT(0),
1272 .halt_reg = 0x0f00c,
1274 .enable_reg = 0x0f00c,
1275 .enable_mask = BIT(0),
1289 .halt_reg = 0x0f010,
1291 .enable_reg = 0x0f010,
1292 .enable_mask = BIT(0),
1306 .halt_reg = 0x50000,
1308 .enable_reg = 0x50000,
1309 .enable_mask = BIT(0),
1323 .halt_reg = 0x50004,
1326 .enable_reg = 0x50004,
1327 .enable_mask = BIT(0),
1341 .halt_reg = 0x12004,
1343 .enable_reg = 0x12004,
1344 .enable_mask = BIT(0),
1358 .halt_reg = 0x12008,
1360 .enable_reg = 0x12008,
1361 .enable_mask = BIT(0),
1375 .halt_reg = 0x1200c,
1377 .enable_reg = 0x1200c,
1378 .enable_mask = BIT(0),
1392 .halt_reg = 0x6a004,
1394 .enable_reg = 0x6a004,
1395 .enable_mask = BIT(0),
1404 .halt_reg = 0x13004,
1406 .enable_reg = 0x13004,
1407 .enable_mask = BIT(0),
1421 .halt_reg = 0x13008,
1423 .enable_reg = 0x13008,
1424 .enable_mask = BIT(0),
1433 .halt_reg = 0x13038,
1435 .enable_reg = 0x13038,
1436 .enable_mask = BIT(0),
1450 .halt_reg = 0x14004,
1452 .enable_reg = 0x14004,
1453 .enable_mask = BIT(0),
1467 .halt_reg = 0x14008,
1469 .enable_reg = 0x14008,
1470 .enable_mask = BIT(0),
1479 .halt_reg = 0x15004,
1481 .enable_reg = 0x15004,
1482 .enable_mask = BIT(0),
1496 .halt_reg = 0x15008,
1498 .enable_reg = 0x15008,
1499 .enable_mask = BIT(0),
1508 .halt_reg = 0x16004,
1510 .enable_reg = 0x16004,
1511 .enable_mask = BIT(0),
1525 .halt_reg = 0x16008,
1527 .enable_reg = 0x16008,
1528 .enable_mask = BIT(0),
1537 .halt_reg = 0x17004,
1540 .enable_reg = 0x52004,
1550 .halt_reg = 0x17008,
1553 .enable_reg = 0x52004,
1568 .halt_reg = 0x19004,
1570 .enable_reg = 0x19004,
1571 .enable_mask = BIT(0),
1585 .halt_reg = 0x19008,
1587 .enable_reg = 0x19008,
1588 .enable_mask = BIT(0),
1602 .halt_reg = 0x1a004,
1604 .enable_reg = 0x1a004,
1605 .enable_mask = BIT(0),
1619 .halt_reg = 0x1b004,
1621 .enable_reg = 0x1b004,
1622 .enable_mask = BIT(0),
1636 .halt_reg = 0x1b008,
1638 .enable_reg = 0x1b008,
1639 .enable_mask = BIT(0),
1653 .halt_reg = 0x1c004,
1655 .enable_reg = 0x1c004,
1656 .enable_mask = BIT(0),
1670 .halt_reg = 0x1d004,
1672 .enable_reg = 0x1d004,
1673 .enable_mask = BIT(0),
1687 .halt_reg = 0x1d008,
1689 .enable_reg = 0x1d008,
1690 .enable_mask = BIT(0),
1704 .halt_reg = 0x1e004,
1706 .enable_reg = 0x1e004,
1707 .enable_mask = BIT(0),
1721 .halt_reg = 0x1f004,
1723 .enable_reg = 0x1f004,
1724 .enable_mask = BIT(0),
1738 .halt_reg = 0x1f008,
1740 .enable_reg = 0x1f008,
1741 .enable_mask = BIT(0),
1755 .halt_reg = 0x20004,
1757 .enable_reg = 0x20004,
1758 .enable_mask = BIT(0),
1772 .halt_reg = 0x21004,
1774 .enable_reg = 0x21004,
1775 .enable_mask = BIT(0),
1789 .halt_reg = 0x21008,
1791 .enable_reg = 0x21008,
1792 .enable_mask = BIT(0),
1806 .halt_reg = 0x22004,
1808 .enable_reg = 0x22004,
1809 .enable_mask = BIT(0),
1823 .halt_reg = 0x23004,
1825 .enable_reg = 0x23004,
1826 .enable_mask = BIT(0),
1840 .halt_reg = 0x23008,
1842 .enable_reg = 0x23008,
1843 .enable_mask = BIT(0),
1857 .halt_reg = 0x24004,
1859 .enable_reg = 0x24004,
1860 .enable_mask = BIT(0),
1874 .halt_reg = 0x25004,
1877 .enable_reg = 0x52004,
1887 .halt_reg = 0x25008,
1890 .enable_reg = 0x52004,
1905 .halt_reg = 0x26004,
1907 .enable_reg = 0x26004,
1908 .enable_mask = BIT(0),
1922 .halt_reg = 0x26008,
1924 .enable_reg = 0x26008,
1925 .enable_mask = BIT(0),
1939 .halt_reg = 0x27004,
1941 .enable_reg = 0x27004,
1942 .enable_mask = BIT(0),
1956 .halt_reg = 0x28004,
1958 .enable_reg = 0x28004,
1959 .enable_mask = BIT(0),
1973 .halt_reg = 0x28008,
1975 .enable_reg = 0x28008,
1976 .enable_mask = BIT(0),
1990 .halt_reg = 0x29004,
1992 .enable_reg = 0x29004,
1993 .enable_mask = BIT(0),
2007 .halt_reg = 0x2a004,
2009 .enable_reg = 0x2a004,
2010 .enable_mask = BIT(0),
2024 .halt_reg = 0x2a008,
2026 .enable_reg = 0x2a008,
2027 .enable_mask = BIT(0),
2041 .halt_reg = 0x2b004,
2043 .enable_reg = 0x2b004,
2044 .enable_mask = BIT(0),
2058 .halt_reg = 0x2c004,
2060 .enable_reg = 0x2c004,
2061 .enable_mask = BIT(0),
2075 .halt_reg = 0x2c008,
2077 .enable_reg = 0x2c008,
2078 .enable_mask = BIT(0),
2092 .halt_reg = 0x2d004,
2094 .enable_reg = 0x2d004,
2095 .enable_mask = BIT(0),
2109 .halt_reg = 0x2e004,
2111 .enable_reg = 0x2e004,
2112 .enable_mask = BIT(0),
2126 .halt_reg = 0x2e008,
2128 .enable_reg = 0x2e008,
2129 .enable_mask = BIT(0),
2143 .halt_reg = 0x2f004,
2145 .enable_reg = 0x2f004,
2146 .enable_mask = BIT(0),
2160 .halt_reg = 0x30004,
2162 .enable_reg = 0x30004,
2163 .enable_mask = BIT(0),
2177 .halt_reg = 0x30008,
2179 .enable_reg = 0x30008,
2180 .enable_mask = BIT(0),
2194 .halt_reg = 0x31004,
2196 .enable_reg = 0x31004,
2197 .enable_mask = BIT(0),
2211 .halt_reg = 0x33004,
2213 .enable_reg = 0x33004,
2214 .enable_mask = BIT(0),
2223 .halt_reg = 0x3300c,
2225 .enable_reg = 0x3300c,
2226 .enable_mask = BIT(0),
2240 .halt_reg = 0x34004,
2243 .enable_reg = 0x52004,
2253 .halt_reg = 0x36004,
2255 .enable_reg = 0x36004,
2256 .enable_mask = BIT(0),
2265 .halt_reg = 0x36008,
2267 .enable_reg = 0x36008,
2268 .enable_mask = BIT(0),
2282 .halt_reg = 0x3600c,
2284 .enable_reg = 0x3600c,
2285 .enable_mask = BIT(0),
2299 .halt_reg = 0x38004,
2302 .enable_reg = 0x52004,
2312 .halt_reg = 0x46018,
2314 .enable_reg = 0x46018,
2315 .enable_mask = BIT(0),
2325 .halt_reg = 0x4800c,
2327 .enable_reg = 0x4800c,
2328 .enable_mask = BIT(0),
2342 .halt_reg = 0x64000,
2344 .enable_reg = 0x64000,
2345 .enable_mask = BIT(0),
2359 .halt_reg = 0x65000,
2361 .enable_reg = 0x65000,
2362 .enable_mask = BIT(0),
2376 .halt_reg = 0x66000,
2378 .enable_reg = 0x66000,
2379 .enable_mask = BIT(0),
2393 .halt_reg = 0x6b008,
2395 .enable_reg = 0x6b008,
2396 .enable_mask = BIT(0),
2405 .halt_reg = 0x6b00c,
2407 .enable_reg = 0x6b00c,
2408 .enable_mask = BIT(0),
2417 .halt_reg = 0x6b010,
2419 .enable_reg = 0x6b010,
2420 .enable_mask = BIT(0),
2429 .halt_reg = 0x6b014,
2431 .enable_reg = 0x6b014,
2432 .enable_mask = BIT(0),
2446 .halt_reg = 0x6b018,
2449 .enable_reg = 0x6b018,
2450 .enable_mask = BIT(0),
2464 .halt_reg = 0x6d008,
2466 .enable_reg = 0x6d008,
2467 .enable_mask = BIT(0),
2476 .halt_reg = 0x6d00c,
2478 .enable_reg = 0x6d00c,
2479 .enable_mask = BIT(0),
2488 .halt_reg = 0x6d010,
2490 .enable_reg = 0x6d010,
2491 .enable_mask = BIT(0),
2500 .halt_reg = 0x6d014,
2502 .enable_reg = 0x6d014,
2503 .enable_mask = BIT(0),
2517 .halt_reg = 0x6d018,
2520 .enable_reg = 0x6d018,
2521 .enable_mask = BIT(0),
2535 .halt_reg = 0x6e008,
2537 .enable_reg = 0x6e008,
2538 .enable_mask = BIT(0),
2547 .halt_reg = 0x6e00c,
2549 .enable_reg = 0x6e00c,
2550 .enable_mask = BIT(0),
2559 .halt_reg = 0x6e010,
2561 .enable_reg = 0x6e010,
2562 .enable_mask = BIT(0),
2571 .halt_reg = 0x6e014,
2573 .enable_reg = 0x6e014,
2574 .enable_mask = BIT(0),
2588 .halt_reg = 0x6e018,
2591 .enable_reg = 0x6e018,
2592 .enable_mask = BIT(0),
2606 .halt_reg = 0x6f004,
2608 .enable_reg = 0x6f004,
2609 .enable_mask = BIT(0),
2618 .halt_reg = 0x6f008,
2620 .enable_reg = 0x6f008,
2621 .enable_mask = BIT(0),
2635 .halt_reg = 0x75008,
2637 .enable_reg = 0x75008,
2638 .enable_mask = BIT(0),
2652 .halt_reg = 0x7500c,
2654 .enable_reg = 0x7500c,
2655 .enable_mask = BIT(0),
2678 .halt_reg = 0x75010,
2680 .enable_reg = 0x75010,
2681 .enable_mask = BIT(0),
2709 .halt_reg = 0x7d010,
2712 .enable_reg = 0x7d010,
2713 .enable_mask = BIT(0),
2722 .halt_reg = 0x7d014,
2725 .enable_reg = 0x7d014,
2726 .enable_mask = BIT(0),
2735 .halt_reg = 0x75014,
2737 .enable_reg = 0x75014,
2738 .enable_mask = BIT(0),
2752 .halt_reg = 0x75018,
2755 .enable_reg = 0x75018,
2756 .enable_mask = BIT(0),
2770 .halt_reg = 0x7501c,
2773 .enable_reg = 0x7501c,
2774 .enable_mask = BIT(0),
2788 .halt_reg = 0x75020,
2791 .enable_reg = 0x75020,
2792 .enable_mask = BIT(0),
2820 .halt_reg = 0x7600c,
2822 .enable_reg = 0x7600c,
2823 .enable_mask = BIT(0),
2837 .halt_reg = 0x76010,
2839 .enable_reg = 0x76010,
2840 .enable_mask = BIT(0),
2856 .enable_reg = 0x76030,
2857 .enable_mask = BIT(0),
2868 .enable_reg = 0x76034,
2869 .enable_mask = BIT(0),
2878 .halt_reg = 0x81008,
2880 .enable_reg = 0x81008,
2881 .enable_mask = BIT(0),
2891 .halt_reg = 0x8100c,
2893 .enable_reg = 0x8100c,
2894 .enable_mask = BIT(0),
2904 .halt_reg = 0x81014,
2906 .enable_reg = 0x81014,
2907 .enable_mask = BIT(0),
2917 .halt_reg = 0x81018,
2919 .enable_reg = 0x81018,
2920 .enable_mask = BIT(0),
2930 .halt_reg = 0x83014,
2932 .enable_reg = 0x83014,
2933 .enable_mask = BIT(0),
2947 .halt_reg = 0x83018,
2949 .enable_reg = 0x83018,
2950 .enable_mask = BIT(0),
2964 .halt_reg = 0x84004,
2966 .enable_reg = 0x84004,
2967 .enable_mask = BIT(0),
2976 .halt_reg = 0x85000,
2978 .enable_reg = 0x85000,
2979 .enable_mask = BIT(0),
2988 .halt_reg = 0x8b004,
2990 .enable_reg = 0x8b004,
2991 .enable_mask = BIT(0),
3000 .halt_reg = 0x8b008,
3002 .enable_reg = 0x8b008,
3003 .enable_mask = BIT(0),
3017 .halt_reg = 0x8800C,
3019 .enable_reg = 0x8800C,
3020 .enable_mask = BIT(0),
3034 .halt_reg = 0x88000,
3036 .enable_reg = 0x88000,
3037 .enable_mask = BIT(0),
3051 .halt_reg = 0x88004,
3053 .enable_reg = 0x88004,
3054 .enable_mask = BIT(0),
3068 .halt_reg = 0x88008,
3070 .enable_reg = 0x88008,
3071 .enable_mask = BIT(0),
3085 .halt_reg = 0x88010,
3087 .enable_reg = 0x88010,
3088 .enable_mask = BIT(0),
3102 .halt_reg = 0x88014,
3104 .enable_reg = 0x88014,
3105 .enable_mask = BIT(0),
3119 .halt_reg = 0x88018,
3121 .enable_reg = 0x88018,
3122 .enable_mask = BIT(0),
3136 .halt_reg = 0x8a000,
3138 .enable_reg = 0x8a000,
3139 .enable_mask = BIT(0),
3148 .halt_reg = 0x8a004,
3150 .enable_reg = 0x8a004,
3151 .enable_mask = BIT(0),
3160 .halt_reg = 0x8a024,
3162 .enable_reg = 0x8a024,
3163 .enable_mask = BIT(0),
3172 .halt_reg = 0x8a028,
3174 .enable_reg = 0x8a028,
3175 .enable_mask = BIT(0),
3192 .gdscr = 0x81004,
3193 .gds_hw_ctrl = 0x81028,
3202 .gdscr = 0x7d024,
3211 .gdscr = 0x7d034,
3220 .gdscr = 0x7d038,
3229 .gdscr = 0xf004,
3238 .gdscr = 0x6b004,
3246 .gdscr = 0x6d004,
3254 .gdscr = 0x6e004,
3262 .gdscr = 0x75004,
3475 [GCC_SYSTEM_NOC_BCR] = { 0x4000 },
3476 [GCC_CONFIG_NOC_BCR] = { 0x5000 },
3477 [GCC_PERIPH_NOC_BCR] = { 0x6000 },
3478 [GCC_IMEM_BCR] = { 0x8000 },
3479 [GCC_MMSS_BCR] = { 0x9000 },
3480 [GCC_PIMEM_BCR] = { 0x0a000 },
3481 [GCC_QDSS_BCR] = { 0x0c000 },
3482 [GCC_USB_30_BCR] = { 0x0f000 },
3483 [GCC_USB_20_BCR] = { 0x12000 },
3484 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12038 },
3485 [GCC_QUSB2PHY_SEC_BCR] = { 0x1203c },
3486 [GCC_USB3_PHY_BCR] = { 0x50020 },
3487 [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
3488 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3489 [GCC_SDCC1_BCR] = { 0x13000 },
3490 [GCC_SDCC2_BCR] = { 0x14000 },
3491 [GCC_SDCC3_BCR] = { 0x15000 },
3492 [GCC_SDCC4_BCR] = { 0x16000 },
3493 [GCC_BLSP1_BCR] = { 0x17000 },
3494 [GCC_BLSP1_QUP1_BCR] = { 0x19000 },
3495 [GCC_BLSP1_UART1_BCR] = { 0x1a000 },
3496 [GCC_BLSP1_QUP2_BCR] = { 0x1b000 },
3497 [GCC_BLSP1_UART2_BCR] = { 0x1c000 },
3498 [GCC_BLSP1_QUP3_BCR] = { 0x1d000 },
3499 [GCC_BLSP1_UART3_BCR] = { 0x1e000 },
3500 [GCC_BLSP1_QUP4_BCR] = { 0x1f000 },
3501 [GCC_BLSP1_UART4_BCR] = { 0x20000 },
3502 [GCC_BLSP1_QUP5_BCR] = { 0x21000 },
3503 [GCC_BLSP1_UART5_BCR] = { 0x22000 },
3504 [GCC_BLSP1_QUP6_BCR] = { 0x23000 },
3505 [GCC_BLSP1_UART6_BCR] = { 0x24000 },
3506 [GCC_BLSP2_BCR] = { 0x25000 },
3507 [GCC_BLSP2_QUP1_BCR] = { 0x26000 },
3508 [GCC_BLSP2_UART1_BCR] = { 0x27000 },
3509 [GCC_BLSP2_QUP2_BCR] = { 0x28000 },
3510 [GCC_BLSP2_UART2_BCR] = { 0x29000 },
3511 [GCC_BLSP2_QUP3_BCR] = { 0x2a000 },
3512 [GCC_BLSP2_UART3_BCR] = { 0x2b000 },
3513 [GCC_BLSP2_QUP4_BCR] = { 0x2c000 },
3514 [GCC_BLSP2_UART4_BCR] = { 0x2d000 },
3515 [GCC_BLSP2_QUP5_BCR] = { 0x2e000 },
3516 [GCC_BLSP2_UART5_BCR] = { 0x2f000 },
3517 [GCC_BLSP2_QUP6_BCR] = { 0x30000 },
3518 [GCC_BLSP2_UART6_BCR] = { 0x31000 },
3519 [GCC_PDM_BCR] = { 0x33000 },
3520 [GCC_PRNG_BCR] = { 0x34000 },
3521 [GCC_TSIF_BCR] = { 0x36000 },
3522 [GCC_TCSR_BCR] = { 0x37000 },
3523 [GCC_BOOT_ROM_BCR] = { 0x38000 },
3524 [GCC_MSG_RAM_BCR] = { 0x39000 },
3525 [GCC_TLMM_BCR] = { 0x3a000 },
3526 [GCC_MPM_BCR] = { 0x3b000 },
3527 [GCC_SEC_CTRL_BCR] = { 0x3d000 },
3528 [GCC_SPMI_BCR] = { 0x3f000 },
3529 [GCC_SPDM_BCR] = { 0x40000 },
3530 [GCC_CE1_BCR] = { 0x41000 },
3531 [GCC_BIMC_BCR] = { 0x44000 },
3532 [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x49000 },
3533 [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x49008 },
3534 [GCC_SNOC_BUS_TIMEOUT1_BCR] = { 0x49010 },
3535 [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x49018 },
3536 [GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x49020 },
3537 [GCC_PNOC_BUS_TIMEOUT0_BCR] = { 0x4a000 },
3538 [GCC_PNOC_BUS_TIMEOUT1_BCR] = { 0x4a008 },
3539 [GCC_PNOC_BUS_TIMEOUT2_BCR] = { 0x4a010 },
3540 [GCC_PNOC_BUS_TIMEOUT3_BCR] = { 0x4a018 },
3541 [GCC_PNOC_BUS_TIMEOUT4_BCR] = { 0x4a020 },
3542 [GCC_CNOC_BUS_TIMEOUT0_BCR] = { 0x4b000 },
3543 [GCC_CNOC_BUS_TIMEOUT1_BCR] = { 0x4b008 },
3544 [GCC_CNOC_BUS_TIMEOUT2_BCR] = { 0x4b010 },
3545 [GCC_CNOC_BUS_TIMEOUT3_BCR] = { 0x4b018 },
3546 [GCC_CNOC_BUS_TIMEOUT4_BCR] = { 0x4b020 },
3547 [GCC_CNOC_BUS_TIMEOUT5_BCR] = { 0x4b028 },
3548 [GCC_CNOC_BUS_TIMEOUT6_BCR] = { 0x4b030 },
3549 [GCC_CNOC_BUS_TIMEOUT7_BCR] = { 0x4b038 },
3550 [GCC_CNOC_BUS_TIMEOUT8_BCR] = { 0x80000 },
3551 [GCC_CNOC_BUS_TIMEOUT9_BCR] = { 0x80008 },
3552 [GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR] = { 0x80010 },
3553 [GCC_APB2JTAG_BCR] = { 0x4c000 },
3554 [GCC_RBCPR_CX_BCR] = { 0x4e000 },
3555 [GCC_RBCPR_MX_BCR] = { 0x4f000 },
3556 [GCC_PCIE_0_BCR] = { 0x6b000 },
3557 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3558 [GCC_PCIE_1_BCR] = { 0x6d000 },
3559 [GCC_PCIE_1_PHY_BCR] = { 0x6d038 },
3560 [GCC_PCIE_2_BCR] = { 0x6e000 },
3561 [GCC_PCIE_2_PHY_BCR] = { 0x6e038 },
3562 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3563 [GCC_PCIE_PHY_COM_BCR] = { 0x6f014 },
3564 [GCC_PCIE_PHY_COM_NOCSR_BCR] = { 0x6f00c },
3565 [GCC_DCD_BCR] = { 0x70000 },
3566 [GCC_OBT_ODT_BCR] = { 0x73000 },
3567 [GCC_UFS_BCR] = { 0x75000 },
3568 [GCC_SSC_BCR] = { 0x63000 },
3569 [GCC_VS_BCR] = { 0x7a000 },
3570 [GCC_AGGRE0_NOC_BCR] = { 0x81000 },
3571 [GCC_AGGRE1_NOC_BCR] = { 0x82000 },
3572 [GCC_AGGRE2_NOC_BCR] = { 0x83000 },
3573 [GCC_DCC_BCR] = { 0x84000 },
3574 [GCC_IPA_BCR] = { 0x89000 },
3575 [GCC_QSPI_BCR] = { 0x8b000 },
3576 [GCC_SKL_BCR] = { 0x8c000 },
3577 [GCC_MSMPU_BCR] = { 0x8d000 },
3578 [GCC_MSS_Q6_BCR] = { 0x8e000 },
3579 [GCC_QREFS_VBG_CAL_BCR] = { 0x88020 },
3580 [GCC_MSS_RESTART] = { 0x8f008 },
3587 .max_register = 0x8f010,
3621 regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21)); in gcc_msm8996_probe()