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/linux/include/linux/mfd/wm8350/
H A Dpmic.h19 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
20 #define WM8350_CSA_FLASH_CONTROL 0xAD
21 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
22 #define WM8350_CSB_FLASH_CONTROL 0xAF
23 #define WM8350_DCDC_LDO_REQUESTED 0xB0
24 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
25 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
26 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
27 #define WM8350_DCDC1_CONTROL 0xB4
28 #define WM8350_DCDC1_TIMEOUTS 0xB5
[all …]
/linux/Documentation/devicetree/bindings/soc/loongson/
H A Dloongson,ls2k-pmc.yaml65 reg = <0x1fe27000 0x58>;
68 loongson,suspend-address = <0x0 0x1c000500>;
72 offset = <0x30>;
73 mask = <0x1>;
79 offset = <0x14>;
80 mask = <0x3c00>;
81 value = <0x3c00>;
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/linux/sound/soc/sof/amd/
H A Dacp-dsp-offset.h15 #define ACP_DMA_CNTL_0 0x00
16 #define ACP_DMA_DSCR_STRT_IDX_0 0x20
17 #define ACP_DMA_DSCR_CNT_0 0x40
18 #define ACP_DMA_PRIO_0 0x60
19 #define ACP_DMA_CUR_DSCR_0 0x80
20 #define ACP_DMA_ERR_STS_0 0xC0
21 #define ACP_DMA_DESC_BASE_ADDR 0xE0
22 #define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4
23 #define ACP_DMA_CH_STS 0xE8
24 #define ACP_DMA_CH_GROUP 0xEC
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/linux/sound/soc/codecs/
H A Drt700.h30 #define RT700_AUDIO_FUNCTION_GROUP 0x01
31 #define RT700_DAC_OUT1 0x02
32 #define RT700_DAC_OUT2 0x03
33 #define RT700_ADC_IN1 0x09
34 #define RT700_ADC_IN2 0x08
35 #define RT700_DMIC1 0x12
36 #define RT700_DMIC2 0x13
37 #define RT700_SPK_OUT 0x14
38 #define RT700_MIC2 0x19
39 #define RT700_LINE1 0x1a
[all …]
H A Drt711.h32 #define RT711_AUDIO_FUNCTION_GROUP 0x01
33 #define RT711_DAC_OUT2 0x03
34 #define RT711_ADC_IN1 0x09
35 #define RT711_ADC_IN2 0x08
36 #define RT711_DMIC1 0x12
37 #define RT711_DMIC2 0x13
38 #define RT711_MIC2 0x19
39 #define RT711_LINE1 0x1a
40 #define RT711_LINE2 0x1b
41 #define RT711_BEEP 0x1d
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/linux/arch/sh/boards/
H A Dboard-magicpanelr2.c33 #define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
43 for (i = 0; i < 10; ++i) { in ethernet_reset_finished()
49 return 0; in ethernet_reset_finished()
55 CLRBITS_OUTB(0x10, PORT_PMDR); in reset_ethernet()
60 SETBITS_OUTB(0x10, PORT_PMDR); in reset_ethernet()
65 /* CS2: LAN (0x08000000 - 0x0bffffff) */ in setup_chip_select()
67 __raw_writel(0x36db0400, CS2BCR); in setup_chip_select()
69 __raw_writel(0x000003c0, CS2WCR); in setup_chip_select()
71 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ in setup_chip_select()
73 __raw_writel(0x00000200, CS4BCR); in setup_chip_select()
[all …]
/linux/lib/crc/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k2000.dtsi17 #size-cells = <0>;
22 reg = <0x0>;
29 reg = <0x1>;
36 #clock-cells = <0>;
51 thermal-sensors = <&tsensor 0>;
71 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
72 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
73 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
74 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
82 ranges = <1 0x0 0x0 0x18400000 0x4000>;
[all …]
H A Dloongson-2k0500.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0>;
29 #clock-cells = <0>;
44 thermal-sensors = <&tsensor 0>;
64 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
65 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
66 <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
67 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
68 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
[all …]
H A Dloongson-2k1000.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg= <0x0>;
30 reg = <0x1>;
37 #clock-cells = <0>;
49 i2c-gpio-0 {
51 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
55 #size-cells = <0>;
66 #size-cells = <0>;
74 thermal-sensors = <&tsensor 0>;
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmpc866ads.dts19 #size-cells = <0>;
21 PowerPC,866@0 {
23 reg = <0x0>;
26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x800000>;
45 reg = <0xff000100 0x40>;
[all …]
H A Dtqm8xx.dts26 #size-cells = <0>;
28 PowerPC,860@0 {
30 reg = <0x0>;
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
45 reg = <0x0 0x2000000>;
52 reg = <0xfff00100 0x40>;
[all …]
H A Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/linux/arch/mips/include/asm/mach-db1x00/
H A Dbcsr.h23 #define DB1000_BCSR_PHYS_ADDR 0x0E000000
24 #define DB1000_BCSR_HEXLED_OFS 0x01000000
26 #define DB1550_BCSR_PHYS_ADDR 0x0F000000
27 #define DB1550_BCSR_HEXLED_OFS 0x00400000
29 #define PB1550_BCSR_PHYS_ADDR 0x0F000000
30 #define PB1550_BCSR_HEXLED_OFS 0x00800000
32 #define DB1200_BCSR_PHYS_ADDR 0x19800000
33 #define DB1200_BCSR_HEXLED_OFS 0x00400000
35 #define PB1200_BCSR_PHYS_ADDR 0x0D800000
36 #define PB1200_BCSR_HEXLED_OFS 0x00400000
[all …]
/linux/drivers/infiniband/sw/siw/
H A Diwarp.h20 #define MPA_IRD_ORD_MASK 0x3fff
31 MPA_RR_FLAG_MARKERS = cpu_to_be16(0x8000),
32 MPA_RR_FLAG_CRC = cpu_to_be16(0x4000),
33 MPA_RR_FLAG_REJECT = cpu_to_be16(0x2000),
34 MPA_RR_FLAG_ENHANCED = cpu_to_be16(0x1000),
35 MPA_RR_FLAG_GSO_EXP = cpu_to_be16(0x0800),
36 MPA_RR_MASK_REVISION = cpu_to_be16(0x00ff)
61 MPA_V2_PEER_TO_PEER = cpu_to_be16(0x8000),
62 MPA_V2_ZERO_LENGTH_RTR = cpu_to_be16(0x4000),
63 MPA_V2_RDMA_WRITE_RTR = cpu_to_be16(0x8000),
[all …]
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dxmit.h46 #define B43legacy_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
48 #define B43legacy_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
50 #define B43legacy_TX4_MAC_LIFETIME 0x00001000
51 #define B43legacy_TX4_MAC_FRAMEBURST 0x00000800
52 #define B43legacy_TX4_MAC_SENDCTS 0x00000400
53 #define B43legacy_TX4_MAC_AMPDU 0x00000300
55 #define B43legacy_TX4_MAC_CTSFALLBACKOFDM 0x00000200
56 #define B43legacy_TX4_MAC_FALLBACKOFDM 0x00000100
57 #define B43legacy_TX4_MAC_5GHZ 0x00000080
58 #define B43legacy_TX4_MAC_IGNPMQ 0x00000020
[all …]
/linux/drivers/mfd/
H A Dwm8350-regmap.c23 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Reset/ID */
24 { 0x7CFF, 0x0C00, 0x0000 }, /* R1 - ID */
25 { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
26 { 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
27 { 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
28 { 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
29 { 0xFB0E, 0xFB0E, 0x0000 }, /* R6 - Interface Control */
30 { 0x0000, 0x0000, 0x0000 }, /* R7 */
31 { 0xE537, 0xE537, 0xFFFF }, /* R8 - Power mgmt (1) */
32 { 0x0FF3, 0x0FF3, 0xFFFF }, /* R9 - Power mgmt (2) */
[all …]
/linux/sound/hda/codecs/
H A Dca0132_regs.h12 #define DSP_CHIP_OFFSET 0x100000
13 #define DSP_DBGCNTL_MODULE_OFFSET 0xE30
17 #define DSP_DBGCNTL_EXEC_LOBIT 0x0
18 #define DSP_DBGCNTL_EXEC_HIBIT 0x3
19 #define DSP_DBGCNTL_EXEC_MASK 0xF
21 #define DSP_DBGCNTL_SS_LOBIT 0x4
22 #define DSP_DBGCNTL_SS_HIBIT 0x7
23 #define DSP_DBGCNTL_SS_MASK 0xF0
25 #define DSP_DBGCNTL_STATE_LOBIT 0xA
26 #define DSP_DBGCNTL_STATE_HIBIT 0xD
[all …]
/linux/drivers/edac/
H A Daltera_edac.h15 #define CV_CTLCFG_OFST 0x00
18 #define CV_CTLCFG_ECC_EN 0x400
19 #define CV_CTLCFG_ECC_CORR_EN 0x800
20 #define CV_CTLCFG_GEN_SB_ERR 0x2000
21 #define CV_CTLCFG_GEN_DB_ERR 0x4000
26 #define CV_DRAMADDRW_OFST 0x2C
29 #define DRAMADDRW_COLBIT_MASK 0x001F
30 #define DRAMADDRW_COLBIT_SHIFT 0
31 #define DRAMADDRW_ROWBIT_MASK 0x03E0
33 #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dxmit.h101 #define B43_TXH_MAC_RTS_FB_SHORTPRMBL 0x80000000 /* RTS fallback preamble */
102 #define B43_TXH_MAC_RTS_SHORTPRMBL 0x40000000 /* RTS main rate preamble */
103 #define B43_TXH_MAC_FB_SHORTPRMBL 0x20000000 /* Main fallback preamble */
104 #define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */
105 #define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */
107 #define B43_TXH_MAC_ALT_TXPWR 0x00080000 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
108 #define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */
110 #define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */
111 #define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */
112 #define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */
[all …]

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