1846aef1dSAjit Kumar Pandey /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2846aef1dSAjit Kumar Pandey /* 3846aef1dSAjit Kumar Pandey * This file is provided under a dual BSD/GPLv2 license. When using or 4846aef1dSAjit Kumar Pandey * redistributing this file, you may do so under either license. 5846aef1dSAjit Kumar Pandey * 6d0dab6b7SVenkata Prasad Potturu * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7846aef1dSAjit Kumar Pandey * 8846aef1dSAjit Kumar Pandey * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 9846aef1dSAjit Kumar Pandey */ 10846aef1dSAjit Kumar Pandey 11846aef1dSAjit Kumar Pandey #ifndef _ACP_DSP_IP_OFFSET_H 12846aef1dSAjit Kumar Pandey #define _ACP_DSP_IP_OFFSET_H 13846aef1dSAjit Kumar Pandey 140e44572aSAjit Kumar Pandey /* Registers from ACP_DMA_0 block */ 150e44572aSAjit Kumar Pandey #define ACP_DMA_CNTL_0 0x00 160e44572aSAjit Kumar Pandey #define ACP_DMA_DSCR_STRT_IDX_0 0x20 170e44572aSAjit Kumar Pandey #define ACP_DMA_DSCR_CNT_0 0x40 180e44572aSAjit Kumar Pandey #define ACP_DMA_PRIO_0 0x60 190e44572aSAjit Kumar Pandey #define ACP_DMA_CUR_DSCR_0 0x80 200e44572aSAjit Kumar Pandey #define ACP_DMA_ERR_STS_0 0xC0 210e44572aSAjit Kumar Pandey #define ACP_DMA_DESC_BASE_ADDR 0xE0 220e44572aSAjit Kumar Pandey #define ACP_DMA_DESC_MAX_NUM_DSCR 0xE4 230e44572aSAjit Kumar Pandey #define ACP_DMA_CH_STS 0xE8 240e44572aSAjit Kumar Pandey #define ACP_DMA_CH_GROUP 0xEC 250e44572aSAjit Kumar Pandey #define ACP_DMA_CH_RST_STS 0xF0 260e44572aSAjit Kumar Pandey 277e51a9e3SAjit Kumar Pandey /* Registers from ACP_DSP_0 block */ 287e51a9e3SAjit Kumar Pandey #define ACP_DSP0_RUNSTALL 0x414 297e51a9e3SAjit Kumar Pandey 300e44572aSAjit Kumar Pandey /* Registers from ACP_AXI2AXIATU block */ 310e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0xC00 320e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0xC04 330e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0xC08 340e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0xC0C 350e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0xC10 360e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0xC14 370e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0xC18 380e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0xC1C 390e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20 400e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24 410e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0xC28 420e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0xC2C 430e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0xC30 440e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0xC34 450e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0xC38 460e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0xC3C 470e44572aSAjit Kumar Pandey #define ACPAXI2AXI_ATU_CTRL 0xC40 48846aef1dSAjit Kumar Pandey #define ACP_SOFT_RESET 0x1000 49b585692fSAjit Kumar Pandey #define ACP_CONTROL 0x1004 50846aef1dSAjit Kumar Pandey 514da6b033SAjit Kumar Pandey #define ACP3X_I2S_PIN_CONFIG 0x1400 52d0dab6b7SVenkata Prasad Potturu #define ACP5X_I2S_PIN_CONFIG 0x1400 5341cb85bcSV sujith kumar Reddy #define ACP6X_I2S_PIN_CONFIG 0x1440 54bda93076SAjit Kumar Pandey 554da6b033SAjit Kumar Pandey /* Registers offsets from ACP_PGFSM block */ 564da6b033SAjit Kumar Pandey #define ACP3X_PGFSM_BASE 0x141C 57d0dab6b7SVenkata Prasad Potturu #define ACP5X_PGFSM_BASE 0x1424 5841cb85bcSV sujith kumar Reddy #define ACP6X_PGFSM_BASE 0x1024 594da6b033SAjit Kumar Pandey #define PGFSM_CONTROL_OFFSET 0x0 604da6b033SAjit Kumar Pandey #define PGFSM_STATUS_OFFSET 0x4 614da6b033SAjit Kumar Pandey #define ACP3X_CLKMUX_SEL 0x1424 62d0dab6b7SVenkata Prasad Potturu #define ACP5X_CLKMUX_SEL 0x142C 6341cb85bcSV sujith kumar Reddy #define ACP6X_CLKMUX_SEL 0x102C 64846aef1dSAjit Kumar Pandey 650e44572aSAjit Kumar Pandey /* Registers from ACP_INTR block */ 664da6b033SAjit Kumar Pandey #define ACP3X_EXT_INTR_STAT 0x1808 67d0dab6b7SVenkata Prasad Potturu #define ACP5X_EXT_INTR_STAT 0x1808 688af5c7e9SVijendar Mukunda #define ACP6X_EXTERNAL_INTR_ENB 0x1A00 698af5c7e9SVijendar Mukunda #define ACP6X_EXTERNAL_INTR_CNTL 0x1A04 7041cb85bcSV sujith kumar Reddy #define ACP6X_EXT_INTR_STAT 0x1A0C 718af5c7e9SVijendar Mukunda #define ACP6X_EXT_INTR_STAT1 0x1A10 724da6b033SAjit Kumar Pandey 734da6b033SAjit Kumar Pandey #define ACP3X_DSP_SW_INTR_BASE 0x1814 74d0dab6b7SVenkata Prasad Potturu #define ACP5X_DSP_SW_INTR_BASE 0x1814 7541cb85bcSV sujith kumar Reddy #define ACP6X_DSP_SW_INTR_BASE 0x1808 764da6b033SAjit Kumar Pandey #define DSP_SW_INTR_CNTL_OFFSET 0x0 774da6b033SAjit Kumar Pandey #define DSP_SW_INTR_STAT_OFFSET 0x4 784da6b033SAjit Kumar Pandey #define DSP_SW_INTR_TRIG_OFFSET 0x8 79*897e91e9SVijendar Mukunda #define ACP3X_ERROR_STATUS 0x18C4 80*897e91e9SVijendar Mukunda #define ACP6X_ERROR_STATUS 0x1A4C 814da6b033SAjit Kumar Pandey #define ACP3X_AXI2DAGB_SEM_0 0x1880 82d0dab6b7SVenkata Prasad Potturu #define ACP5X_AXI2DAGB_SEM_0 0x1884 8341cb85bcSV sujith kumar Reddy #define ACP6X_AXI2DAGB_SEM_0 0x1874 840e44572aSAjit Kumar Pandey 8596eb8185SVijendar Mukunda /* ACP common registers to report errors related to I2S & SoundWire interfaces */ 86*897e91e9SVijendar Mukunda #define ACP3X_SW_I2S_ERROR_REASON 0x18C8 87*897e91e9SVijendar Mukunda #define ACP6X_SW0_I2S_ERROR_REASON 0x18B4 8896eb8185SVijendar Mukunda #define ACP_SW1_I2S_ERROR_REASON 0x1A50 8996eb8185SVijendar Mukunda 900e44572aSAjit Kumar Pandey /* Registers from ACP_SHA block */ 910e44572aSAjit Kumar Pandey #define ACP_SHA_DSP_FW_QUALIFIER 0x1C70 920e44572aSAjit Kumar Pandey #define ACP_SHA_DMA_CMD 0x1CB0 930e44572aSAjit Kumar Pandey #define ACP_SHA_MSG_LENGTH 0x1CB4 940e44572aSAjit Kumar Pandey #define ACP_SHA_DMA_STRT_ADDR 0x1CB8 950e44572aSAjit Kumar Pandey #define ACP_SHA_DMA_DESTINATION_ADDR 0x1CBC 960e44572aSAjit Kumar Pandey #define ACP_SHA_DMA_CMD_STS 0x1CC0 970e44572aSAjit Kumar Pandey #define ACP_SHA_DMA_ERR_STATUS 0x1CC4 980e44572aSAjit Kumar Pandey #define ACP_SHA_TRANSFER_BYTE_CNT 0x1CC8 996a69b724SVenkata Prasad Potturu #define ACP_SHA_DMA_INCLUDE_HDR 0x1CCC 100f063eba3SAjit Kumar Pandey #define ACP_SHA_PSP_ACK 0x1C74 1010e44572aSAjit Kumar Pandey 1020e44572aSAjit Kumar Pandey #define ACP_SCRATCH_REG_0 0x10000 10341cb85bcSV sujith kumar Reddy #define ACP6X_DSP_FUSION_RUNSTALL 0x0644 104b5ba6461SV sujith kumar Reddy 105b5ba6461SV sujith kumar Reddy /* Cache window registers */ 106b5ba6461SV sujith kumar Reddy #define ACP_DSP0_CACHE_OFFSET0 0x0420 107b5ba6461SV sujith kumar Reddy #define ACP_DSP0_CACHE_SIZE0 0x0424 108260b08aeSVijendar Mukunda 109260b08aeSVijendar Mukunda #define ACP_SW0_EN 0x3000 110260b08aeSVijendar Mukunda #define ACP_SW1_EN 0x3C00 111846aef1dSAjit Kumar Pandey #endif 112