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/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-usb2-dr-1.dtsi2 * PQ3 USB DR device tree stub [ controller @ offset 0x23000 ]
37 reg = <0x23000 0x1000>;
39 #size-cells = <0>;
40 interrupts = <46 0x2 0 0>;
H A Dmpc8536si-post.dtsi39 interrupts = <19 2 0 0>;
42 /* controller at 0x8000 */
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
53 /* controller at 0x9000 */
59 bus-range = <0 255>;
61 interrupts = <25 2 0 0>;
63 pcie@0 {
64 reg = <0 0 0 0 0>;
69 interrupts = <25 2 0 0>;
[all …]
/linux/drivers/clk/qcom/
H A Dlpasscorecc-sc7180.c30 { 249600000, 2000000000, 0 },
34 .l = 0x20,
35 .alpha = 0x0,
36 .config_ctl_val = 0x20485699,
37 .config_ctl_hi_val = 0x00002067,
38 .test_ctl_val = 0x40000000,
39 .test_ctl_hi_val = 0x00000000,
40 .user_ctl_val = 0x00005105,
41 .user_ctl_hi_val = 0x00004805,
46 [PLL_OFF_L_VAL] = 0x04,
[all …]
H A Dnwgcc-nord.c36 .offset = 0x0,
39 .enable_reg = 0x0,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 { P_BI_TCXO, 0 },
89 F(60000000, P_NW_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
90 F(100000000, P_NW_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
91 F(200000000, P_NW_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
96 .cmd_rcgr = 0x20004,
[all …]
H A Dgcc-msm8909.c52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
H A Dgcc-sm8750.c53 .offset = 0x0,
56 .enable_reg = 0x52020,
57 .enable_mask = BIT(0),
70 { 0x1, 2 },
75 .offset = 0x0,
92 .offset = 0x1000,
95 .enable_reg = 0x52020,
109 .offset = 0x4000,
112 .enable_reg = 0x52020,
126 .offset = 0x7000,
[all …]
H A Dgcc-sdx65.c36 .offset = 0x0,
39 .enable_reg = 0x6d000,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
73 { P_BI_TCXO, 0 },
91 { P_BI_TCXO, 0 },
105 { P_BI_TCXO, 0 },
119 { P_PCIE_PIPE_CLK, 0 },
129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
[all …]
H A Dgcc-kaanapali.c53 .offset = 0x0,
56 .enable_reg = 0x52020,
57 .enable_mask = BIT(0),
70 { 0x1, 2 },
75 .offset = 0x0,
92 .offset = 0x1000,
95 .enable_reg = 0x52020,
109 .offset = 0x4000,
112 .enable_reg = 0x52020,
126 .offset = 0x7000,
[all …]
H A Dgcc-nord.c46 .offset = 0x0,
49 .enable_reg = 0x9d020,
50 .enable_mask = BIT(0),
63 { 0x1, 2 },
68 .offset = 0x0,
85 { P_BI_TCXO, 0 },
97 { P_BI_TCXO, 0 },
107 { P_BI_TCXO, 0 },
121 { P_BI_TCXO, 0 },
131 .reg = 0x49094,
[all …]
H A Dgcc-hawi.c57 .offset = 0x0,
60 .enable_reg = 0x52028,
61 .enable_mask = BIT(0),
74 { 0x1, 2 },
79 .offset = 0x0,
96 .offset = 0x4000,
99 .enable_reg = 0x52028,
113 .offset = 0x5000,
116 .enable_reg = 0x52028,
130 .offset = 0x7000,
[all …]
H A Dgcc-sm8650.c63 .offset = 0x0,
66 .enable_reg = 0x52020,
67 .enable_mask = BIT(0),
80 .offset = 0x0,
83 .enable_reg = 0x57020,
84 .enable_mask = BIT(0),
97 { 0x1, 2 },
102 .offset = 0x0,
119 .offset = 0x0,
136 .offset = 0x4000,
[all …]
H A Dcamcc-milos.c56 { 249600000, 2300000000, 0 },
60 { 777000000, 1285000000, 0 },
65 .l = 0x3e,
66 .alpha = 0x8000,
67 .config_ctl_val = 0x20485699,
68 .config_ctl_hi_val = 0x00182261,
69 .config_ctl_hi1_val = 0x82aa299c,
70 .test_ctl_val = 0x00000000,
71 .test_ctl_hi_val = 0x00000003,
72 .test_ctl_hi1_val = 0x00009000,
[all …]
/linux/arch/arm/mach-omap2/
H A Domap34xx.h17 #define L4_34XX_BASE 0x48000000
18 #define L4_WK_34XX_BASE 0x48300000
19 #define L4_PER_34XX_BASE 0x49000000
20 #define L4_EMU_34XX_BASE 0x54000000
21 #define L3_34XX_BASE 0x68000000
23 #define L4_WK_AM33XX_BASE 0x44C00000
25 #define OMAP3430_32KSYNCT_BASE 0x48320000
26 #define OMAP3430_CM_BASE 0x48004800
27 #define OMAP3430_PRM_BASE 0x48306800
28 #define OMAP343X_SMS_BASE 0x6C000000
[all …]
/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-drv.c40 int err = 0; in dcss_drv_platform_probe()
46 remote = of_graph_get_remote_node(dev->of_node, 0, 0); in dcss_drv_platform_probe()
71 return 0; in dcss_drv_platform_probe()
97 .blkctl_ofs = 0x2F000,
98 .ctxld_ofs = 0x23000,
99 .dtg_ofs = 0x20000,
100 .scaler_ofs = 0x1C000,
101 .ss_ofs = 0x1B000,
102 .dpr_ofs = 0x18000,
/linux/Documentation/devicetree/bindings/rtc/
H A Dti,omap-rtc.yaml51 pinctrl-0:
66 "^ext-wakeup(-[0-9]+)?$":
74 pattern: '^ext_wakeup[0-3]$'
109 "^ext-wakeup(-[0-9]+)?$": false
117 reg = <0x23000 0x1000>;
124 rtc@0 {
126 reg = <0x0 0x1000>;
132 pinctrl-0 = <&ext_wakeup>;
/linux/arch/powerpc/boot/dts/
H A Dmpc8349emitxgp.dts25 #size-cells = <0>;
27 PowerPC,8349@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
40 memory@0 {
42 reg = <0x00000000 0x10000000>;
50 ranges = <0x0 0xe0000000 0x00100000>;
51 reg = <0xe0000000 0x00000200>;
[all …]
H A Dasp834x-redboot.dts25 #size-cells = <0>;
27 PowerPC,8347@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
40 memory@0 {
42 reg = <0x00000000 0x8000000>; // 128MB at 0
51 reg = <0xff005000 0x1000>;
52 interrupts = <77 0x8>;
[all …]
H A Dmpc8349emitx.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
42 memory@0 {
44 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <0xe0000000 0x00000200>;
[all …]
H A Dmpc8313erdb.dts27 #size-cells = <0>;
29 PowerPC,8313@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
42 memory@0 {
44 reg = <0x00000000 0x08000000>; // 128MB at 0
51 reg = <0xe0005000 0x1000>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-afe-common.h121 MT8365_AFE_APLL1 = 0,
127 MT8365_AFE_1ST_I2S = 0,
133 MT8365_AFE_I2S_SEPARATE_CLOCK = 0,
138 MT8365_AFE_TDM_OUT_I2S = 0,
144 AFE_TDM_CH_START_O28_O29 = 0,
152 MT8365_PCM_FORMAT_I2S = 0,
159 MT8365_FS_8K = 0,
177 FS_8000HZ = 0, /* 0000b */
205 MT8365_AFE_IRQ_DIR_MCU = 0,
212 MT8365_I2S0_MCK = 0,
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
90 pattern: "^rtu@[0-9a-f]+$"
102 pattern: "^txpru@[0-9a-f]+"
106 pattern: "^pru@[0-9a-f]+$"
119 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
123 ranges = <0x0 0x300000 0x80000>;
125 pruss: pruss@0 {
127 reg = <0x0 0x80000>;
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_13_0_kaanapali.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x1f000, .len = 0x1000,
35 .base = 0x20000, .len = 0x1000,
39 .base = 0x21000, .len = 0x1000,
43 .base = 0x22000, .len = 0x1000,
47 .base = 0x23000, .len = 0x1000,
51 .base = 0x24000, .len = 0x1000,
59 .base = 0x2b000, .len = 0x84,
[all …]
/linux/arch/arm/boot/dts/ti/davinci/
H A Dda850.dtsi16 reg = <0xc0000000 0x0>;
21 #size-cells = <0>;
23 cpu: cpu@0 {
26 reg = <0>;
78 reg = <0xfffee000 0x2000>;
84 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #clock-cells = <0>;
102 reg = <0x11800000 0x40000>,
103 <0x11e00000 0x8000>,
[all …]
/linux/drivers/interconnect/qcom/
H A Dsar2130p.c232 .port_offsets = { 0x9e000 },
234 .urg_fwd = 0,
249 .port_offsets = { 0x9f000 },
251 .urg_fwd = 0,
275 .port_offsets = { 0xe000, 0x4e000 },
276 .prio = 0,
277 .urg_fwd = 0,
292 .port_offsets = { 0xf000, 0x4f000 },
293 .prio = 0,
308 .port_offsets = { 0x9d000 },
[all …]
H A Dsc7280.c167 .port_offsets = { 0x7000 },
169 .urg_fwd = 0,
181 .port_offsets = { 0x11000 },
183 .urg_fwd = 0,
195 .port_offsets = { 0x8000 },
197 .urg_fwd = 0,
217 .port_offsets = { 0xc000 },
219 .urg_fwd = 0,
231 .port_offsets = { 0xe000 },
233 .urg_fwd = 0,
[all …]

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