1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,kaanapali-gcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "clk-regmap-phy-mux.h" 23 #include "common.h" 24 #include "gdsc.h" 25 #include "reset.h" 26 27 enum { 28 DT_BI_TCXO, 29 DT_BI_TCXO_AO, 30 DT_SLEEP_CLK, 31 DT_PCIE_0_PIPE_CLK, 32 DT_UFS_PHY_RX_SYMBOL_0_CLK, 33 DT_UFS_PHY_RX_SYMBOL_1_CLK, 34 DT_UFS_PHY_TX_SYMBOL_0_CLK, 35 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 36 }; 37 38 enum { 39 P_BI_TCXO, 40 P_GCC_GPLL0_OUT_EVEN, 41 P_GCC_GPLL0_OUT_MAIN, 42 P_GCC_GPLL1_OUT_MAIN, 43 P_GCC_GPLL4_OUT_MAIN, 44 P_GCC_GPLL7_OUT_MAIN, 45 P_GCC_GPLL9_OUT_MAIN, 46 P_PCIE_0_PIPE_CLK, 47 P_SLEEP_CLK, 48 P_UFS_PHY_RX_SYMBOL_0_CLK, 49 P_UFS_PHY_RX_SYMBOL_1_CLK, 50 P_UFS_PHY_TX_SYMBOL_0_CLK, 51 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 52 }; 53 54 static struct clk_alpha_pll gcc_gpll0 = { 55 .offset = 0x0, 56 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 57 .clkr = { 58 .enable_reg = 0x52020, 59 .enable_mask = BIT(0), 60 .hw.init = &(const struct clk_init_data) { 61 .name = "gcc_gpll0", 62 .parent_data = &(const struct clk_parent_data) { 63 .index = DT_BI_TCXO, 64 }, 65 .num_parents = 1, 66 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 67 }, 68 }, 69 }; 70 71 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 72 { 0x1, 2 }, 73 { } 74 }; 75 76 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 77 .offset = 0x0, 78 .post_div_shift = 10, 79 .post_div_table = post_div_table_gcc_gpll0_out_even, 80 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 81 .width = 4, 82 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 83 .clkr.hw.init = &(const struct clk_init_data) { 84 .name = "gcc_gpll0_out_even", 85 .parent_hws = (const struct clk_hw*[]) { 86 &gcc_gpll0.clkr.hw, 87 }, 88 .num_parents = 1, 89 .ops = &clk_alpha_pll_postdiv_taycan_eko_t_ops, 90 }, 91 }; 92 93 static struct clk_alpha_pll gcc_gpll1 = { 94 .offset = 0x1000, 95 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 96 .clkr = { 97 .enable_reg = 0x52020, 98 .enable_mask = BIT(1), 99 .hw.init = &(const struct clk_init_data) { 100 .name = "gcc_gpll1", 101 .parent_data = &(const struct clk_parent_data) { 102 .index = DT_BI_TCXO, 103 }, 104 .num_parents = 1, 105 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 106 }, 107 }, 108 }; 109 110 static struct clk_alpha_pll gcc_gpll4 = { 111 .offset = 0x4000, 112 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 113 .clkr = { 114 .enable_reg = 0x52020, 115 .enable_mask = BIT(4), 116 .hw.init = &(const struct clk_init_data) { 117 .name = "gcc_gpll4", 118 .parent_data = &(const struct clk_parent_data) { 119 .index = DT_BI_TCXO, 120 }, 121 .num_parents = 1, 122 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 123 }, 124 }, 125 }; 126 127 static struct clk_alpha_pll gcc_gpll7 = { 128 .offset = 0x7000, 129 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 130 .clkr = { 131 .enable_reg = 0x52020, 132 .enable_mask = BIT(7), 133 .hw.init = &(const struct clk_init_data) { 134 .name = "gcc_gpll7", 135 .parent_data = &(const struct clk_parent_data) { 136 .index = DT_BI_TCXO, 137 }, 138 .num_parents = 1, 139 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 140 }, 141 }, 142 }; 143 144 static struct clk_alpha_pll gcc_gpll9 = { 145 .offset = 0x9000, 146 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T], 147 .clkr = { 148 .enable_reg = 0x52020, 149 .enable_mask = BIT(9), 150 .hw.init = &(const struct clk_init_data) { 151 .name = "gcc_gpll9", 152 .parent_data = &(const struct clk_parent_data) { 153 .index = DT_BI_TCXO, 154 }, 155 .num_parents = 1, 156 .ops = &clk_alpha_pll_fixed_taycan_eko_t_ops, 157 }, 158 }, 159 }; 160 161 static const struct parent_map gcc_parent_map_0[] = { 162 { P_BI_TCXO, 0 }, 163 { P_GCC_GPLL0_OUT_MAIN, 1 }, 164 { P_GCC_GPLL0_OUT_EVEN, 6 }, 165 }; 166 167 static const struct clk_parent_data gcc_parent_data_0[] = { 168 { .index = DT_BI_TCXO }, 169 { .hw = &gcc_gpll0.clkr.hw }, 170 { .hw = &gcc_gpll0_out_even.clkr.hw }, 171 }; 172 173 static const struct parent_map gcc_parent_map_1[] = { 174 { P_BI_TCXO, 0 }, 175 { P_GCC_GPLL0_OUT_MAIN, 1 }, 176 { P_GCC_GPLL1_OUT_MAIN, 4 }, 177 { P_GCC_GPLL4_OUT_MAIN, 5 }, 178 { P_GCC_GPLL0_OUT_EVEN, 6 }, 179 }; 180 181 static const struct clk_parent_data gcc_parent_data_1[] = { 182 { .index = DT_BI_TCXO }, 183 { .hw = &gcc_gpll0.clkr.hw }, 184 { .hw = &gcc_gpll1.clkr.hw }, 185 { .hw = &gcc_gpll4.clkr.hw }, 186 { .hw = &gcc_gpll0_out_even.clkr.hw }, 187 }; 188 189 static const struct parent_map gcc_parent_map_2[] = { 190 { P_BI_TCXO, 0 }, 191 { P_GCC_GPLL0_OUT_MAIN, 1 }, 192 { P_SLEEP_CLK, 5 }, 193 { P_GCC_GPLL0_OUT_EVEN, 6 }, 194 }; 195 196 static const struct clk_parent_data gcc_parent_data_2[] = { 197 { .index = DT_BI_TCXO }, 198 { .hw = &gcc_gpll0.clkr.hw }, 199 { .index = DT_SLEEP_CLK }, 200 { .hw = &gcc_gpll0_out_even.clkr.hw }, 201 }; 202 203 static const struct parent_map gcc_parent_map_3[] = { 204 { P_BI_TCXO, 0 }, 205 { P_GCC_GPLL0_OUT_MAIN, 1 }, 206 { P_GCC_GPLL4_OUT_MAIN, 5 }, 207 { P_GCC_GPLL0_OUT_EVEN, 6 }, 208 }; 209 210 static const struct clk_parent_data gcc_parent_data_3[] = { 211 { .index = DT_BI_TCXO }, 212 { .hw = &gcc_gpll0.clkr.hw }, 213 { .hw = &gcc_gpll4.clkr.hw }, 214 { .hw = &gcc_gpll0_out_even.clkr.hw }, 215 }; 216 217 static const struct parent_map gcc_parent_map_4[] = { 218 { P_BI_TCXO, 0 }, 219 }; 220 221 static const struct clk_parent_data gcc_parent_data_4[] = { 222 { .index = DT_BI_TCXO }, 223 }; 224 225 static const struct parent_map gcc_parent_map_5[] = { 226 { P_BI_TCXO, 0 }, 227 { P_GCC_GPLL0_OUT_MAIN, 1 }, 228 { P_GCC_GPLL7_OUT_MAIN, 2 }, 229 { P_GCC_GPLL0_OUT_EVEN, 6 }, 230 }; 231 232 static const struct clk_parent_data gcc_parent_data_5[] = { 233 { .index = DT_BI_TCXO }, 234 { .hw = &gcc_gpll0.clkr.hw }, 235 { .hw = &gcc_gpll7.clkr.hw }, 236 { .hw = &gcc_gpll0_out_even.clkr.hw }, 237 }; 238 239 static const struct parent_map gcc_parent_map_6[] = { 240 { P_BI_TCXO, 0 }, 241 { P_SLEEP_CLK, 5 }, 242 }; 243 244 static const struct clk_parent_data gcc_parent_data_6[] = { 245 { .index = DT_BI_TCXO }, 246 { .index = DT_SLEEP_CLK }, 247 }; 248 249 static const struct parent_map gcc_parent_map_8[] = { 250 { P_BI_TCXO, 0 }, 251 { P_GCC_GPLL0_OUT_MAIN, 1 }, 252 { P_GCC_GPLL9_OUT_MAIN, 2 }, 253 { P_GCC_GPLL4_OUT_MAIN, 5 }, 254 { P_GCC_GPLL0_OUT_EVEN, 6 }, 255 }; 256 257 static const struct clk_parent_data gcc_parent_data_8[] = { 258 { .index = DT_BI_TCXO }, 259 { .hw = &gcc_gpll0.clkr.hw }, 260 { .hw = &gcc_gpll9.clkr.hw }, 261 { .hw = &gcc_gpll4.clkr.hw }, 262 { .hw = &gcc_gpll0_out_even.clkr.hw }, 263 }; 264 265 static const struct parent_map gcc_parent_map_12[] = { 266 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, 267 { P_BI_TCXO, 2 }, 268 }; 269 270 static const struct clk_parent_data gcc_parent_data_12[] = { 271 { .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK }, 272 { .index = DT_BI_TCXO }, 273 }; 274 275 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 276 .reg = 0x6b090, 277 .clkr = { 278 .hw.init = &(const struct clk_init_data) { 279 .name = "gcc_pcie_0_pipe_clk_src", 280 .parent_data = &(const struct clk_parent_data){ 281 .index = DT_PCIE_0_PIPE_CLK, 282 }, 283 .num_parents = 1, 284 .ops = &clk_regmap_phy_mux_ops, 285 }, 286 }, 287 }; 288 289 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 290 .reg = 0x77068, 291 .clkr = { 292 .hw.init = &(const struct clk_init_data) { 293 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 294 .parent_data = &(const struct clk_parent_data){ 295 .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, 296 }, 297 .num_parents = 1, 298 .ops = &clk_regmap_phy_mux_ops, 299 }, 300 }, 301 }; 302 303 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 304 .reg = 0x770ec, 305 .clkr = { 306 .hw.init = &(const struct clk_init_data) { 307 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 308 .parent_data = &(const struct clk_parent_data){ 309 .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, 310 }, 311 .num_parents = 1, 312 .ops = &clk_regmap_phy_mux_ops, 313 }, 314 }, 315 }; 316 317 static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 318 .reg = 0x77058, 319 .clkr = { 320 .hw.init = &(const struct clk_init_data) { 321 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 322 .parent_data = &(const struct clk_parent_data){ 323 .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, 324 }, 325 .num_parents = 1, 326 .ops = &clk_regmap_phy_mux_ops, 327 }, 328 }, 329 }; 330 331 static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = { 332 .reg = 0x39074, 333 .shift = 0, 334 .width = 2, 335 .parent_map = gcc_parent_map_12, 336 .clkr = { 337 .hw.init = &(const struct clk_init_data) { 338 .name = "gcc_usb3_prim_phy_pipe_clk_src", 339 .parent_data = gcc_parent_data_12, 340 .num_parents = ARRAY_SIZE(gcc_parent_data_12), 341 .ops = &clk_regmap_mux_closest_ops, 342 }, 343 }, 344 }; 345 346 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 347 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 348 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 349 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 350 { } 351 }; 352 353 static struct clk_rcg2 gcc_gp1_clk_src = { 354 .cmd_rcgr = 0x64004, 355 .mnd_width = 16, 356 .hid_width = 5, 357 .parent_map = gcc_parent_map_2, 358 .freq_tbl = ftbl_gcc_gp1_clk_src, 359 .clkr.hw.init = &(const struct clk_init_data) { 360 .name = "gcc_gp1_clk_src", 361 .parent_data = gcc_parent_data_2, 362 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 363 .flags = CLK_SET_RATE_PARENT, 364 .ops = &clk_rcg2_ops, 365 }, 366 }; 367 368 static struct clk_rcg2 gcc_gp2_clk_src = { 369 .cmd_rcgr = 0x65004, 370 .mnd_width = 16, 371 .hid_width = 5, 372 .parent_map = gcc_parent_map_2, 373 .freq_tbl = ftbl_gcc_gp1_clk_src, 374 .clkr.hw.init = &(const struct clk_init_data) { 375 .name = "gcc_gp2_clk_src", 376 .parent_data = gcc_parent_data_2, 377 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 378 .flags = CLK_SET_RATE_PARENT, 379 .ops = &clk_rcg2_ops, 380 }, 381 }; 382 383 static struct clk_rcg2 gcc_gp3_clk_src = { 384 .cmd_rcgr = 0x66004, 385 .mnd_width = 16, 386 .hid_width = 5, 387 .parent_map = gcc_parent_map_2, 388 .freq_tbl = ftbl_gcc_gp1_clk_src, 389 .clkr.hw.init = &(const struct clk_init_data) { 390 .name = "gcc_gp3_clk_src", 391 .parent_data = gcc_parent_data_2, 392 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 393 .flags = CLK_SET_RATE_PARENT, 394 .ops = &clk_rcg2_ops, 395 }, 396 }; 397 398 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 399 F(19200000, P_BI_TCXO, 1, 0, 0), 400 { } 401 }; 402 403 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 404 .cmd_rcgr = 0x6b094, 405 .mnd_width = 16, 406 .hid_width = 5, 407 .parent_map = gcc_parent_map_6, 408 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 409 .clkr.hw.init = &(const struct clk_init_data) { 410 .name = "gcc_pcie_0_aux_clk_src", 411 .parent_data = gcc_parent_data_6, 412 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 413 .flags = CLK_SET_RATE_PARENT, 414 .ops = &clk_rcg2_shared_no_init_park_ops, 415 }, 416 }; 417 418 static struct clk_rcg2 gcc_pcie_0_phy_aux_clk_src = { 419 .cmd_rcgr = 0x6b0ac, 420 .mnd_width = 0, 421 .hid_width = 5, 422 .parent_map = gcc_parent_map_0, 423 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 424 .clkr.hw.init = &(const struct clk_init_data) { 425 .name = "gcc_pcie_0_phy_aux_clk_src", 426 .parent_data = gcc_parent_data_0, 427 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 428 .flags = CLK_SET_RATE_PARENT, 429 .ops = &clk_rcg2_shared_no_init_park_ops, 430 }, 431 }; 432 433 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 434 F(19200000, P_BI_TCXO, 1, 0, 0), 435 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 436 { } 437 }; 438 439 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 440 .cmd_rcgr = 0x6b078, 441 .mnd_width = 0, 442 .hid_width = 5, 443 .parent_map = gcc_parent_map_0, 444 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 445 .clkr.hw.init = &(const struct clk_init_data) { 446 .name = "gcc_pcie_0_phy_rchng_clk_src", 447 .parent_data = gcc_parent_data_0, 448 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 449 .flags = CLK_SET_RATE_PARENT, 450 .ops = &clk_rcg2_shared_no_init_park_ops, 451 }, 452 }; 453 454 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 455 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 456 { } 457 }; 458 459 static struct clk_rcg2 gcc_pdm2_clk_src = { 460 .cmd_rcgr = 0x33010, 461 .mnd_width = 0, 462 .hid_width = 5, 463 .parent_map = gcc_parent_map_0, 464 .freq_tbl = ftbl_gcc_pdm2_clk_src, 465 .clkr.hw.init = &(const struct clk_init_data) { 466 .name = "gcc_pdm2_clk_src", 467 .parent_data = gcc_parent_data_0, 468 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 469 .flags = CLK_SET_RATE_PARENT, 470 .ops = &clk_rcg2_shared_no_init_park_ops, 471 }, 472 }; 473 474 static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { 475 .cmd_rcgr = 0x17008, 476 .mnd_width = 0, 477 .hid_width = 5, 478 .parent_map = gcc_parent_map_0, 479 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 480 .clkr.hw.init = &(const struct clk_init_data) { 481 .name = "gcc_qupv3_i2c_s0_clk_src", 482 .parent_data = gcc_parent_data_0, 483 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 484 .flags = CLK_SET_RATE_PARENT, 485 .ops = &clk_rcg2_shared_no_init_park_ops, 486 }, 487 }; 488 489 static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { 490 .cmd_rcgr = 0x17024, 491 .mnd_width = 0, 492 .hid_width = 5, 493 .parent_map = gcc_parent_map_0, 494 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 495 .clkr.hw.init = &(const struct clk_init_data) { 496 .name = "gcc_qupv3_i2c_s1_clk_src", 497 .parent_data = gcc_parent_data_0, 498 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 499 .flags = CLK_SET_RATE_PARENT, 500 .ops = &clk_rcg2_shared_no_init_park_ops, 501 }, 502 }; 503 504 static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { 505 .cmd_rcgr = 0x17040, 506 .mnd_width = 0, 507 .hid_width = 5, 508 .parent_map = gcc_parent_map_0, 509 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 510 .clkr.hw.init = &(const struct clk_init_data) { 511 .name = "gcc_qupv3_i2c_s2_clk_src", 512 .parent_data = gcc_parent_data_0, 513 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 514 .flags = CLK_SET_RATE_PARENT, 515 .ops = &clk_rcg2_shared_no_init_park_ops, 516 }, 517 }; 518 519 static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { 520 .cmd_rcgr = 0x1705c, 521 .mnd_width = 0, 522 .hid_width = 5, 523 .parent_map = gcc_parent_map_0, 524 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 525 .clkr.hw.init = &(const struct clk_init_data) { 526 .name = "gcc_qupv3_i2c_s3_clk_src", 527 .parent_data = gcc_parent_data_0, 528 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 529 .flags = CLK_SET_RATE_PARENT, 530 .ops = &clk_rcg2_shared_no_init_park_ops, 531 }, 532 }; 533 534 static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { 535 .cmd_rcgr = 0x17078, 536 .mnd_width = 0, 537 .hid_width = 5, 538 .parent_map = gcc_parent_map_0, 539 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 540 .clkr.hw.init = &(const struct clk_init_data) { 541 .name = "gcc_qupv3_i2c_s4_clk_src", 542 .parent_data = gcc_parent_data_0, 543 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 544 .flags = CLK_SET_RATE_PARENT, 545 .ops = &clk_rcg2_shared_no_init_park_ops, 546 }, 547 }; 548 549 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = { 550 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 551 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 552 F(19200000, P_BI_TCXO, 1, 0, 0), 553 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 554 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 555 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 556 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 557 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 558 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 559 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 560 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 561 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 562 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 563 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 564 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 565 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 566 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 567 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 568 F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0), 569 { } 570 }; 571 572 static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = { 573 .name = "gcc_qupv3_wrap1_qspi_ref_clk_src", 574 .parent_data = gcc_parent_data_5, 575 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 576 .flags = CLK_SET_RATE_PARENT, 577 .ops = &clk_rcg2_shared_no_init_park_ops, 578 }; 579 580 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = { 581 .cmd_rcgr = 0x188c0, 582 .mnd_width = 16, 583 .hid_width = 5, 584 .parent_map = gcc_parent_map_5, 585 .freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src, 586 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init, 587 }; 588 589 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 590 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 591 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 592 F(19200000, P_BI_TCXO, 1, 0, 0), 593 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 594 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 595 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 596 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 597 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 598 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 599 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 600 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 601 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 602 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 603 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 604 { } 605 }; 606 607 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 608 .name = "gcc_qupv3_wrap1_s0_clk_src", 609 .parent_data = gcc_parent_data_0, 610 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 611 .flags = CLK_SET_RATE_PARENT, 612 .ops = &clk_rcg2_shared_no_init_park_ops, 613 }; 614 615 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 616 .cmd_rcgr = 0x18014, 617 .mnd_width = 16, 618 .hid_width = 5, 619 .parent_map = gcc_parent_map_0, 620 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 621 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 622 }; 623 624 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 625 .name = "gcc_qupv3_wrap1_s1_clk_src", 626 .parent_data = gcc_parent_data_0, 627 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 628 .flags = CLK_SET_RATE_PARENT, 629 .ops = &clk_rcg2_shared_no_init_park_ops, 630 }; 631 632 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 633 .cmd_rcgr = 0x18150, 634 .mnd_width = 16, 635 .hid_width = 5, 636 .parent_map = gcc_parent_map_0, 637 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 638 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 639 }; 640 641 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 642 .name = "gcc_qupv3_wrap1_s3_clk_src", 643 .parent_data = gcc_parent_data_0, 644 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 645 .flags = CLK_SET_RATE_PARENT, 646 .ops = &clk_rcg2_shared_no_init_park_ops, 647 }; 648 649 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 650 .cmd_rcgr = 0x182a0, 651 .mnd_width = 16, 652 .hid_width = 5, 653 .parent_map = gcc_parent_map_0, 654 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 655 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 656 }; 657 658 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = { 659 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 660 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 661 F(19200000, P_BI_TCXO, 1, 0, 0), 662 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 663 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 664 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 665 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 666 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 667 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 668 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 669 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 670 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 671 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 672 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 673 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 674 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 675 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 676 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 677 { } 678 }; 679 680 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 681 .name = "gcc_qupv3_wrap1_s4_clk_src", 682 .parent_data = gcc_parent_data_0, 683 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 684 .flags = CLK_SET_RATE_PARENT, 685 .ops = &clk_rcg2_shared_no_init_park_ops, 686 }; 687 688 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 689 .cmd_rcgr = 0x183dc, 690 .mnd_width = 16, 691 .hid_width = 5, 692 .parent_map = gcc_parent_map_0, 693 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 694 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 695 }; 696 697 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 698 .name = "gcc_qupv3_wrap1_s5_clk_src", 699 .parent_data = gcc_parent_data_0, 700 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 701 .flags = CLK_SET_RATE_PARENT, 702 .ops = &clk_rcg2_shared_no_init_park_ops, 703 }; 704 705 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 706 .cmd_rcgr = 0x18518, 707 .mnd_width = 16, 708 .hid_width = 5, 709 .parent_map = gcc_parent_map_0, 710 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 711 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 712 }; 713 714 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 715 .name = "gcc_qupv3_wrap1_s6_clk_src", 716 .parent_data = gcc_parent_data_0, 717 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 718 .flags = CLK_SET_RATE_PARENT, 719 .ops = &clk_rcg2_shared_no_init_park_ops, 720 }; 721 722 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 723 .cmd_rcgr = 0x18654, 724 .mnd_width = 16, 725 .hid_width = 5, 726 .parent_map = gcc_parent_map_0, 727 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 728 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 729 }; 730 731 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 732 .name = "gcc_qupv3_wrap1_s7_clk_src", 733 .parent_data = gcc_parent_data_0, 734 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 735 .flags = CLK_SET_RATE_PARENT, 736 .ops = &clk_rcg2_shared_no_init_park_ops, 737 }; 738 739 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 740 .cmd_rcgr = 0x18790, 741 .mnd_width = 16, 742 .hid_width = 5, 743 .parent_map = gcc_parent_map_0, 744 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 745 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 746 }; 747 748 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 749 .name = "gcc_qupv3_wrap2_s0_clk_src", 750 .parent_data = gcc_parent_data_0, 751 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 752 .flags = CLK_SET_RATE_PARENT, 753 .ops = &clk_rcg2_shared_no_init_park_ops, 754 }; 755 756 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 757 .cmd_rcgr = 0x1e014, 758 .mnd_width = 16, 759 .hid_width = 5, 760 .parent_map = gcc_parent_map_0, 761 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 762 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 763 }; 764 765 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 766 .name = "gcc_qupv3_wrap2_s1_clk_src", 767 .parent_data = gcc_parent_data_0, 768 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 769 .flags = CLK_SET_RATE_PARENT, 770 .ops = &clk_rcg2_shared_no_init_park_ops, 771 }; 772 773 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 774 .cmd_rcgr = 0x1e150, 775 .mnd_width = 16, 776 .hid_width = 5, 777 .parent_map = gcc_parent_map_0, 778 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 779 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 780 }; 781 782 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 783 .name = "gcc_qupv3_wrap2_s2_clk_src", 784 .parent_data = gcc_parent_data_0, 785 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 786 .flags = CLK_SET_RATE_PARENT, 787 .ops = &clk_rcg2_shared_no_init_park_ops, 788 }; 789 790 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 791 .cmd_rcgr = 0x1e28c, 792 .mnd_width = 16, 793 .hid_width = 5, 794 .parent_map = gcc_parent_map_0, 795 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 796 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 797 }; 798 799 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 800 .name = "gcc_qupv3_wrap2_s3_clk_src", 801 .parent_data = gcc_parent_data_0, 802 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 803 .flags = CLK_SET_RATE_PARENT, 804 .ops = &clk_rcg2_shared_no_init_park_ops, 805 }; 806 807 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 808 .cmd_rcgr = 0x1e3c8, 809 .mnd_width = 16, 810 .hid_width = 5, 811 .parent_map = gcc_parent_map_0, 812 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 813 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 814 }; 815 816 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 817 .name = "gcc_qupv3_wrap2_s4_clk_src", 818 .parent_data = gcc_parent_data_0, 819 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 820 .flags = CLK_SET_RATE_PARENT, 821 .ops = &clk_rcg2_shared_no_init_park_ops, 822 }; 823 824 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 825 .cmd_rcgr = 0x1e504, 826 .mnd_width = 16, 827 .hid_width = 5, 828 .parent_map = gcc_parent_map_0, 829 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 830 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 831 }; 832 833 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_ibi_ctrl_0_clk_src[] = { 834 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 835 { } 836 }; 837 838 static struct clk_rcg2 gcc_qupv3_wrap3_ibi_ctrl_0_clk_src = { 839 .cmd_rcgr = 0xa877c, 840 .mnd_width = 0, 841 .hid_width = 5, 842 .parent_map = gcc_parent_map_1, 843 .freq_tbl = ftbl_gcc_qupv3_wrap3_ibi_ctrl_0_clk_src, 844 .clkr.hw.init = &(const struct clk_init_data) { 845 .name = "gcc_qupv3_wrap3_ibi_ctrl_0_clk_src", 846 .parent_data = gcc_parent_data_1, 847 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 848 .flags = CLK_SET_RATE_PARENT, 849 .ops = &clk_rcg2_shared_no_init_park_ops, 850 }, 851 }; 852 853 static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = { 854 .name = "gcc_qupv3_wrap3_s0_clk_src", 855 .parent_data = gcc_parent_data_0, 856 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 857 .flags = CLK_SET_RATE_PARENT, 858 .ops = &clk_rcg2_shared_no_init_park_ops, 859 }; 860 861 static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = { 862 .cmd_rcgr = 0xa8014, 863 .mnd_width = 16, 864 .hid_width = 5, 865 .parent_map = gcc_parent_map_0, 866 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 867 .clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init, 868 }; 869 870 static struct clk_init_data gcc_qupv3_wrap3_s1_clk_src_init = { 871 .name = "gcc_qupv3_wrap3_s1_clk_src", 872 .parent_data = gcc_parent_data_0, 873 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 874 .flags = CLK_SET_RATE_PARENT, 875 .ops = &clk_rcg2_shared_no_init_park_ops, 876 }; 877 878 static struct clk_rcg2 gcc_qupv3_wrap3_s1_clk_src = { 879 .cmd_rcgr = 0xa8150, 880 .mnd_width = 16, 881 .hid_width = 5, 882 .parent_map = gcc_parent_map_0, 883 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 884 .clkr.hw.init = &gcc_qupv3_wrap3_s1_clk_src_init, 885 }; 886 887 static struct clk_init_data gcc_qupv3_wrap3_s2_clk_src_init = { 888 .name = "gcc_qupv3_wrap3_s2_clk_src", 889 .parent_data = gcc_parent_data_0, 890 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 891 .flags = CLK_SET_RATE_PARENT, 892 .ops = &clk_rcg2_shared_no_init_park_ops, 893 }; 894 895 static struct clk_rcg2 gcc_qupv3_wrap3_s2_clk_src = { 896 .cmd_rcgr = 0xa828c, 897 .mnd_width = 16, 898 .hid_width = 5, 899 .parent_map = gcc_parent_map_0, 900 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 901 .clkr.hw.init = &gcc_qupv3_wrap3_s2_clk_src_init, 902 }; 903 904 static struct clk_init_data gcc_qupv3_wrap3_s3_clk_src_init = { 905 .name = "gcc_qupv3_wrap3_s3_clk_src", 906 .parent_data = gcc_parent_data_0, 907 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 908 .flags = CLK_SET_RATE_PARENT, 909 .ops = &clk_rcg2_shared_no_init_park_ops, 910 }; 911 912 static struct clk_rcg2 gcc_qupv3_wrap3_s3_clk_src = { 913 .cmd_rcgr = 0xa83c8, 914 .mnd_width = 16, 915 .hid_width = 5, 916 .parent_map = gcc_parent_map_0, 917 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 918 .clkr.hw.init = &gcc_qupv3_wrap3_s3_clk_src_init, 919 }; 920 921 static struct clk_init_data gcc_qupv3_wrap3_s4_clk_src_init = { 922 .name = "gcc_qupv3_wrap3_s4_clk_src", 923 .parent_data = gcc_parent_data_0, 924 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 925 .flags = CLK_SET_RATE_PARENT, 926 .ops = &clk_rcg2_shared_no_init_park_ops, 927 }; 928 929 static struct clk_rcg2 gcc_qupv3_wrap3_s4_clk_src = { 930 .cmd_rcgr = 0xa8504, 931 .mnd_width = 16, 932 .hid_width = 5, 933 .parent_map = gcc_parent_map_0, 934 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 935 .clkr.hw.init = &gcc_qupv3_wrap3_s4_clk_src_init, 936 }; 937 938 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s5_clk_src[] = { 939 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 940 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 941 F(19200000, P_BI_TCXO, 1, 0, 0), 942 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 943 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 944 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 945 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 946 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 947 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 948 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 949 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 950 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 951 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 952 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 953 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 954 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 955 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 956 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 957 F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75), 958 { } 959 }; 960 961 static struct clk_init_data gcc_qupv3_wrap3_s5_clk_src_init = { 962 .name = "gcc_qupv3_wrap3_s5_clk_src", 963 .parent_data = gcc_parent_data_0, 964 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 965 .flags = CLK_SET_RATE_PARENT, 966 .ops = &clk_rcg2_shared_no_init_park_ops, 967 }; 968 969 static struct clk_rcg2 gcc_qupv3_wrap3_s5_clk_src = { 970 .cmd_rcgr = 0xa8640, 971 .mnd_width = 16, 972 .hid_width = 5, 973 .parent_map = gcc_parent_map_0, 974 .freq_tbl = ftbl_gcc_qupv3_wrap3_s5_clk_src, 975 .clkr.hw.init = &gcc_qupv3_wrap3_s5_clk_src_init, 976 }; 977 978 static struct clk_init_data gcc_qupv3_wrap4_s0_clk_src_init = { 979 .name = "gcc_qupv3_wrap4_s0_clk_src", 980 .parent_data = gcc_parent_data_0, 981 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 982 .flags = CLK_SET_RATE_PARENT, 983 .ops = &clk_rcg2_shared_no_init_park_ops, 984 }; 985 986 static struct clk_rcg2 gcc_qupv3_wrap4_s0_clk_src = { 987 .cmd_rcgr = 0xa9014, 988 .mnd_width = 16, 989 .hid_width = 5, 990 .parent_map = gcc_parent_map_0, 991 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 992 .clkr.hw.init = &gcc_qupv3_wrap4_s0_clk_src_init, 993 }; 994 995 static struct clk_init_data gcc_qupv3_wrap4_s1_clk_src_init = { 996 .name = "gcc_qupv3_wrap4_s1_clk_src", 997 .parent_data = gcc_parent_data_0, 998 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 999 .flags = CLK_SET_RATE_PARENT, 1000 .ops = &clk_rcg2_shared_no_init_park_ops, 1001 }; 1002 1003 static struct clk_rcg2 gcc_qupv3_wrap4_s1_clk_src = { 1004 .cmd_rcgr = 0xa9150, 1005 .mnd_width = 16, 1006 .hid_width = 5, 1007 .parent_map = gcc_parent_map_0, 1008 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1009 .clkr.hw.init = &gcc_qupv3_wrap4_s1_clk_src_init, 1010 }; 1011 1012 static struct clk_init_data gcc_qupv3_wrap4_s2_clk_src_init = { 1013 .name = "gcc_qupv3_wrap4_s2_clk_src", 1014 .parent_data = gcc_parent_data_0, 1015 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1016 .flags = CLK_SET_RATE_PARENT, 1017 .ops = &clk_rcg2_shared_no_init_park_ops, 1018 }; 1019 1020 static struct clk_rcg2 gcc_qupv3_wrap4_s2_clk_src = { 1021 .cmd_rcgr = 0xa928c, 1022 .mnd_width = 16, 1023 .hid_width = 5, 1024 .parent_map = gcc_parent_map_0, 1025 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1026 .clkr.hw.init = &gcc_qupv3_wrap4_s2_clk_src_init, 1027 }; 1028 1029 static struct clk_init_data gcc_qupv3_wrap4_s3_clk_src_init = { 1030 .name = "gcc_qupv3_wrap4_s3_clk_src", 1031 .parent_data = gcc_parent_data_0, 1032 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1033 .flags = CLK_SET_RATE_PARENT, 1034 .ops = &clk_rcg2_shared_no_init_park_ops, 1035 }; 1036 1037 static struct clk_rcg2 gcc_qupv3_wrap4_s3_clk_src = { 1038 .cmd_rcgr = 0xa93c8, 1039 .mnd_width = 16, 1040 .hid_width = 5, 1041 .parent_map = gcc_parent_map_0, 1042 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1043 .clkr.hw.init = &gcc_qupv3_wrap4_s3_clk_src_init, 1044 }; 1045 1046 static struct clk_init_data gcc_qupv3_wrap4_s4_clk_src_init = { 1047 .name = "gcc_qupv3_wrap4_s4_clk_src", 1048 .parent_data = gcc_parent_data_0, 1049 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1050 .flags = CLK_SET_RATE_PARENT, 1051 .ops = &clk_rcg2_shared_no_init_park_ops, 1052 }; 1053 1054 static struct clk_rcg2 gcc_qupv3_wrap4_s4_clk_src = { 1055 .cmd_rcgr = 0xa9504, 1056 .mnd_width = 16, 1057 .hid_width = 5, 1058 .parent_map = gcc_parent_map_0, 1059 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1060 .clkr.hw.init = &gcc_qupv3_wrap4_s4_clk_src_init, 1061 }; 1062 1063 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1064 F(400000, P_BI_TCXO, 12, 1, 4), 1065 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1066 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1067 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1068 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1069 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1070 { } 1071 }; 1072 1073 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1074 .cmd_rcgr = 0x1401c, 1075 .mnd_width = 8, 1076 .hid_width = 5, 1077 .parent_map = gcc_parent_map_8, 1078 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1079 .clkr.hw.init = &(const struct clk_init_data) { 1080 .name = "gcc_sdcc2_apps_clk_src", 1081 .parent_data = gcc_parent_data_8, 1082 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1083 .flags = CLK_SET_RATE_PARENT, 1084 .ops = &clk_rcg2_shared_floor_ops, 1085 }, 1086 }; 1087 1088 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1089 F(400000, P_BI_TCXO, 12, 1, 4), 1090 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1091 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1092 { } 1093 }; 1094 1095 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1096 .cmd_rcgr = 0x1601c, 1097 .mnd_width = 8, 1098 .hid_width = 5, 1099 .parent_map = gcc_parent_map_0, 1100 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1101 .clkr.hw.init = &(const struct clk_init_data) { 1102 .name = "gcc_sdcc4_apps_clk_src", 1103 .parent_data = gcc_parent_data_0, 1104 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1105 .flags = CLK_SET_RATE_PARENT, 1106 .ops = &clk_rcg2_shared_floor_ops, 1107 }, 1108 }; 1109 1110 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1111 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1112 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1113 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1114 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1115 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1116 { } 1117 }; 1118 1119 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1120 .cmd_rcgr = 0x77034, 1121 .mnd_width = 8, 1122 .hid_width = 5, 1123 .parent_map = gcc_parent_map_3, 1124 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1125 .clkr.hw.init = &(const struct clk_init_data) { 1126 .name = "gcc_ufs_phy_axi_clk_src", 1127 .parent_data = gcc_parent_data_3, 1128 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1129 .flags = CLK_SET_RATE_PARENT, 1130 .ops = &clk_rcg2_shared_no_init_park_ops, 1131 }, 1132 }; 1133 1134 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1135 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1136 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1137 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1138 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1139 { } 1140 }; 1141 1142 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1143 .cmd_rcgr = 0x7708c, 1144 .mnd_width = 0, 1145 .hid_width = 5, 1146 .parent_map = gcc_parent_map_3, 1147 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1148 .clkr.hw.init = &(const struct clk_init_data) { 1149 .name = "gcc_ufs_phy_ice_core_clk_src", 1150 .parent_data = gcc_parent_data_3, 1151 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1152 .flags = CLK_SET_RATE_PARENT, 1153 .ops = &clk_rcg2_shared_no_init_park_ops, 1154 }, 1155 }; 1156 1157 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1158 F(9600000, P_BI_TCXO, 2, 0, 0), 1159 F(19200000, P_BI_TCXO, 1, 0, 0), 1160 { } 1161 }; 1162 1163 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1164 .cmd_rcgr = 0x770c0, 1165 .mnd_width = 0, 1166 .hid_width = 5, 1167 .parent_map = gcc_parent_map_4, 1168 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1169 .clkr.hw.init = &(const struct clk_init_data) { 1170 .name = "gcc_ufs_phy_phy_aux_clk_src", 1171 .parent_data = gcc_parent_data_4, 1172 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1173 .flags = CLK_SET_RATE_PARENT, 1174 .ops = &clk_rcg2_shared_no_init_park_ops, 1175 }, 1176 }; 1177 1178 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 1179 .cmd_rcgr = 0x770a4, 1180 .mnd_width = 0, 1181 .hid_width = 5, 1182 .parent_map = gcc_parent_map_3, 1183 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1184 .clkr.hw.init = &(const struct clk_init_data) { 1185 .name = "gcc_ufs_phy_unipro_core_clk_src", 1186 .parent_data = gcc_parent_data_3, 1187 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1188 .flags = CLK_SET_RATE_PARENT, 1189 .ops = &clk_rcg2_shared_no_init_park_ops, 1190 }, 1191 }; 1192 1193 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1194 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1195 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1196 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1197 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1198 { } 1199 }; 1200 1201 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1202 .cmd_rcgr = 0x39034, 1203 .mnd_width = 8, 1204 .hid_width = 5, 1205 .parent_map = gcc_parent_map_0, 1206 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1207 .clkr.hw.init = &(const struct clk_init_data) { 1208 .name = "gcc_usb30_prim_master_clk_src", 1209 .parent_data = gcc_parent_data_0, 1210 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1211 .flags = CLK_SET_RATE_PARENT, 1212 .ops = &clk_rcg2_shared_no_init_park_ops, 1213 }, 1214 }; 1215 1216 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1217 .cmd_rcgr = 0x3904c, 1218 .mnd_width = 0, 1219 .hid_width = 5, 1220 .parent_map = gcc_parent_map_0, 1221 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1222 .clkr.hw.init = &(const struct clk_init_data) { 1223 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1224 .parent_data = gcc_parent_data_0, 1225 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1226 .flags = CLK_SET_RATE_PARENT, 1227 .ops = &clk_rcg2_shared_no_init_park_ops, 1228 }, 1229 }; 1230 1231 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1232 .cmd_rcgr = 0x39078, 1233 .mnd_width = 0, 1234 .hid_width = 5, 1235 .parent_map = gcc_parent_map_6, 1236 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1237 .clkr.hw.init = &(const struct clk_init_data) { 1238 .name = "gcc_usb3_prim_phy_aux_clk_src", 1239 .parent_data = gcc_parent_data_6, 1240 .num_parents = ARRAY_SIZE(gcc_parent_data_6), 1241 .flags = CLK_SET_RATE_PARENT, 1242 .ops = &clk_rcg2_shared_no_init_park_ops, 1243 }, 1244 }; 1245 1246 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 1247 .reg = 0x1828c, 1248 .shift = 0, 1249 .width = 4, 1250 .clkr.hw.init = &(const struct clk_init_data) { 1251 .name = "gcc_qupv3_wrap1_s2_clk_src", 1252 .parent_hws = (const struct clk_hw*[]) { 1253 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1254 }, 1255 .num_parents = 1, 1256 .flags = CLK_SET_RATE_PARENT, 1257 .ops = &clk_regmap_div_ro_ops, 1258 }, 1259 }; 1260 1261 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1262 .reg = 0x39064, 1263 .shift = 0, 1264 .width = 4, 1265 .clkr.hw.init = &(const struct clk_init_data) { 1266 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1267 .parent_hws = (const struct clk_hw*[]) { 1268 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1269 }, 1270 .num_parents = 1, 1271 .flags = CLK_SET_RATE_PARENT, 1272 .ops = &clk_regmap_div_ro_ops, 1273 }, 1274 }; 1275 1276 static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1277 .halt_reg = 0x10068, 1278 .halt_check = BRANCH_HALT_SKIP, 1279 .hwcg_reg = 0x10068, 1280 .hwcg_bit = 1, 1281 .clkr = { 1282 .enable_reg = 0x52000, 1283 .enable_mask = BIT(12), 1284 .hw.init = &(const struct clk_init_data) { 1285 .name = "gcc_aggre_noc_pcie_axi_clk", 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1292 .halt_reg = 0x770f0, 1293 .halt_check = BRANCH_HALT_VOTED, 1294 .hwcg_reg = 0x770f0, 1295 .hwcg_bit = 1, 1296 .clkr = { 1297 .enable_reg = 0x770f0, 1298 .enable_mask = BIT(0), 1299 .hw.init = &(const struct clk_init_data) { 1300 .name = "gcc_aggre_ufs_phy_axi_clk", 1301 .parent_hws = (const struct clk_hw*[]) { 1302 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1303 }, 1304 .num_parents = 1, 1305 .flags = CLK_SET_RATE_PARENT, 1306 .ops = &clk_branch2_ops, 1307 }, 1308 }, 1309 }; 1310 1311 static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { 1312 .halt_reg = 0x39094, 1313 .halt_check = BRANCH_HALT_VOTED, 1314 .hwcg_reg = 0x39094, 1315 .hwcg_bit = 1, 1316 .clkr = { 1317 .enable_reg = 0x39094, 1318 .enable_mask = BIT(0), 1319 .hw.init = &(const struct clk_init_data) { 1320 .name = "gcc_aggre_usb3_prim_axi_clk", 1321 .parent_hws = (const struct clk_hw*[]) { 1322 &gcc_usb30_prim_master_clk_src.clkr.hw, 1323 }, 1324 .num_parents = 1, 1325 .flags = CLK_SET_RATE_PARENT, 1326 .ops = &clk_branch2_ops, 1327 }, 1328 }, 1329 }; 1330 1331 static struct clk_branch gcc_boot_rom_ahb_clk = { 1332 .halt_reg = 0x38004, 1333 .halt_check = BRANCH_HALT_VOTED, 1334 .hwcg_reg = 0x38004, 1335 .hwcg_bit = 1, 1336 .clkr = { 1337 .enable_reg = 0x52010, 1338 .enable_mask = BIT(18), 1339 .hw.init = &(const struct clk_init_data) { 1340 .name = "gcc_boot_rom_ahb_clk", 1341 .ops = &clk_branch2_ops, 1342 }, 1343 }, 1344 }; 1345 1346 static struct clk_branch gcc_camera_hf_axi_clk = { 1347 .halt_reg = 0x26014, 1348 .halt_check = BRANCH_HALT_SKIP, 1349 .hwcg_reg = 0x26014, 1350 .hwcg_bit = 1, 1351 .clkr = { 1352 .enable_reg = 0x26014, 1353 .enable_mask = BIT(0), 1354 .hw.init = &(const struct clk_init_data) { 1355 .name = "gcc_camera_hf_axi_clk", 1356 .ops = &clk_branch2_ops, 1357 }, 1358 }, 1359 }; 1360 1361 static struct clk_branch gcc_camera_sf_axi_clk = { 1362 .halt_reg = 0x26028, 1363 .halt_check = BRANCH_HALT_SKIP, 1364 .hwcg_reg = 0x26028, 1365 .hwcg_bit = 1, 1366 .clkr = { 1367 .enable_reg = 0x26028, 1368 .enable_mask = BIT(0), 1369 .hw.init = &(const struct clk_init_data) { 1370 .name = "gcc_camera_sf_axi_clk", 1371 .ops = &clk_branch2_ops, 1372 }, 1373 }, 1374 }; 1375 1376 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1377 .halt_reg = 0x10050, 1378 .halt_check = BRANCH_HALT_SKIP, 1379 .hwcg_reg = 0x10050, 1380 .hwcg_bit = 1, 1381 .clkr = { 1382 .enable_reg = 0x52000, 1383 .enable_mask = BIT(20), 1384 .hw.init = &(const struct clk_init_data) { 1385 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1386 .ops = &clk_branch2_ops, 1387 }, 1388 }, 1389 }; 1390 1391 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1392 .halt_reg = 0x39090, 1393 .halt_check = BRANCH_HALT_VOTED, 1394 .hwcg_reg = 0x39090, 1395 .hwcg_bit = 1, 1396 .clkr = { 1397 .enable_reg = 0x39090, 1398 .enable_mask = BIT(0), 1399 .hw.init = &(const struct clk_init_data) { 1400 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1401 .parent_hws = (const struct clk_hw*[]) { 1402 &gcc_usb30_prim_master_clk_src.clkr.hw, 1403 }, 1404 .num_parents = 1, 1405 .flags = CLK_SET_RATE_PARENT, 1406 .ops = &clk_branch2_ops, 1407 }, 1408 }, 1409 }; 1410 1411 static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1412 .halt_reg = 0x10058, 1413 .halt_check = BRANCH_HALT_VOTED, 1414 .clkr = { 1415 .enable_reg = 0x52008, 1416 .enable_mask = BIT(6), 1417 .hw.init = &(const struct clk_init_data) { 1418 .name = "gcc_cnoc_pcie_sf_axi_clk", 1419 .ops = &clk_branch2_ops, 1420 }, 1421 }, 1422 }; 1423 1424 static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = { 1425 .halt_reg = 0x1007c, 1426 .halt_check = BRANCH_HALT_SKIP, 1427 .hwcg_reg = 0x1007c, 1428 .hwcg_bit = 1, 1429 .clkr = { 1430 .enable_reg = 0x52000, 1431 .enable_mask = BIT(19), 1432 .hw.init = &(const struct clk_init_data) { 1433 .name = "gcc_ddrss_pcie_sf_qtb_clk", 1434 .ops = &clk_branch2_ops, 1435 }, 1436 }, 1437 }; 1438 1439 static struct clk_branch gcc_disp_hf_axi_clk = { 1440 .halt_reg = 0x2701c, 1441 .halt_check = BRANCH_HALT_SKIP, 1442 .clkr = { 1443 .enable_reg = 0x2701c, 1444 .enable_mask = BIT(0), 1445 .hw.init = &(const struct clk_init_data) { 1446 .name = "gcc_disp_hf_axi_clk", 1447 .ops = &clk_branch2_ops, 1448 }, 1449 }, 1450 }; 1451 1452 static struct clk_branch gcc_disp_sf_axi_clk = { 1453 .halt_reg = 0x27008, 1454 .halt_check = BRANCH_HALT_SKIP, 1455 .hwcg_reg = 0x27008, 1456 .hwcg_bit = 1, 1457 .clkr = { 1458 .enable_reg = 0x27008, 1459 .enable_mask = BIT(0), 1460 .hw.init = &(const struct clk_init_data) { 1461 .name = "gcc_disp_sf_axi_clk", 1462 .ops = &clk_branch2_aon_ops, 1463 }, 1464 }, 1465 }; 1466 1467 static struct clk_branch gcc_eva_axi0_clk = { 1468 .halt_reg = 0x9f008, 1469 .halt_check = BRANCH_HALT_SKIP, 1470 .hwcg_reg = 0x9f008, 1471 .hwcg_bit = 1, 1472 .clkr = { 1473 .enable_reg = 0x9f008, 1474 .enable_mask = BIT(0), 1475 .hw.init = &(const struct clk_init_data) { 1476 .name = "gcc_eva_axi0_clk", 1477 .ops = &clk_branch2_ops, 1478 }, 1479 }, 1480 }; 1481 1482 static struct clk_branch gcc_eva_axi0c_clk = { 1483 .halt_reg = 0x9f01c, 1484 .halt_check = BRANCH_HALT_SKIP, 1485 .hwcg_reg = 0x9f01c, 1486 .hwcg_bit = 1, 1487 .clkr = { 1488 .enable_reg = 0x9f01c, 1489 .enable_mask = BIT(0), 1490 .hw.init = &(const struct clk_init_data) { 1491 .name = "gcc_eva_axi0c_clk", 1492 .ops = &clk_branch2_ops, 1493 }, 1494 }, 1495 }; 1496 1497 static struct clk_branch gcc_gp1_clk = { 1498 .halt_reg = 0x64000, 1499 .halt_check = BRANCH_HALT, 1500 .clkr = { 1501 .enable_reg = 0x64000, 1502 .enable_mask = BIT(0), 1503 .hw.init = &(const struct clk_init_data) { 1504 .name = "gcc_gp1_clk", 1505 .parent_hws = (const struct clk_hw*[]) { 1506 &gcc_gp1_clk_src.clkr.hw, 1507 }, 1508 .num_parents = 1, 1509 .flags = CLK_SET_RATE_PARENT, 1510 .ops = &clk_branch2_ops, 1511 }, 1512 }, 1513 }; 1514 1515 static struct clk_branch gcc_gp2_clk = { 1516 .halt_reg = 0x65000, 1517 .halt_check = BRANCH_HALT, 1518 .clkr = { 1519 .enable_reg = 0x65000, 1520 .enable_mask = BIT(0), 1521 .hw.init = &(const struct clk_init_data) { 1522 .name = "gcc_gp2_clk", 1523 .parent_hws = (const struct clk_hw*[]) { 1524 &gcc_gp2_clk_src.clkr.hw, 1525 }, 1526 .num_parents = 1, 1527 .flags = CLK_SET_RATE_PARENT, 1528 .ops = &clk_branch2_ops, 1529 }, 1530 }, 1531 }; 1532 1533 static struct clk_branch gcc_gp3_clk = { 1534 .halt_reg = 0x66000, 1535 .halt_check = BRANCH_HALT, 1536 .clkr = { 1537 .enable_reg = 0x66000, 1538 .enable_mask = BIT(0), 1539 .hw.init = &(const struct clk_init_data) { 1540 .name = "gcc_gp3_clk", 1541 .parent_hws = (const struct clk_hw*[]) { 1542 &gcc_gp3_clk_src.clkr.hw, 1543 }, 1544 .num_parents = 1, 1545 .flags = CLK_SET_RATE_PARENT, 1546 .ops = &clk_branch2_ops, 1547 }, 1548 }, 1549 }; 1550 1551 static struct clk_branch gcc_gpu_gemnoc_gfx_clk = { 1552 .halt_reg = 0x71010, 1553 .halt_check = BRANCH_HALT_VOTED, 1554 .hwcg_reg = 0x71010, 1555 .hwcg_bit = 1, 1556 .clkr = { 1557 .enable_reg = 0x71010, 1558 .enable_mask = BIT(0), 1559 .hw.init = &(const struct clk_init_data) { 1560 .name = "gcc_gpu_gemnoc_gfx_clk", 1561 .ops = &clk_branch2_ops, 1562 }, 1563 }, 1564 }; 1565 1566 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1567 .halt_check = BRANCH_HALT_DELAY, 1568 .clkr = { 1569 .enable_reg = 0x52000, 1570 .enable_mask = BIT(15), 1571 .hw.init = &(const struct clk_init_data) { 1572 .name = "gcc_gpu_gpll0_clk_src", 1573 .parent_hws = (const struct clk_hw*[]) { 1574 &gcc_gpll0.clkr.hw, 1575 }, 1576 .num_parents = 1, 1577 .flags = CLK_SET_RATE_PARENT, 1578 .ops = &clk_branch2_ops, 1579 }, 1580 }, 1581 }; 1582 1583 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1584 .halt_check = BRANCH_HALT_DELAY, 1585 .clkr = { 1586 .enable_reg = 0x52000, 1587 .enable_mask = BIT(16), 1588 .hw.init = &(const struct clk_init_data) { 1589 .name = "gcc_gpu_gpll0_div_clk_src", 1590 .parent_hws = (const struct clk_hw*[]) { 1591 &gcc_gpll0_out_even.clkr.hw, 1592 }, 1593 .num_parents = 1, 1594 .flags = CLK_SET_RATE_PARENT, 1595 .ops = &clk_branch2_ops, 1596 }, 1597 }, 1598 }; 1599 1600 static struct clk_branch gcc_pcie_0_aux_clk = { 1601 .halt_reg = 0x6b044, 1602 .halt_check = BRANCH_HALT_VOTED, 1603 .clkr = { 1604 .enable_reg = 0x52008, 1605 .enable_mask = BIT(3), 1606 .hw.init = &(const struct clk_init_data) { 1607 .name = "gcc_pcie_0_aux_clk", 1608 .parent_hws = (const struct clk_hw*[]) { 1609 &gcc_pcie_0_aux_clk_src.clkr.hw, 1610 }, 1611 .num_parents = 1, 1612 .flags = CLK_SET_RATE_PARENT, 1613 .ops = &clk_branch2_ops, 1614 }, 1615 }, 1616 }; 1617 1618 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1619 .halt_reg = 0x6b040, 1620 .halt_check = BRANCH_HALT_VOTED, 1621 .hwcg_reg = 0x6b040, 1622 .hwcg_bit = 1, 1623 .clkr = { 1624 .enable_reg = 0x52008, 1625 .enable_mask = BIT(2), 1626 .hw.init = &(const struct clk_init_data) { 1627 .name = "gcc_pcie_0_cfg_ahb_clk", 1628 .ops = &clk_branch2_ops, 1629 }, 1630 }, 1631 }; 1632 1633 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1634 .halt_reg = 0x6b030, 1635 .halt_check = BRANCH_HALT_SKIP, 1636 .hwcg_reg = 0x6b030, 1637 .hwcg_bit = 1, 1638 .clkr = { 1639 .enable_reg = 0x52008, 1640 .enable_mask = BIT(1), 1641 .hw.init = &(const struct clk_init_data) { 1642 .name = "gcc_pcie_0_mstr_axi_clk", 1643 .ops = &clk_branch2_ops, 1644 }, 1645 }, 1646 }; 1647 1648 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1649 .halt_reg = 0x6b054, 1650 .halt_check = BRANCH_HALT_VOTED, 1651 .clkr = { 1652 .enable_reg = 0x52018, 1653 .enable_mask = BIT(31), 1654 .hw.init = &(const struct clk_init_data) { 1655 .name = "gcc_pcie_0_phy_aux_clk", 1656 .parent_hws = (const struct clk_hw*[]) { 1657 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1658 }, 1659 .num_parents = 1, 1660 .flags = CLK_SET_RATE_PARENT, 1661 .ops = &clk_branch2_ops, 1662 }, 1663 }, 1664 }; 1665 1666 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1667 .halt_reg = 0x6b074, 1668 .halt_check = BRANCH_HALT_VOTED, 1669 .clkr = { 1670 .enable_reg = 0x52000, 1671 .enable_mask = BIT(22), 1672 .hw.init = &(const struct clk_init_data) { 1673 .name = "gcc_pcie_0_phy_rchng_clk", 1674 .parent_hws = (const struct clk_hw*[]) { 1675 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1676 }, 1677 .num_parents = 1, 1678 .flags = CLK_SET_RATE_PARENT, 1679 .ops = &clk_branch2_ops, 1680 }, 1681 }, 1682 }; 1683 1684 static struct clk_branch gcc_pcie_0_pipe_clk = { 1685 .halt_reg = 0x6b064, 1686 .halt_check = BRANCH_HALT_SKIP, 1687 .clkr = { 1688 .enable_reg = 0x52008, 1689 .enable_mask = BIT(4), 1690 .hw.init = &(const struct clk_init_data) { 1691 .name = "gcc_pcie_0_pipe_clk", 1692 .parent_hws = (const struct clk_hw*[]) { 1693 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1694 }, 1695 .num_parents = 1, 1696 .flags = CLK_SET_RATE_PARENT, 1697 .ops = &clk_branch2_ops, 1698 }, 1699 }, 1700 }; 1701 1702 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1703 .halt_reg = 0x6b020, 1704 .halt_check = BRANCH_HALT_VOTED, 1705 .hwcg_reg = 0x6b020, 1706 .hwcg_bit = 1, 1707 .clkr = { 1708 .enable_reg = 0x52008, 1709 .enable_mask = BIT(0), 1710 .hw.init = &(const struct clk_init_data) { 1711 .name = "gcc_pcie_0_slv_axi_clk", 1712 .ops = &clk_branch2_ops, 1713 }, 1714 }, 1715 }; 1716 1717 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1718 .halt_reg = 0x6b01c, 1719 .halt_check = BRANCH_HALT_VOTED, 1720 .clkr = { 1721 .enable_reg = 0x52008, 1722 .enable_mask = BIT(5), 1723 .hw.init = &(const struct clk_init_data) { 1724 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728 }; 1729 1730 static struct clk_branch gcc_pdm2_clk = { 1731 .halt_reg = 0x3300c, 1732 .halt_check = BRANCH_HALT, 1733 .clkr = { 1734 .enable_reg = 0x3300c, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(const struct clk_init_data) { 1737 .name = "gcc_pdm2_clk", 1738 .parent_hws = (const struct clk_hw*[]) { 1739 &gcc_pdm2_clk_src.clkr.hw, 1740 }, 1741 .num_parents = 1, 1742 .flags = CLK_SET_RATE_PARENT, 1743 .ops = &clk_branch2_ops, 1744 }, 1745 }, 1746 }; 1747 1748 static struct clk_branch gcc_pdm_ahb_clk = { 1749 .halt_reg = 0x33004, 1750 .halt_check = BRANCH_HALT_VOTED, 1751 .hwcg_reg = 0x33004, 1752 .hwcg_bit = 1, 1753 .clkr = { 1754 .enable_reg = 0x33004, 1755 .enable_mask = BIT(0), 1756 .hw.init = &(const struct clk_init_data) { 1757 .name = "gcc_pdm_ahb_clk", 1758 .ops = &clk_branch2_ops, 1759 }, 1760 }, 1761 }; 1762 1763 static struct clk_branch gcc_pdm_xo4_clk = { 1764 .halt_reg = 0x33008, 1765 .halt_check = BRANCH_HALT, 1766 .clkr = { 1767 .enable_reg = 0x33008, 1768 .enable_mask = BIT(0), 1769 .hw.init = &(const struct clk_init_data) { 1770 .name = "gcc_pdm_xo4_clk", 1771 .ops = &clk_branch2_ops, 1772 }, 1773 }, 1774 }; 1775 1776 static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = { 1777 .halt_reg = 0x26010, 1778 .halt_check = BRANCH_HALT_VOTED, 1779 .hwcg_reg = 0x26010, 1780 .hwcg_bit = 1, 1781 .clkr = { 1782 .enable_reg = 0x26010, 1783 .enable_mask = BIT(0), 1784 .hw.init = &(const struct clk_init_data) { 1785 .name = "gcc_qmip_camera_cmd_ahb_clk", 1786 .ops = &clk_branch2_ops, 1787 }, 1788 }, 1789 }; 1790 1791 static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { 1792 .halt_reg = 0x26008, 1793 .halt_check = BRANCH_HALT_VOTED, 1794 .hwcg_reg = 0x26008, 1795 .hwcg_bit = 1, 1796 .clkr = { 1797 .enable_reg = 0x26008, 1798 .enable_mask = BIT(0), 1799 .hw.init = &(const struct clk_init_data) { 1800 .name = "gcc_qmip_camera_nrt_ahb_clk", 1801 .ops = &clk_branch2_ops, 1802 }, 1803 }, 1804 }; 1805 1806 static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { 1807 .halt_reg = 0x2600c, 1808 .halt_check = BRANCH_HALT_VOTED, 1809 .hwcg_reg = 0x2600c, 1810 .hwcg_bit = 1, 1811 .clkr = { 1812 .enable_reg = 0x2600c, 1813 .enable_mask = BIT(0), 1814 .hw.init = &(const struct clk_init_data) { 1815 .name = "gcc_qmip_camera_rt_ahb_clk", 1816 .ops = &clk_branch2_ops, 1817 }, 1818 }, 1819 }; 1820 1821 static struct clk_branch gcc_qmip_disp_dcp_sf_ahb_clk = { 1822 .halt_reg = 0x27030, 1823 .halt_check = BRANCH_HALT_VOTED, 1824 .hwcg_reg = 0x27030, 1825 .hwcg_bit = 1, 1826 .clkr = { 1827 .enable_reg = 0x27030, 1828 .enable_mask = BIT(0), 1829 .hw.init = &(const struct clk_init_data) { 1830 .name = "gcc_qmip_disp_dcp_sf_ahb_clk", 1831 .ops = &clk_branch2_ops, 1832 }, 1833 }, 1834 }; 1835 1836 static struct clk_branch gcc_qmip_gpu_ahb_clk = { 1837 .halt_reg = 0x71008, 1838 .halt_check = BRANCH_HALT_VOTED, 1839 .hwcg_reg = 0x71008, 1840 .hwcg_bit = 1, 1841 .clkr = { 1842 .enable_reg = 0x71008, 1843 .enable_mask = BIT(0), 1844 .hw.init = &(const struct clk_init_data) { 1845 .name = "gcc_qmip_gpu_ahb_clk", 1846 .ops = &clk_branch2_ops, 1847 }, 1848 }, 1849 }; 1850 1851 static struct clk_branch gcc_qmip_pcie_ahb_clk = { 1852 .halt_reg = 0x6b018, 1853 .halt_check = BRANCH_HALT_VOTED, 1854 .hwcg_reg = 0x6b018, 1855 .hwcg_bit = 1, 1856 .clkr = { 1857 .enable_reg = 0x52010, 1858 .enable_mask = BIT(19), 1859 .hw.init = &(const struct clk_init_data) { 1860 .name = "gcc_qmip_pcie_ahb_clk", 1861 .ops = &clk_branch2_ops, 1862 }, 1863 }, 1864 }; 1865 1866 static struct clk_branch gcc_qmip_video_cv_cpu_ahb_clk = { 1867 .halt_reg = 0x32014, 1868 .halt_check = BRANCH_HALT_VOTED, 1869 .hwcg_reg = 0x32014, 1870 .hwcg_bit = 1, 1871 .clkr = { 1872 .enable_reg = 0x32014, 1873 .enable_mask = BIT(0), 1874 .hw.init = &(const struct clk_init_data) { 1875 .name = "gcc_qmip_video_cv_cpu_ahb_clk", 1876 .ops = &clk_branch2_ops, 1877 }, 1878 }, 1879 }; 1880 1881 static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { 1882 .halt_reg = 0x32008, 1883 .halt_check = BRANCH_HALT_VOTED, 1884 .hwcg_reg = 0x32008, 1885 .hwcg_bit = 1, 1886 .clkr = { 1887 .enable_reg = 0x32008, 1888 .enable_mask = BIT(0), 1889 .hw.init = &(const struct clk_init_data) { 1890 .name = "gcc_qmip_video_cvp_ahb_clk", 1891 .ops = &clk_branch2_ops, 1892 }, 1893 }, 1894 }; 1895 1896 static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = { 1897 .halt_reg = 0x32010, 1898 .halt_check = BRANCH_HALT_VOTED, 1899 .hwcg_reg = 0x32010, 1900 .hwcg_bit = 1, 1901 .clkr = { 1902 .enable_reg = 0x32010, 1903 .enable_mask = BIT(0), 1904 .hw.init = &(const struct clk_init_data) { 1905 .name = "gcc_qmip_video_v_cpu_ahb_clk", 1906 .ops = &clk_branch2_ops, 1907 }, 1908 }, 1909 }; 1910 1911 static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { 1912 .halt_reg = 0x3200c, 1913 .halt_check = BRANCH_HALT_VOTED, 1914 .hwcg_reg = 0x3200c, 1915 .hwcg_bit = 1, 1916 .clkr = { 1917 .enable_reg = 0x3200c, 1918 .enable_mask = BIT(0), 1919 .hw.init = &(const struct clk_init_data) { 1920 .name = "gcc_qmip_video_vcodec_ahb_clk", 1921 .ops = &clk_branch2_ops, 1922 }, 1923 }, 1924 }; 1925 1926 static struct clk_branch gcc_qupv3_i2c_core_clk = { 1927 .halt_reg = 0x23004, 1928 .halt_check = BRANCH_HALT_VOTED, 1929 .clkr = { 1930 .enable_reg = 0x52008, 1931 .enable_mask = BIT(8), 1932 .hw.init = &(const struct clk_init_data) { 1933 .name = "gcc_qupv3_i2c_core_clk", 1934 .ops = &clk_branch2_ops, 1935 }, 1936 }, 1937 }; 1938 1939 static struct clk_branch gcc_qupv3_i2c_s0_clk = { 1940 .halt_reg = 0x17004, 1941 .halt_check = BRANCH_HALT_VOTED, 1942 .clkr = { 1943 .enable_reg = 0x52008, 1944 .enable_mask = BIT(10), 1945 .hw.init = &(const struct clk_init_data) { 1946 .name = "gcc_qupv3_i2c_s0_clk", 1947 .parent_hws = (const struct clk_hw*[]) { 1948 &gcc_qupv3_i2c_s0_clk_src.clkr.hw, 1949 }, 1950 .num_parents = 1, 1951 .flags = CLK_SET_RATE_PARENT, 1952 .ops = &clk_branch2_ops, 1953 }, 1954 }, 1955 }; 1956 1957 static struct clk_branch gcc_qupv3_i2c_s1_clk = { 1958 .halt_reg = 0x17020, 1959 .halt_check = BRANCH_HALT_VOTED, 1960 .clkr = { 1961 .enable_reg = 0x52008, 1962 .enable_mask = BIT(11), 1963 .hw.init = &(const struct clk_init_data) { 1964 .name = "gcc_qupv3_i2c_s1_clk", 1965 .parent_hws = (const struct clk_hw*[]) { 1966 &gcc_qupv3_i2c_s1_clk_src.clkr.hw, 1967 }, 1968 .num_parents = 1, 1969 .flags = CLK_SET_RATE_PARENT, 1970 .ops = &clk_branch2_ops, 1971 }, 1972 }, 1973 }; 1974 1975 static struct clk_branch gcc_qupv3_i2c_s2_clk = { 1976 .halt_reg = 0x1703c, 1977 .halt_check = BRANCH_HALT_VOTED, 1978 .clkr = { 1979 .enable_reg = 0x52008, 1980 .enable_mask = BIT(12), 1981 .hw.init = &(const struct clk_init_data) { 1982 .name = "gcc_qupv3_i2c_s2_clk", 1983 .parent_hws = (const struct clk_hw*[]) { 1984 &gcc_qupv3_i2c_s2_clk_src.clkr.hw, 1985 }, 1986 .num_parents = 1, 1987 .flags = CLK_SET_RATE_PARENT, 1988 .ops = &clk_branch2_ops, 1989 }, 1990 }, 1991 }; 1992 1993 static struct clk_branch gcc_qupv3_i2c_s3_clk = { 1994 .halt_reg = 0x17058, 1995 .halt_check = BRANCH_HALT_VOTED, 1996 .clkr = { 1997 .enable_reg = 0x52008, 1998 .enable_mask = BIT(13), 1999 .hw.init = &(const struct clk_init_data) { 2000 .name = "gcc_qupv3_i2c_s3_clk", 2001 .parent_hws = (const struct clk_hw*[]) { 2002 &gcc_qupv3_i2c_s3_clk_src.clkr.hw, 2003 }, 2004 .num_parents = 1, 2005 .flags = CLK_SET_RATE_PARENT, 2006 .ops = &clk_branch2_ops, 2007 }, 2008 }, 2009 }; 2010 2011 static struct clk_branch gcc_qupv3_i2c_s4_clk = { 2012 .halt_reg = 0x17074, 2013 .halt_check = BRANCH_HALT_VOTED, 2014 .clkr = { 2015 .enable_reg = 0x52008, 2016 .enable_mask = BIT(14), 2017 .hw.init = &(const struct clk_init_data) { 2018 .name = "gcc_qupv3_i2c_s4_clk", 2019 .parent_hws = (const struct clk_hw*[]) { 2020 &gcc_qupv3_i2c_s4_clk_src.clkr.hw, 2021 }, 2022 .num_parents = 1, 2023 .flags = CLK_SET_RATE_PARENT, 2024 .ops = &clk_branch2_ops, 2025 }, 2026 }, 2027 }; 2028 2029 static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = { 2030 .halt_reg = 0x23000, 2031 .halt_check = BRANCH_HALT_VOTED, 2032 .hwcg_reg = 0x23000, 2033 .hwcg_bit = 1, 2034 .clkr = { 2035 .enable_reg = 0x52008, 2036 .enable_mask = BIT(7), 2037 .hw.init = &(const struct clk_init_data) { 2038 .name = "gcc_qupv3_i2c_s_ahb_clk", 2039 .ops = &clk_branch2_ops, 2040 }, 2041 }, 2042 }; 2043 2044 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2045 .halt_reg = 0x2315c, 2046 .halt_check = BRANCH_HALT_VOTED, 2047 .clkr = { 2048 .enable_reg = 0x52008, 2049 .enable_mask = BIT(18), 2050 .hw.init = &(const struct clk_init_data) { 2051 .name = "gcc_qupv3_wrap1_core_2x_clk", 2052 .ops = &clk_branch2_ops, 2053 }, 2054 }, 2055 }; 2056 2057 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2058 .halt_reg = 0x23148, 2059 .halt_check = BRANCH_HALT_VOTED, 2060 .clkr = { 2061 .enable_reg = 0x52008, 2062 .enable_mask = BIT(19), 2063 .hw.init = &(const struct clk_init_data) { 2064 .name = "gcc_qupv3_wrap1_core_clk", 2065 .ops = &clk_branch2_ops, 2066 }, 2067 }, 2068 }; 2069 2070 static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = { 2071 .halt_reg = 0x188bc, 2072 .halt_check = BRANCH_HALT_VOTED, 2073 .clkr = { 2074 .enable_reg = 0x52010, 2075 .enable_mask = BIT(29), 2076 .hw.init = &(const struct clk_init_data) { 2077 .name = "gcc_qupv3_wrap1_qspi_ref_clk", 2078 .parent_hws = (const struct clk_hw*[]) { 2079 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 2080 }, 2081 .num_parents = 1, 2082 .flags = CLK_SET_RATE_PARENT, 2083 .ops = &clk_branch2_ops, 2084 }, 2085 }, 2086 }; 2087 2088 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2089 .halt_reg = 0x18004, 2090 .halt_check = BRANCH_HALT_VOTED, 2091 .clkr = { 2092 .enable_reg = 0x52008, 2093 .enable_mask = BIT(22), 2094 .hw.init = &(const struct clk_init_data) { 2095 .name = "gcc_qupv3_wrap1_s0_clk", 2096 .parent_hws = (const struct clk_hw*[]) { 2097 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2098 }, 2099 .num_parents = 1, 2100 .flags = CLK_SET_RATE_PARENT, 2101 .ops = &clk_branch2_ops, 2102 }, 2103 }, 2104 }; 2105 2106 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2107 .halt_reg = 0x18140, 2108 .halt_check = BRANCH_HALT_VOTED, 2109 .clkr = { 2110 .enable_reg = 0x52008, 2111 .enable_mask = BIT(23), 2112 .hw.init = &(const struct clk_init_data) { 2113 .name = "gcc_qupv3_wrap1_s1_clk", 2114 .parent_hws = (const struct clk_hw*[]) { 2115 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2116 }, 2117 .num_parents = 1, 2118 .flags = CLK_SET_RATE_PARENT, 2119 .ops = &clk_branch2_ops, 2120 }, 2121 }, 2122 }; 2123 2124 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2125 .halt_reg = 0x1827c, 2126 .halt_check = BRANCH_HALT_VOTED, 2127 .clkr = { 2128 .enable_reg = 0x52008, 2129 .enable_mask = BIT(24), 2130 .hw.init = &(const struct clk_init_data) { 2131 .name = "gcc_qupv3_wrap1_s2_clk", 2132 .parent_hws = (const struct clk_hw*[]) { 2133 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2134 }, 2135 .num_parents = 1, 2136 .flags = CLK_SET_RATE_PARENT, 2137 .ops = &clk_branch2_ops, 2138 }, 2139 }, 2140 }; 2141 2142 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2143 .halt_reg = 0x18290, 2144 .halt_check = BRANCH_HALT_VOTED, 2145 .clkr = { 2146 .enable_reg = 0x52008, 2147 .enable_mask = BIT(25), 2148 .hw.init = &(const struct clk_init_data) { 2149 .name = "gcc_qupv3_wrap1_s3_clk", 2150 .parent_hws = (const struct clk_hw*[]) { 2151 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2152 }, 2153 .num_parents = 1, 2154 .flags = CLK_SET_RATE_PARENT, 2155 .ops = &clk_branch2_ops, 2156 }, 2157 }, 2158 }; 2159 2160 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2161 .halt_reg = 0x183cc, 2162 .halt_check = BRANCH_HALT_VOTED, 2163 .clkr = { 2164 .enable_reg = 0x52008, 2165 .enable_mask = BIT(26), 2166 .hw.init = &(const struct clk_init_data) { 2167 .name = "gcc_qupv3_wrap1_s4_clk", 2168 .parent_hws = (const struct clk_hw*[]) { 2169 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2170 }, 2171 .num_parents = 1, 2172 .flags = CLK_SET_RATE_PARENT, 2173 .ops = &clk_branch2_ops, 2174 }, 2175 }, 2176 }; 2177 2178 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2179 .halt_reg = 0x18508, 2180 .halt_check = BRANCH_HALT_VOTED, 2181 .clkr = { 2182 .enable_reg = 0x52008, 2183 .enable_mask = BIT(27), 2184 .hw.init = &(const struct clk_init_data) { 2185 .name = "gcc_qupv3_wrap1_s5_clk", 2186 .parent_hws = (const struct clk_hw*[]) { 2187 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2188 }, 2189 .num_parents = 1, 2190 .flags = CLK_SET_RATE_PARENT, 2191 .ops = &clk_branch2_ops, 2192 }, 2193 }, 2194 }; 2195 2196 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2197 .halt_reg = 0x18644, 2198 .halt_check = BRANCH_HALT_VOTED, 2199 .clkr = { 2200 .enable_reg = 0x52008, 2201 .enable_mask = BIT(28), 2202 .hw.init = &(const struct clk_init_data) { 2203 .name = "gcc_qupv3_wrap1_s6_clk", 2204 .parent_hws = (const struct clk_hw*[]) { 2205 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2206 }, 2207 .num_parents = 1, 2208 .flags = CLK_SET_RATE_PARENT, 2209 .ops = &clk_branch2_ops, 2210 }, 2211 }, 2212 }; 2213 2214 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2215 .halt_reg = 0x18780, 2216 .halt_check = BRANCH_HALT_VOTED, 2217 .clkr = { 2218 .enable_reg = 0x52010, 2219 .enable_mask = BIT(16), 2220 .hw.init = &(const struct clk_init_data) { 2221 .name = "gcc_qupv3_wrap1_s7_clk", 2222 .parent_hws = (const struct clk_hw*[]) { 2223 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2224 }, 2225 .num_parents = 1, 2226 .flags = CLK_SET_RATE_PARENT, 2227 .ops = &clk_branch2_ops, 2228 }, 2229 }, 2230 }; 2231 2232 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2233 .halt_reg = 0x232b4, 2234 .halt_check = BRANCH_HALT_VOTED, 2235 .clkr = { 2236 .enable_reg = 0x52010, 2237 .enable_mask = BIT(3), 2238 .hw.init = &(const struct clk_init_data) { 2239 .name = "gcc_qupv3_wrap2_core_2x_clk", 2240 .ops = &clk_branch2_ops, 2241 }, 2242 }, 2243 }; 2244 2245 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2246 .halt_reg = 0x232a0, 2247 .halt_check = BRANCH_HALT_VOTED, 2248 .clkr = { 2249 .enable_reg = 0x52010, 2250 .enable_mask = BIT(0), 2251 .hw.init = &(const struct clk_init_data) { 2252 .name = "gcc_qupv3_wrap2_core_clk", 2253 .ops = &clk_branch2_ops, 2254 }, 2255 }, 2256 }; 2257 2258 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2259 .halt_reg = 0x1e004, 2260 .halt_check = BRANCH_HALT_VOTED, 2261 .clkr = { 2262 .enable_reg = 0x52010, 2263 .enable_mask = BIT(4), 2264 .hw.init = &(const struct clk_init_data) { 2265 .name = "gcc_qupv3_wrap2_s0_clk", 2266 .parent_hws = (const struct clk_hw*[]) { 2267 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2268 }, 2269 .num_parents = 1, 2270 .flags = CLK_SET_RATE_PARENT, 2271 .ops = &clk_branch2_ops, 2272 }, 2273 }, 2274 }; 2275 2276 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2277 .halt_reg = 0x1e140, 2278 .halt_check = BRANCH_HALT_VOTED, 2279 .clkr = { 2280 .enable_reg = 0x52010, 2281 .enable_mask = BIT(5), 2282 .hw.init = &(const struct clk_init_data) { 2283 .name = "gcc_qupv3_wrap2_s1_clk", 2284 .parent_hws = (const struct clk_hw*[]) { 2285 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2286 }, 2287 .num_parents = 1, 2288 .flags = CLK_SET_RATE_PARENT, 2289 .ops = &clk_branch2_ops, 2290 }, 2291 }, 2292 }; 2293 2294 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2295 .halt_reg = 0x1e27c, 2296 .halt_check = BRANCH_HALT_VOTED, 2297 .clkr = { 2298 .enable_reg = 0x52010, 2299 .enable_mask = BIT(6), 2300 .hw.init = &(const struct clk_init_data) { 2301 .name = "gcc_qupv3_wrap2_s2_clk", 2302 .parent_hws = (const struct clk_hw*[]) { 2303 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2304 }, 2305 .num_parents = 1, 2306 .flags = CLK_SET_RATE_PARENT, 2307 .ops = &clk_branch2_ops, 2308 }, 2309 }, 2310 }; 2311 2312 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2313 .halt_reg = 0x1e3b8, 2314 .halt_check = BRANCH_HALT_VOTED, 2315 .clkr = { 2316 .enable_reg = 0x52010, 2317 .enable_mask = BIT(7), 2318 .hw.init = &(const struct clk_init_data) { 2319 .name = "gcc_qupv3_wrap2_s3_clk", 2320 .parent_hws = (const struct clk_hw*[]) { 2321 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2322 }, 2323 .num_parents = 1, 2324 .flags = CLK_SET_RATE_PARENT, 2325 .ops = &clk_branch2_ops, 2326 }, 2327 }, 2328 }; 2329 2330 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2331 .halt_reg = 0x1e4f4, 2332 .halt_check = BRANCH_HALT_VOTED, 2333 .clkr = { 2334 .enable_reg = 0x52010, 2335 .enable_mask = BIT(8), 2336 .hw.init = &(const struct clk_init_data) { 2337 .name = "gcc_qupv3_wrap2_s4_clk", 2338 .parent_hws = (const struct clk_hw*[]) { 2339 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2340 }, 2341 .num_parents = 1, 2342 .flags = CLK_SET_RATE_PARENT, 2343 .ops = &clk_branch2_ops, 2344 }, 2345 }, 2346 }; 2347 2348 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { 2349 .halt_reg = 0x2340c, 2350 .halt_check = BRANCH_HALT_VOTED, 2351 .clkr = { 2352 .enable_reg = 0x52018, 2353 .enable_mask = BIT(11), 2354 .hw.init = &(const struct clk_init_data) { 2355 .name = "gcc_qupv3_wrap3_core_2x_clk", 2356 .ops = &clk_branch2_ops, 2357 }, 2358 }, 2359 }; 2360 2361 static struct clk_branch gcc_qupv3_wrap3_core_clk = { 2362 .halt_reg = 0x233f8, 2363 .halt_check = BRANCH_HALT_VOTED, 2364 .clkr = { 2365 .enable_reg = 0x52018, 2366 .enable_mask = BIT(10), 2367 .hw.init = &(const struct clk_init_data) { 2368 .name = "gcc_qupv3_wrap3_core_clk", 2369 .ops = &clk_branch2_ops, 2370 }, 2371 }, 2372 }; 2373 2374 static struct clk_branch gcc_qupv3_wrap3_ibi_ctrl_1_clk = { 2375 .halt_reg = 0xa8774, 2376 .halt_check = BRANCH_HALT_VOTED, 2377 .hwcg_reg = 0xa8774, 2378 .hwcg_bit = 1, 2379 .clkr = { 2380 .enable_reg = 0x52018, 2381 .enable_mask = BIT(20), 2382 .hw.init = &(const struct clk_init_data) { 2383 .name = "gcc_qupv3_wrap3_ibi_ctrl_1_clk", 2384 .parent_hws = (const struct clk_hw*[]) { 2385 &gcc_qupv3_wrap3_ibi_ctrl_0_clk_src.clkr.hw, 2386 }, 2387 .num_parents = 1, 2388 .flags = CLK_SET_RATE_PARENT, 2389 .ops = &clk_branch2_ops, 2390 }, 2391 }, 2392 }; 2393 2394 static struct clk_branch gcc_qupv3_wrap3_ibi_ctrl_2_clk = { 2395 .halt_reg = 0xa8778, 2396 .halt_check = BRANCH_HALT_VOTED, 2397 .hwcg_reg = 0xa8778, 2398 .hwcg_bit = 1, 2399 .clkr = { 2400 .enable_reg = 0x52018, 2401 .enable_mask = BIT(21), 2402 .hw.init = &(const struct clk_init_data) { 2403 .name = "gcc_qupv3_wrap3_ibi_ctrl_2_clk", 2404 .parent_hws = (const struct clk_hw*[]) { 2405 &gcc_qupv3_wrap3_ibi_ctrl_0_clk_src.clkr.hw, 2406 }, 2407 .num_parents = 1, 2408 .flags = CLK_SET_RATE_PARENT, 2409 .ops = &clk_branch2_ops, 2410 }, 2411 }, 2412 }; 2413 2414 static struct clk_branch gcc_qupv3_wrap3_s0_clk = { 2415 .halt_reg = 0xa8004, 2416 .halt_check = BRANCH_HALT_VOTED, 2417 .clkr = { 2418 .enable_reg = 0x52018, 2419 .enable_mask = BIT(12), 2420 .hw.init = &(const struct clk_init_data) { 2421 .name = "gcc_qupv3_wrap3_s0_clk", 2422 .parent_hws = (const struct clk_hw*[]) { 2423 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 2424 }, 2425 .num_parents = 1, 2426 .flags = CLK_SET_RATE_PARENT, 2427 .ops = &clk_branch2_ops, 2428 }, 2429 }, 2430 }; 2431 2432 static struct clk_branch gcc_qupv3_wrap3_s1_clk = { 2433 .halt_reg = 0xa8140, 2434 .halt_check = BRANCH_HALT_VOTED, 2435 .clkr = { 2436 .enable_reg = 0x52018, 2437 .enable_mask = BIT(13), 2438 .hw.init = &(const struct clk_init_data) { 2439 .name = "gcc_qupv3_wrap3_s1_clk", 2440 .parent_hws = (const struct clk_hw*[]) { 2441 &gcc_qupv3_wrap3_s1_clk_src.clkr.hw, 2442 }, 2443 .num_parents = 1, 2444 .flags = CLK_SET_RATE_PARENT, 2445 .ops = &clk_branch2_ops, 2446 }, 2447 }, 2448 }; 2449 2450 static struct clk_branch gcc_qupv3_wrap3_s2_clk = { 2451 .halt_reg = 0xa827c, 2452 .halt_check = BRANCH_HALT_VOTED, 2453 .clkr = { 2454 .enable_reg = 0x52018, 2455 .enable_mask = BIT(14), 2456 .hw.init = &(const struct clk_init_data) { 2457 .name = "gcc_qupv3_wrap3_s2_clk", 2458 .parent_hws = (const struct clk_hw*[]) { 2459 &gcc_qupv3_wrap3_s2_clk_src.clkr.hw, 2460 }, 2461 .num_parents = 1, 2462 .flags = CLK_SET_RATE_PARENT, 2463 .ops = &clk_branch2_ops, 2464 }, 2465 }, 2466 }; 2467 2468 static struct clk_branch gcc_qupv3_wrap3_s3_clk = { 2469 .halt_reg = 0xa83b8, 2470 .halt_check = BRANCH_HALT_VOTED, 2471 .clkr = { 2472 .enable_reg = 0x52018, 2473 .enable_mask = BIT(15), 2474 .hw.init = &(const struct clk_init_data) { 2475 .name = "gcc_qupv3_wrap3_s3_clk", 2476 .parent_hws = (const struct clk_hw*[]) { 2477 &gcc_qupv3_wrap3_s3_clk_src.clkr.hw, 2478 }, 2479 .num_parents = 1, 2480 .flags = CLK_SET_RATE_PARENT, 2481 .ops = &clk_branch2_ops, 2482 }, 2483 }, 2484 }; 2485 2486 static struct clk_branch gcc_qupv3_wrap3_s4_clk = { 2487 .halt_reg = 0xa84f4, 2488 .halt_check = BRANCH_HALT_VOTED, 2489 .clkr = { 2490 .enable_reg = 0x52018, 2491 .enable_mask = BIT(16), 2492 .hw.init = &(const struct clk_init_data) { 2493 .name = "gcc_qupv3_wrap3_s4_clk", 2494 .parent_hws = (const struct clk_hw*[]) { 2495 &gcc_qupv3_wrap3_s4_clk_src.clkr.hw, 2496 }, 2497 .num_parents = 1, 2498 .flags = CLK_SET_RATE_PARENT, 2499 .ops = &clk_branch2_ops, 2500 }, 2501 }, 2502 }; 2503 2504 static struct clk_branch gcc_qupv3_wrap3_s5_clk = { 2505 .halt_reg = 0xa8630, 2506 .halt_check = BRANCH_HALT_VOTED, 2507 .clkr = { 2508 .enable_reg = 0x52018, 2509 .enable_mask = BIT(17), 2510 .hw.init = &(const struct clk_init_data) { 2511 .name = "gcc_qupv3_wrap3_s5_clk", 2512 .parent_hws = (const struct clk_hw*[]) { 2513 &gcc_qupv3_wrap3_s5_clk_src.clkr.hw, 2514 }, 2515 .num_parents = 1, 2516 .flags = CLK_SET_RATE_PARENT, 2517 .ops = &clk_branch2_ops, 2518 }, 2519 }, 2520 }; 2521 2522 static struct clk_branch gcc_qupv3_wrap4_core_2x_clk = { 2523 .halt_reg = 0x23564, 2524 .halt_check = BRANCH_HALT_VOTED, 2525 .clkr = { 2526 .enable_reg = 0x52018, 2527 .enable_mask = BIT(25), 2528 .hw.init = &(const struct clk_init_data) { 2529 .name = "gcc_qupv3_wrap4_core_2x_clk", 2530 .ops = &clk_branch2_ops, 2531 }, 2532 }, 2533 }; 2534 2535 static struct clk_branch gcc_qupv3_wrap4_core_clk = { 2536 .halt_reg = 0x23550, 2537 .halt_check = BRANCH_HALT_VOTED, 2538 .clkr = { 2539 .enable_reg = 0x52018, 2540 .enable_mask = BIT(24), 2541 .hw.init = &(const struct clk_init_data) { 2542 .name = "gcc_qupv3_wrap4_core_clk", 2543 .ops = &clk_branch2_ops, 2544 }, 2545 }, 2546 }; 2547 2548 static struct clk_branch gcc_qupv3_wrap4_s0_clk = { 2549 .halt_reg = 0xa9004, 2550 .halt_check = BRANCH_HALT_VOTED, 2551 .clkr = { 2552 .enable_reg = 0x52018, 2553 .enable_mask = BIT(26), 2554 .hw.init = &(const struct clk_init_data) { 2555 .name = "gcc_qupv3_wrap4_s0_clk", 2556 .parent_hws = (const struct clk_hw*[]) { 2557 &gcc_qupv3_wrap4_s0_clk_src.clkr.hw, 2558 }, 2559 .num_parents = 1, 2560 .flags = CLK_SET_RATE_PARENT, 2561 .ops = &clk_branch2_ops, 2562 }, 2563 }, 2564 }; 2565 2566 static struct clk_branch gcc_qupv3_wrap4_s1_clk = { 2567 .halt_reg = 0xa9140, 2568 .halt_check = BRANCH_HALT_VOTED, 2569 .clkr = { 2570 .enable_reg = 0x52018, 2571 .enable_mask = BIT(27), 2572 .hw.init = &(const struct clk_init_data) { 2573 .name = "gcc_qupv3_wrap4_s1_clk", 2574 .parent_hws = (const struct clk_hw*[]) { 2575 &gcc_qupv3_wrap4_s1_clk_src.clkr.hw, 2576 }, 2577 .num_parents = 1, 2578 .flags = CLK_SET_RATE_PARENT, 2579 .ops = &clk_branch2_ops, 2580 }, 2581 }, 2582 }; 2583 2584 static struct clk_branch gcc_qupv3_wrap4_s2_clk = { 2585 .halt_reg = 0xa927c, 2586 .halt_check = BRANCH_HALT_VOTED, 2587 .clkr = { 2588 .enable_reg = 0x52018, 2589 .enable_mask = BIT(28), 2590 .hw.init = &(const struct clk_init_data) { 2591 .name = "gcc_qupv3_wrap4_s2_clk", 2592 .parent_hws = (const struct clk_hw*[]) { 2593 &gcc_qupv3_wrap4_s2_clk_src.clkr.hw, 2594 }, 2595 .num_parents = 1, 2596 .flags = CLK_SET_RATE_PARENT, 2597 .ops = &clk_branch2_ops, 2598 }, 2599 }, 2600 }; 2601 2602 static struct clk_branch gcc_qupv3_wrap4_s3_clk = { 2603 .halt_reg = 0xa93b8, 2604 .halt_check = BRANCH_HALT_VOTED, 2605 .clkr = { 2606 .enable_reg = 0x52018, 2607 .enable_mask = BIT(29), 2608 .hw.init = &(const struct clk_init_data) { 2609 .name = "gcc_qupv3_wrap4_s3_clk", 2610 .parent_hws = (const struct clk_hw*[]) { 2611 &gcc_qupv3_wrap4_s3_clk_src.clkr.hw, 2612 }, 2613 .num_parents = 1, 2614 .flags = CLK_SET_RATE_PARENT, 2615 .ops = &clk_branch2_ops, 2616 }, 2617 }, 2618 }; 2619 2620 static struct clk_branch gcc_qupv3_wrap4_s4_clk = { 2621 .halt_reg = 0xa94f4, 2622 .halt_check = BRANCH_HALT_VOTED, 2623 .clkr = { 2624 .enable_reg = 0x52018, 2625 .enable_mask = BIT(30), 2626 .hw.init = &(const struct clk_init_data) { 2627 .name = "gcc_qupv3_wrap4_s4_clk", 2628 .parent_hws = (const struct clk_hw*[]) { 2629 &gcc_qupv3_wrap4_s4_clk_src.clkr.hw, 2630 }, 2631 .num_parents = 1, 2632 .flags = CLK_SET_RATE_PARENT, 2633 .ops = &clk_branch2_ops, 2634 }, 2635 }, 2636 }; 2637 2638 static struct clk_branch gcc_qupv3_wrap_1_m_axi_clk = { 2639 .halt_reg = 0x23140, 2640 .halt_check = BRANCH_HALT_VOTED, 2641 .hwcg_reg = 0x23140, 2642 .hwcg_bit = 1, 2643 .clkr = { 2644 .enable_reg = 0x52008, 2645 .enable_mask = BIT(20), 2646 .hw.init = &(const struct clk_init_data) { 2647 .name = "gcc_qupv3_wrap_1_m_axi_clk", 2648 .ops = &clk_branch2_ops, 2649 }, 2650 }, 2651 }; 2652 2653 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2654 .halt_reg = 0x23144, 2655 .halt_check = BRANCH_HALT_VOTED, 2656 .hwcg_reg = 0x23144, 2657 .hwcg_bit = 1, 2658 .clkr = { 2659 .enable_reg = 0x52008, 2660 .enable_mask = BIT(21), 2661 .hw.init = &(const struct clk_init_data) { 2662 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2663 .ops = &clk_branch2_ops, 2664 }, 2665 }, 2666 }; 2667 2668 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2669 .halt_reg = 0x23298, 2670 .halt_check = BRANCH_HALT_VOTED, 2671 .hwcg_reg = 0x23298, 2672 .hwcg_bit = 1, 2673 .clkr = { 2674 .enable_reg = 0x52010, 2675 .enable_mask = BIT(2), 2676 .hw.init = &(const struct clk_init_data) { 2677 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2678 .ops = &clk_branch2_ops, 2679 }, 2680 }, 2681 }; 2682 2683 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2684 .halt_reg = 0x2329c, 2685 .halt_check = BRANCH_HALT_VOTED, 2686 .hwcg_reg = 0x2329c, 2687 .hwcg_bit = 1, 2688 .clkr = { 2689 .enable_reg = 0x52010, 2690 .enable_mask = BIT(1), 2691 .hw.init = &(const struct clk_init_data) { 2692 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2693 .ops = &clk_branch2_ops, 2694 }, 2695 }, 2696 }; 2697 2698 static struct clk_branch gcc_qupv3_wrap_3_ibi_1_ahb_clk = { 2699 .halt_reg = 0xa876c, 2700 .halt_check = BRANCH_HALT_VOTED, 2701 .hwcg_reg = 0xa876c, 2702 .hwcg_bit = 1, 2703 .clkr = { 2704 .enable_reg = 0x52018, 2705 .enable_mask = BIT(18), 2706 .hw.init = &(const struct clk_init_data) { 2707 .name = "gcc_qupv3_wrap_3_ibi_1_ahb_clk", 2708 .ops = &clk_branch2_ops, 2709 }, 2710 }, 2711 }; 2712 2713 static struct clk_branch gcc_qupv3_wrap_3_ibi_2_ahb_clk = { 2714 .halt_reg = 0xa8770, 2715 .halt_check = BRANCH_HALT_VOTED, 2716 .hwcg_reg = 0xa8770, 2717 .hwcg_bit = 1, 2718 .clkr = { 2719 .enable_reg = 0x52018, 2720 .enable_mask = BIT(19), 2721 .hw.init = &(const struct clk_init_data) { 2722 .name = "gcc_qupv3_wrap_3_ibi_2_ahb_clk", 2723 .ops = &clk_branch2_ops, 2724 }, 2725 }, 2726 }; 2727 2728 static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = { 2729 .halt_reg = 0x233f0, 2730 .halt_check = BRANCH_HALT_VOTED, 2731 .hwcg_reg = 0x233f0, 2732 .hwcg_bit = 1, 2733 .clkr = { 2734 .enable_reg = 0x52018, 2735 .enable_mask = BIT(8), 2736 .hw.init = &(const struct clk_init_data) { 2737 .name = "gcc_qupv3_wrap_3_m_ahb_clk", 2738 .ops = &clk_branch2_ops, 2739 }, 2740 }, 2741 }; 2742 2743 static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = { 2744 .halt_reg = 0x233f4, 2745 .halt_check = BRANCH_HALT_VOTED, 2746 .hwcg_reg = 0x233f4, 2747 .hwcg_bit = 1, 2748 .clkr = { 2749 .enable_reg = 0x52018, 2750 .enable_mask = BIT(9), 2751 .hw.init = &(const struct clk_init_data) { 2752 .name = "gcc_qupv3_wrap_3_s_ahb_clk", 2753 .ops = &clk_branch2_ops, 2754 }, 2755 }, 2756 }; 2757 2758 static struct clk_branch gcc_qupv3_wrap_4_m_ahb_clk = { 2759 .halt_reg = 0x23548, 2760 .halt_check = BRANCH_HALT_VOTED, 2761 .hwcg_reg = 0x23548, 2762 .hwcg_bit = 1, 2763 .clkr = { 2764 .enable_reg = 0x52018, 2765 .enable_mask = BIT(22), 2766 .hw.init = &(const struct clk_init_data) { 2767 .name = "gcc_qupv3_wrap_4_m_ahb_clk", 2768 .ops = &clk_branch2_ops, 2769 }, 2770 }, 2771 }; 2772 2773 static struct clk_branch gcc_qupv3_wrap_4_s_ahb_clk = { 2774 .halt_reg = 0x2354c, 2775 .halt_check = BRANCH_HALT_VOTED, 2776 .hwcg_reg = 0x2354c, 2777 .hwcg_bit = 1, 2778 .clkr = { 2779 .enable_reg = 0x52018, 2780 .enable_mask = BIT(23), 2781 .hw.init = &(const struct clk_init_data) { 2782 .name = "gcc_qupv3_wrap_4_s_ahb_clk", 2783 .ops = &clk_branch2_ops, 2784 }, 2785 }, 2786 }; 2787 2788 static struct clk_branch gcc_sdcc2_ahb_clk = { 2789 .halt_reg = 0x14014, 2790 .halt_check = BRANCH_HALT, 2791 .clkr = { 2792 .enable_reg = 0x14014, 2793 .enable_mask = BIT(0), 2794 .hw.init = &(const struct clk_init_data) { 2795 .name = "gcc_sdcc2_ahb_clk", 2796 .ops = &clk_branch2_ops, 2797 }, 2798 }, 2799 }; 2800 2801 static struct clk_branch gcc_sdcc2_apps_clk = { 2802 .halt_reg = 0x14004, 2803 .halt_check = BRANCH_HALT, 2804 .clkr = { 2805 .enable_reg = 0x14004, 2806 .enable_mask = BIT(0), 2807 .hw.init = &(const struct clk_init_data) { 2808 .name = "gcc_sdcc2_apps_clk", 2809 .parent_hws = (const struct clk_hw*[]) { 2810 &gcc_sdcc2_apps_clk_src.clkr.hw, 2811 }, 2812 .num_parents = 1, 2813 .flags = CLK_SET_RATE_PARENT, 2814 .ops = &clk_branch2_ops, 2815 }, 2816 }, 2817 }; 2818 2819 static struct clk_branch gcc_sdcc4_ahb_clk = { 2820 .halt_reg = 0x16014, 2821 .halt_check = BRANCH_HALT, 2822 .clkr = { 2823 .enable_reg = 0x16014, 2824 .enable_mask = BIT(0), 2825 .hw.init = &(const struct clk_init_data) { 2826 .name = "gcc_sdcc4_ahb_clk", 2827 .ops = &clk_branch2_ops, 2828 }, 2829 }, 2830 }; 2831 2832 static struct clk_branch gcc_sdcc4_apps_clk = { 2833 .halt_reg = 0x16004, 2834 .halt_check = BRANCH_HALT, 2835 .clkr = { 2836 .enable_reg = 0x16004, 2837 .enable_mask = BIT(0), 2838 .hw.init = &(const struct clk_init_data) { 2839 .name = "gcc_sdcc4_apps_clk", 2840 .parent_hws = (const struct clk_hw*[]) { 2841 &gcc_sdcc4_apps_clk_src.clkr.hw, 2842 }, 2843 .num_parents = 1, 2844 .flags = CLK_SET_RATE_PARENT, 2845 .ops = &clk_branch2_ops, 2846 }, 2847 }, 2848 }; 2849 2850 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2851 .halt_reg = 0x77028, 2852 .halt_check = BRANCH_HALT_VOTED, 2853 .hwcg_reg = 0x77028, 2854 .hwcg_bit = 1, 2855 .clkr = { 2856 .enable_reg = 0x77028, 2857 .enable_mask = BIT(0), 2858 .hw.init = &(const struct clk_init_data) { 2859 .name = "gcc_ufs_phy_ahb_clk", 2860 .ops = &clk_branch2_ops, 2861 }, 2862 }, 2863 }; 2864 2865 static struct clk_branch gcc_ufs_phy_axi_clk = { 2866 .halt_reg = 0x77018, 2867 .halt_check = BRANCH_HALT_VOTED, 2868 .hwcg_reg = 0x77018, 2869 .hwcg_bit = 1, 2870 .clkr = { 2871 .enable_reg = 0x77018, 2872 .enable_mask = BIT(0), 2873 .hw.init = &(const struct clk_init_data) { 2874 .name = "gcc_ufs_phy_axi_clk", 2875 .parent_hws = (const struct clk_hw*[]) { 2876 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2877 }, 2878 .num_parents = 1, 2879 .flags = CLK_SET_RATE_PARENT, 2880 .ops = &clk_branch2_ops, 2881 }, 2882 }, 2883 }; 2884 2885 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2886 .halt_reg = 0x7707c, 2887 .halt_check = BRANCH_HALT_VOTED, 2888 .hwcg_reg = 0x7707c, 2889 .hwcg_bit = 1, 2890 .clkr = { 2891 .enable_reg = 0x7707c, 2892 .enable_mask = BIT(0), 2893 .hw.init = &(const struct clk_init_data) { 2894 .name = "gcc_ufs_phy_ice_core_clk", 2895 .parent_hws = (const struct clk_hw*[]) { 2896 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2897 }, 2898 .num_parents = 1, 2899 .flags = CLK_SET_RATE_PARENT, 2900 .ops = &clk_branch2_ops, 2901 }, 2902 }, 2903 }; 2904 2905 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2906 .halt_reg = 0x770bc, 2907 .halt_check = BRANCH_HALT_VOTED, 2908 .hwcg_reg = 0x770bc, 2909 .hwcg_bit = 1, 2910 .clkr = { 2911 .enable_reg = 0x770bc, 2912 .enable_mask = BIT(0), 2913 .hw.init = &(const struct clk_init_data) { 2914 .name = "gcc_ufs_phy_phy_aux_clk", 2915 .parent_hws = (const struct clk_hw*[]) { 2916 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2917 }, 2918 .num_parents = 1, 2919 .flags = CLK_SET_RATE_PARENT, 2920 .ops = &clk_branch2_ops, 2921 }, 2922 }, 2923 }; 2924 2925 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 2926 .halt_reg = 0x77030, 2927 .halt_check = BRANCH_HALT_DELAY, 2928 .clkr = { 2929 .enable_reg = 0x77030, 2930 .enable_mask = BIT(0), 2931 .hw.init = &(const struct clk_init_data) { 2932 .name = "gcc_ufs_phy_rx_symbol_0_clk", 2933 .parent_hws = (const struct clk_hw*[]) { 2934 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 2935 }, 2936 .num_parents = 1, 2937 .flags = CLK_SET_RATE_PARENT, 2938 .ops = &clk_branch2_ops, 2939 }, 2940 }, 2941 }; 2942 2943 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 2944 .halt_reg = 0x770d8, 2945 .halt_check = BRANCH_HALT_DELAY, 2946 .clkr = { 2947 .enable_reg = 0x770d8, 2948 .enable_mask = BIT(0), 2949 .hw.init = &(const struct clk_init_data) { 2950 .name = "gcc_ufs_phy_rx_symbol_1_clk", 2951 .parent_hws = (const struct clk_hw*[]) { 2952 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 2953 }, 2954 .num_parents = 1, 2955 .flags = CLK_SET_RATE_PARENT, 2956 .ops = &clk_branch2_ops, 2957 }, 2958 }, 2959 }; 2960 2961 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 2962 .halt_reg = 0x7702c, 2963 .halt_check = BRANCH_HALT_DELAY, 2964 .clkr = { 2965 .enable_reg = 0x7702c, 2966 .enable_mask = BIT(0), 2967 .hw.init = &(const struct clk_init_data) { 2968 .name = "gcc_ufs_phy_tx_symbol_0_clk", 2969 .parent_hws = (const struct clk_hw*[]) { 2970 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 2971 }, 2972 .num_parents = 1, 2973 .flags = CLK_SET_RATE_PARENT, 2974 .ops = &clk_branch2_ops, 2975 }, 2976 }, 2977 }; 2978 2979 static struct clk_branch gcc_ufs_phy_unipro_core_clk = { 2980 .halt_reg = 0x7706c, 2981 .halt_check = BRANCH_HALT_VOTED, 2982 .hwcg_reg = 0x7706c, 2983 .hwcg_bit = 1, 2984 .clkr = { 2985 .enable_reg = 0x7706c, 2986 .enable_mask = BIT(0), 2987 .hw.init = &(const struct clk_init_data) { 2988 .name = "gcc_ufs_phy_unipro_core_clk", 2989 .parent_hws = (const struct clk_hw*[]) { 2990 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, 2991 }, 2992 .num_parents = 1, 2993 .flags = CLK_SET_RATE_PARENT, 2994 .ops = &clk_branch2_ops, 2995 }, 2996 }, 2997 }; 2998 2999 static struct clk_branch gcc_usb30_prim_master_clk = { 3000 .halt_reg = 0x39018, 3001 .halt_check = BRANCH_HALT, 3002 .clkr = { 3003 .enable_reg = 0x39018, 3004 .enable_mask = BIT(0), 3005 .hw.init = &(const struct clk_init_data) { 3006 .name = "gcc_usb30_prim_master_clk", 3007 .parent_hws = (const struct clk_hw*[]) { 3008 &gcc_usb30_prim_master_clk_src.clkr.hw, 3009 }, 3010 .num_parents = 1, 3011 .flags = CLK_SET_RATE_PARENT, 3012 .ops = &clk_branch2_ops, 3013 }, 3014 }, 3015 }; 3016 3017 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3018 .halt_reg = 0x3902c, 3019 .halt_check = BRANCH_HALT, 3020 .clkr = { 3021 .enable_reg = 0x3902c, 3022 .enable_mask = BIT(0), 3023 .hw.init = &(const struct clk_init_data) { 3024 .name = "gcc_usb30_prim_mock_utmi_clk", 3025 .parent_hws = (const struct clk_hw*[]) { 3026 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3027 }, 3028 .num_parents = 1, 3029 .flags = CLK_SET_RATE_PARENT, 3030 .ops = &clk_branch2_ops, 3031 }, 3032 }, 3033 }; 3034 3035 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3036 .halt_reg = 0x39028, 3037 .halt_check = BRANCH_HALT, 3038 .clkr = { 3039 .enable_reg = 0x39028, 3040 .enable_mask = BIT(0), 3041 .hw.init = &(const struct clk_init_data) { 3042 .name = "gcc_usb30_prim_sleep_clk", 3043 .ops = &clk_branch2_ops, 3044 }, 3045 }, 3046 }; 3047 3048 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3049 .halt_reg = 0x39068, 3050 .halt_check = BRANCH_HALT, 3051 .clkr = { 3052 .enable_reg = 0x39068, 3053 .enable_mask = BIT(0), 3054 .hw.init = &(const struct clk_init_data) { 3055 .name = "gcc_usb3_prim_phy_aux_clk", 3056 .parent_hws = (const struct clk_hw*[]) { 3057 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3058 }, 3059 .num_parents = 1, 3060 .flags = CLK_SET_RATE_PARENT, 3061 .ops = &clk_branch2_ops, 3062 }, 3063 }, 3064 }; 3065 3066 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3067 .halt_reg = 0x3906c, 3068 .halt_check = BRANCH_HALT, 3069 .clkr = { 3070 .enable_reg = 0x3906c, 3071 .enable_mask = BIT(0), 3072 .hw.init = &(const struct clk_init_data) { 3073 .name = "gcc_usb3_prim_phy_com_aux_clk", 3074 .parent_hws = (const struct clk_hw*[]) { 3075 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3076 }, 3077 .num_parents = 1, 3078 .flags = CLK_SET_RATE_PARENT, 3079 .ops = &clk_branch2_ops, 3080 }, 3081 }, 3082 }; 3083 3084 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3085 .halt_reg = 0x39070, 3086 .halt_check = BRANCH_HALT_DELAY, 3087 .hwcg_reg = 0x39070, 3088 .hwcg_bit = 1, 3089 .clkr = { 3090 .enable_reg = 0x39070, 3091 .enable_mask = BIT(0), 3092 .hw.init = &(const struct clk_init_data) { 3093 .name = "gcc_usb3_prim_phy_pipe_clk", 3094 .parent_hws = (const struct clk_hw*[]) { 3095 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 3096 }, 3097 .num_parents = 1, 3098 .flags = CLK_SET_RATE_PARENT, 3099 .ops = &clk_branch2_ops, 3100 }, 3101 }, 3102 }; 3103 3104 static struct clk_branch gcc_video_axi0_clk = { 3105 .halt_reg = 0x32018, 3106 .halt_check = BRANCH_HALT_SKIP, 3107 .hwcg_reg = 0x32018, 3108 .hwcg_bit = 1, 3109 .clkr = { 3110 .enable_reg = 0x32018, 3111 .enable_mask = BIT(0), 3112 .hw.init = &(const struct clk_init_data) { 3113 .name = "gcc_video_axi0_clk", 3114 .ops = &clk_branch2_ops, 3115 }, 3116 }, 3117 }; 3118 3119 static struct clk_branch gcc_video_axi1_clk = { 3120 .halt_reg = 0x3202c, 3121 .halt_check = BRANCH_HALT_SKIP, 3122 .hwcg_reg = 0x3202c, 3123 .hwcg_bit = 1, 3124 .clkr = { 3125 .enable_reg = 0x3202c, 3126 .enable_mask = BIT(0), 3127 .hw.init = &(const struct clk_init_data) { 3128 .name = "gcc_video_axi1_clk", 3129 .ops = &clk_branch2_ops, 3130 }, 3131 }, 3132 }; 3133 3134 static struct gdsc gcc_pcie_0_gdsc = { 3135 .gdscr = 0x6b004, 3136 .en_rest_wait_val = 0x2, 3137 .en_few_wait_val = 0x2, 3138 .clk_dis_wait_val = 0xf, 3139 .collapse_ctrl = 0x5214c, 3140 .collapse_mask = BIT(0), 3141 .pd = { 3142 .name = "gcc_pcie_0_gdsc", 3143 }, 3144 .pwrsts = PWRSTS_OFF_ON, 3145 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3146 }; 3147 3148 static struct gdsc gcc_pcie_0_phy_gdsc = { 3149 .gdscr = 0x6c000, 3150 .en_rest_wait_val = 0x2, 3151 .en_few_wait_val = 0x2, 3152 .clk_dis_wait_val = 0x2, 3153 .collapse_ctrl = 0x5214c, 3154 .collapse_mask = BIT(2), 3155 .pd = { 3156 .name = "gcc_pcie_0_phy_gdsc", 3157 }, 3158 .pwrsts = PWRSTS_OFF_ON, 3159 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3160 }; 3161 3162 static struct gdsc gcc_ufs_mem_phy_gdsc = { 3163 .gdscr = 0x9e000, 3164 .en_rest_wait_val = 0x2, 3165 .en_few_wait_val = 0x2, 3166 .clk_dis_wait_val = 0x2, 3167 .pd = { 3168 .name = "gcc_ufs_mem_phy_gdsc", 3169 }, 3170 .pwrsts = PWRSTS_OFF_ON, 3171 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3172 }; 3173 3174 static struct gdsc gcc_ufs_phy_gdsc = { 3175 .gdscr = 0x77004, 3176 .en_rest_wait_val = 0x2, 3177 .en_few_wait_val = 0x2, 3178 .clk_dis_wait_val = 0xf, 3179 .pd = { 3180 .name = "gcc_ufs_phy_gdsc", 3181 }, 3182 .pwrsts = PWRSTS_OFF_ON, 3183 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3184 }; 3185 3186 static struct gdsc gcc_usb30_prim_gdsc = { 3187 .gdscr = 0x39004, 3188 .en_rest_wait_val = 0x2, 3189 .en_few_wait_val = 0x2, 3190 .clk_dis_wait_val = 0xf, 3191 .pd = { 3192 .name = "gcc_usb30_prim_gdsc", 3193 }, 3194 .pwrsts = PWRSTS_OFF_ON, 3195 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3196 }; 3197 3198 static struct gdsc gcc_usb3_phy_gdsc = { 3199 .gdscr = 0x50018, 3200 .en_rest_wait_val = 0x2, 3201 .en_few_wait_val = 0x2, 3202 .clk_dis_wait_val = 0x2, 3203 .pd = { 3204 .name = "gcc_usb3_phy_gdsc", 3205 }, 3206 .pwrsts = PWRSTS_OFF_ON, 3207 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3208 }; 3209 3210 static struct clk_regmap *gcc_kaanapali_clocks[] = { 3211 [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 3212 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3213 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr, 3214 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3215 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3216 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3217 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 3218 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3219 [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 3220 [GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr, 3221 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr, 3222 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr, 3223 [GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr, 3224 [GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr, 3225 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3226 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3227 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3228 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3229 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3230 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3231 [GCC_GPLL0] = &gcc_gpll0.clkr, 3232 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3233 [GCC_GPLL1] = &gcc_gpll1.clkr, 3234 [GCC_GPLL4] = &gcc_gpll4.clkr, 3235 [GCC_GPLL7] = &gcc_gpll7.clkr, 3236 [GCC_GPLL9] = &gcc_gpll9.clkr, 3237 [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr, 3238 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3239 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3240 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3241 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3242 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3243 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3244 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 3245 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 3246 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3247 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3248 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3249 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3250 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3251 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3252 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3253 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3254 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3255 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3256 [GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr, 3257 [GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr, 3258 [GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr, 3259 [GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr, 3260 [GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr, 3261 [GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr, 3262 [GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr, 3263 [GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr, 3264 [GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr, 3265 [GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr, 3266 [GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr, 3267 [GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr, 3268 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3269 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3270 [GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr, 3271 [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr, 3272 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3273 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3274 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3275 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3276 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3277 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3278 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3279 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3280 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3281 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3282 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3283 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3284 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3285 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3286 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3287 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3288 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3289 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3290 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3291 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3292 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3293 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3294 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3295 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3296 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3297 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3298 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3299 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3300 [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, 3301 [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, 3302 [GCC_QUPV3_WRAP3_IBI_CTRL_0_CLK_SRC] = &gcc_qupv3_wrap3_ibi_ctrl_0_clk_src.clkr, 3303 [GCC_QUPV3_WRAP3_IBI_CTRL_1_CLK] = &gcc_qupv3_wrap3_ibi_ctrl_1_clk.clkr, 3304 [GCC_QUPV3_WRAP3_IBI_CTRL_2_CLK] = &gcc_qupv3_wrap3_ibi_ctrl_2_clk.clkr, 3305 [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, 3306 [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, 3307 [GCC_QUPV3_WRAP3_S1_CLK] = &gcc_qupv3_wrap3_s1_clk.clkr, 3308 [GCC_QUPV3_WRAP3_S1_CLK_SRC] = &gcc_qupv3_wrap3_s1_clk_src.clkr, 3309 [GCC_QUPV3_WRAP3_S2_CLK] = &gcc_qupv3_wrap3_s2_clk.clkr, 3310 [GCC_QUPV3_WRAP3_S2_CLK_SRC] = &gcc_qupv3_wrap3_s2_clk_src.clkr, 3311 [GCC_QUPV3_WRAP3_S3_CLK] = &gcc_qupv3_wrap3_s3_clk.clkr, 3312 [GCC_QUPV3_WRAP3_S3_CLK_SRC] = &gcc_qupv3_wrap3_s3_clk_src.clkr, 3313 [GCC_QUPV3_WRAP3_S4_CLK] = &gcc_qupv3_wrap3_s4_clk.clkr, 3314 [GCC_QUPV3_WRAP3_S4_CLK_SRC] = &gcc_qupv3_wrap3_s4_clk_src.clkr, 3315 [GCC_QUPV3_WRAP3_S5_CLK] = &gcc_qupv3_wrap3_s5_clk.clkr, 3316 [GCC_QUPV3_WRAP3_S5_CLK_SRC] = &gcc_qupv3_wrap3_s5_clk_src.clkr, 3317 [GCC_QUPV3_WRAP4_CORE_2X_CLK] = &gcc_qupv3_wrap4_core_2x_clk.clkr, 3318 [GCC_QUPV3_WRAP4_CORE_CLK] = &gcc_qupv3_wrap4_core_clk.clkr, 3319 [GCC_QUPV3_WRAP4_S0_CLK] = &gcc_qupv3_wrap4_s0_clk.clkr, 3320 [GCC_QUPV3_WRAP4_S0_CLK_SRC] = &gcc_qupv3_wrap4_s0_clk_src.clkr, 3321 [GCC_QUPV3_WRAP4_S1_CLK] = &gcc_qupv3_wrap4_s1_clk.clkr, 3322 [GCC_QUPV3_WRAP4_S1_CLK_SRC] = &gcc_qupv3_wrap4_s1_clk_src.clkr, 3323 [GCC_QUPV3_WRAP4_S2_CLK] = &gcc_qupv3_wrap4_s2_clk.clkr, 3324 [GCC_QUPV3_WRAP4_S2_CLK_SRC] = &gcc_qupv3_wrap4_s2_clk_src.clkr, 3325 [GCC_QUPV3_WRAP4_S3_CLK] = &gcc_qupv3_wrap4_s3_clk.clkr, 3326 [GCC_QUPV3_WRAP4_S3_CLK_SRC] = &gcc_qupv3_wrap4_s3_clk_src.clkr, 3327 [GCC_QUPV3_WRAP4_S4_CLK] = &gcc_qupv3_wrap4_s4_clk.clkr, 3328 [GCC_QUPV3_WRAP4_S4_CLK_SRC] = &gcc_qupv3_wrap4_s4_clk_src.clkr, 3329 [GCC_QUPV3_WRAP_1_M_AXI_CLK] = &gcc_qupv3_wrap_1_m_axi_clk.clkr, 3330 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3331 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3332 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3333 [GCC_QUPV3_WRAP_3_IBI_1_AHB_CLK] = &gcc_qupv3_wrap_3_ibi_1_ahb_clk.clkr, 3334 [GCC_QUPV3_WRAP_3_IBI_2_AHB_CLK] = &gcc_qupv3_wrap_3_ibi_2_ahb_clk.clkr, 3335 [GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr, 3336 [GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr, 3337 [GCC_QUPV3_WRAP_4_M_AHB_CLK] = &gcc_qupv3_wrap_4_m_ahb_clk.clkr, 3338 [GCC_QUPV3_WRAP_4_S_AHB_CLK] = &gcc_qupv3_wrap_4_s_ahb_clk.clkr, 3339 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3340 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3341 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3342 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3343 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3344 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3345 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3346 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3347 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3348 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3349 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3350 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3351 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3352 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3353 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3354 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3355 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3356 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3357 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3358 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, 3359 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr, 3360 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3361 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3362 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3363 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3364 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3365 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3366 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3367 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3368 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3369 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3370 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3371 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3372 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, 3373 [GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr, 3374 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr, 3375 [GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr, 3376 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr, 3377 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr, 3378 [GCC_QMIP_DISP_DCP_SF_AHB_CLK] = &gcc_qmip_disp_dcp_sf_ahb_clk.clkr, 3379 [GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr, 3380 [GCC_QMIP_VIDEO_CV_CPU_AHB_CLK] = &gcc_qmip_video_cv_cpu_ahb_clk.clkr, 3381 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr, 3382 [GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr, 3383 }; 3384 3385 static struct gdsc *gcc_kaanapali_gdscs[] = { 3386 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, 3387 [GCC_PCIE_0_PHY_GDSC] = &gcc_pcie_0_phy_gdsc, 3388 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc, 3389 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3390 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3391 [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc, 3392 }; 3393 3394 static const struct qcom_reset_map gcc_kaanapali_resets[] = { 3395 [GCC_CAMERA_BCR] = { 0x26000 }, 3396 [GCC_DISPLAY_BCR] = { 0x27000 }, 3397 [GCC_EVA_AXI0_CLK_ARES] = { 0x9f008, 2 }, 3398 [GCC_EVA_AXI0C_CLK_ARES] = { 0x9f01c, 2 }, 3399 [GCC_EVA_BCR] = { 0x9f000 }, 3400 [GCC_GPU_BCR] = { 0x71000 }, 3401 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3402 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3403 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3404 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3405 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3406 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3407 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3408 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3409 [GCC_PCIE_RSCC_BCR] = { 0x11000 }, 3410 [GCC_PDM_BCR] = { 0x33000 }, 3411 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3412 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3413 [GCC_QUPV3_WRAPPER_3_BCR] = { 0xa8000 }, 3414 [GCC_QUPV3_WRAPPER_4_BCR] = { 0xa9000 }, 3415 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, 3416 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3417 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3418 [GCC_SDCC2_BCR] = { 0x14000 }, 3419 [GCC_SDCC4_BCR] = { 0x16000 }, 3420 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3421 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 3422 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3423 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3424 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3425 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3426 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3427 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3428 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3429 [GCC_VIDEO_AXI1_CLK_ARES] = { 0x3202c, 2 }, 3430 [GCC_VIDEO_BCR] = { 0x32000 }, 3431 [GCC_VIDEO_XO_CLK_ARES] = { 0x32040, 2 }, 3432 }; 3433 3434 static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { 3435 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src), 3436 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3437 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3438 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3439 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3440 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3441 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3442 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3443 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3444 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3445 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3446 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3447 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3448 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src), 3449 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s1_clk_src), 3450 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s2_clk_src), 3451 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s3_clk_src), 3452 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s4_clk_src), 3453 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s5_clk_src), 3454 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s0_clk_src), 3455 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s1_clk_src), 3456 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s2_clk_src), 3457 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s3_clk_src), 3458 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s4_clk_src), 3459 }; 3460 3461 static u32 gcc_kaanapali_critical_cbcrs[] = { 3462 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */ 3463 0x26004, /* GCC_CAMERA_AHB_CLK */ 3464 0x2603c, /* GCC_CAMERA_XO_CLK */ 3465 0x27004, /* GCC_DISP_AHB_CLK */ 3466 0x9f004, /* GCC_EVA_AHB_CLK */ 3467 0x9f024, /* GCC_EVA_XO_CLK */ 3468 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 3469 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ 3470 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ 3471 0x32004, /* GCC_VIDEO_AHB_CLK */ 3472 0x32040, /* GCC_VIDEO_XO_CLK */ 3473 }; 3474 3475 static const struct regmap_config gcc_kaanapali_regmap_config = { 3476 .reg_bits = 32, 3477 .reg_stride = 4, 3478 .val_bits = 32, 3479 .max_register = 0x1f41f0, 3480 .fast_io = true, 3481 }; 3482 3483 static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regmap) 3484 { 3485 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3486 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3487 } 3488 3489 static struct qcom_cc_driver_data gcc_kaanapali_driver_data = { 3490 .clk_cbcrs = gcc_kaanapali_critical_cbcrs, 3491 .num_clk_cbcrs = ARRAY_SIZE(gcc_kaanapali_critical_cbcrs), 3492 .dfs_rcgs = gcc_dfs_clocks, 3493 .num_dfs_rcgs = ARRAY_SIZE(gcc_dfs_clocks), 3494 .clk_regs_configure = clk_kaanapali_regs_configure, 3495 }; 3496 3497 static const struct qcom_cc_desc gcc_kaanapali_desc = { 3498 .config = &gcc_kaanapali_regmap_config, 3499 .clks = gcc_kaanapali_clocks, 3500 .num_clks = ARRAY_SIZE(gcc_kaanapali_clocks), 3501 .resets = gcc_kaanapali_resets, 3502 .num_resets = ARRAY_SIZE(gcc_kaanapali_resets), 3503 .gdscs = gcc_kaanapali_gdscs, 3504 .num_gdscs = ARRAY_SIZE(gcc_kaanapali_gdscs), 3505 .driver_data = &gcc_kaanapali_driver_data, 3506 }; 3507 3508 static const struct of_device_id gcc_kaanapali_match_table[] = { 3509 { .compatible = "qcom,kaanapali-gcc" }, 3510 { } 3511 }; 3512 MODULE_DEVICE_TABLE(of, gcc_kaanapali_match_table); 3513 3514 static int gcc_kaanapali_probe(struct platform_device *pdev) 3515 { 3516 return qcom_cc_probe(pdev, &gcc_kaanapali_desc); 3517 } 3518 3519 static struct platform_driver gcc_kaanapali_driver = { 3520 .probe = gcc_kaanapali_probe, 3521 .driver = { 3522 .name = "gcc-kaanapali", 3523 .of_match_table = gcc_kaanapali_match_table, 3524 }, 3525 }; 3526 3527 static int __init gcc_kaanapali_init(void) 3528 { 3529 return platform_driver_register(&gcc_kaanapali_driver); 3530 } 3531 subsys_initcall(gcc_kaanapali_init); 3532 3533 static void __exit gcc_kaanapali_exit(void) 3534 { 3535 platform_driver_unregister(&gcc_kaanapali_driver); 3536 } 3537 module_exit(gcc_kaanapali_exit); 3538 3539 MODULE_DESCRIPTION("QTI GCC Kaanapali Driver"); 3540 MODULE_LICENSE("GPL"); 3541