1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7 #include <linux/clk-provider.h> 8 #include <linux/mod_devicetable.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,milos-camcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 /* Need to match the order of clocks in DT binding */ 27 enum { 28 DT_BI_TCXO, 29 DT_SLEEP_CLK, 30 DT_IFACE, 31 }; 32 33 enum { 34 P_BI_TCXO, 35 P_CAM_CC_PLL0_OUT_EVEN, 36 P_CAM_CC_PLL0_OUT_MAIN, 37 P_CAM_CC_PLL0_OUT_ODD, 38 P_CAM_CC_PLL1_OUT_EVEN, 39 P_CAM_CC_PLL1_OUT_MAIN, 40 P_CAM_CC_PLL2_OUT_MAIN, 41 P_CAM_CC_PLL3_OUT_EVEN, 42 P_CAM_CC_PLL4_OUT_EVEN, 43 P_CAM_CC_PLL4_OUT_MAIN, 44 P_CAM_CC_PLL5_OUT_EVEN, 45 P_CAM_CC_PLL5_OUT_MAIN, 46 P_CAM_CC_PLL6_OUT_EVEN, 47 P_CAM_CC_PLL6_OUT_MAIN, 48 P_SLEEP_CLK, 49 }; 50 51 static const struct pll_vco lucid_ole_vco[] = { 52 { 249600000, 2300000000, 0 }, 53 }; 54 55 static const struct pll_vco rivian_ole_vco[] = { 56 { 777000000, 1285000000, 0 }, 57 }; 58 59 /* 1200.0 MHz Configuration */ 60 static const struct alpha_pll_config cam_cc_pll0_config = { 61 .l = 0x3e, 62 .alpha = 0x8000, 63 .config_ctl_val = 0x20485699, 64 .config_ctl_hi_val = 0x00182261, 65 .config_ctl_hi1_val = 0x82aa299c, 66 .test_ctl_val = 0x00000000, 67 .test_ctl_hi_val = 0x00000003, 68 .test_ctl_hi1_val = 0x00009000, 69 .test_ctl_hi2_val = 0x00000034, 70 .user_ctl_val = 0x00008400, 71 .user_ctl_hi_val = 0x00000005, 72 }; 73 74 static struct clk_alpha_pll cam_cc_pll0 = { 75 .offset = 0x0, 76 .config = &cam_cc_pll0_config, 77 .vco_table = lucid_ole_vco, 78 .num_vco = ARRAY_SIZE(lucid_ole_vco), 79 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 80 .clkr = { 81 .hw.init = &(const struct clk_init_data) { 82 .name = "cam_cc_pll0", 83 .parent_data = &(const struct clk_parent_data) { 84 .index = DT_BI_TCXO, 85 }, 86 .num_parents = 1, 87 .ops = &clk_alpha_pll_lucid_evo_ops, 88 }, 89 }, 90 }; 91 92 static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { 93 { 0x1, 2 }, 94 { } 95 }; 96 97 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { 98 .offset = 0x0, 99 .post_div_shift = 10, 100 .post_div_table = post_div_table_cam_cc_pll0_out_even, 101 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even), 102 .width = 4, 103 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 104 .clkr.hw.init = &(const struct clk_init_data) { 105 .name = "cam_cc_pll0_out_even", 106 .parent_hws = (const struct clk_hw*[]) { 107 &cam_cc_pll0.clkr.hw, 108 }, 109 .num_parents = 1, 110 .flags = CLK_SET_RATE_PARENT, 111 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 112 }, 113 }; 114 115 static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { 116 { 0x2, 3 }, 117 { } 118 }; 119 120 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 121 .offset = 0x0, 122 .post_div_shift = 14, 123 .post_div_table = post_div_table_cam_cc_pll0_out_odd, 124 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd), 125 .width = 4, 126 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 127 .clkr.hw.init = &(const struct clk_init_data) { 128 .name = "cam_cc_pll0_out_odd", 129 .parent_hws = (const struct clk_hw*[]) { 130 &cam_cc_pll0.clkr.hw, 131 }, 132 .num_parents = 1, 133 .flags = CLK_SET_RATE_PARENT, 134 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 135 }, 136 }; 137 138 /* 600.0 MHz Configuration */ 139 static const struct alpha_pll_config cam_cc_pll1_config = { 140 .l = 0x1f, 141 .alpha = 0x4000, 142 .config_ctl_val = 0x20485699, 143 .config_ctl_hi_val = 0x00182261, 144 .config_ctl_hi1_val = 0x82aa299c, 145 .test_ctl_val = 0x00000000, 146 .test_ctl_hi_val = 0x00000003, 147 .test_ctl_hi1_val = 0x00009000, 148 .test_ctl_hi2_val = 0x00000034, 149 .user_ctl_val = 0x00000400, 150 .user_ctl_hi_val = 0x00000005, 151 }; 152 153 static struct clk_alpha_pll cam_cc_pll1 = { 154 .offset = 0x1000, 155 .config = &cam_cc_pll1_config, 156 .vco_table = lucid_ole_vco, 157 .num_vco = ARRAY_SIZE(lucid_ole_vco), 158 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 159 .clkr = { 160 .hw.init = &(const struct clk_init_data) { 161 .name = "cam_cc_pll1", 162 .parent_data = &(const struct clk_parent_data) { 163 .index = DT_BI_TCXO, 164 }, 165 .num_parents = 1, 166 .ops = &clk_alpha_pll_lucid_evo_ops, 167 }, 168 }, 169 }; 170 171 static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { 172 { 0x1, 2 }, 173 { } 174 }; 175 176 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 177 .offset = 0x1000, 178 .post_div_shift = 10, 179 .post_div_table = post_div_table_cam_cc_pll1_out_even, 180 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even), 181 .width = 4, 182 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 183 .clkr.hw.init = &(const struct clk_init_data) { 184 .name = "cam_cc_pll1_out_even", 185 .parent_hws = (const struct clk_hw*[]) { 186 &cam_cc_pll1.clkr.hw, 187 }, 188 .num_parents = 1, 189 .flags = CLK_SET_RATE_PARENT, 190 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 191 }, 192 }; 193 194 /* 960.0 MHz Configuration */ 195 static const struct alpha_pll_config cam_cc_pll2_config = { 196 .l = 0x32, 197 .alpha = 0x0, 198 .config_ctl_val = 0x10000030, 199 .config_ctl_hi_val = 0x80890263, 200 .config_ctl_hi1_val = 0x00000217, 201 .user_ctl_val = 0x00000001, 202 .user_ctl_hi_val = 0x00100000, 203 }; 204 205 static struct clk_alpha_pll cam_cc_pll2 = { 206 .offset = 0x2000, 207 .config = &cam_cc_pll2_config, 208 .vco_table = rivian_ole_vco, 209 .num_vco = ARRAY_SIZE(rivian_ole_vco), 210 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], 211 .clkr = { 212 .hw.init = &(const struct clk_init_data) { 213 .name = "cam_cc_pll2", 214 .parent_data = &(const struct clk_parent_data) { 215 .index = DT_BI_TCXO, 216 }, 217 .num_parents = 1, 218 .ops = &clk_alpha_pll_rivian_evo_ops, 219 }, 220 }, 221 }; 222 223 /* 600.0 MHz Configuration */ 224 static const struct alpha_pll_config cam_cc_pll3_config = { 225 .l = 0x1f, 226 .alpha = 0x4000, 227 .config_ctl_val = 0x20485699, 228 .config_ctl_hi_val = 0x00182261, 229 .config_ctl_hi1_val = 0x82aa299c, 230 .test_ctl_val = 0x00000000, 231 .test_ctl_hi_val = 0x00000003, 232 .test_ctl_hi1_val = 0x00009000, 233 .test_ctl_hi2_val = 0x00000034, 234 .user_ctl_val = 0x00000400, 235 .user_ctl_hi_val = 0x00000005, 236 }; 237 238 static struct clk_alpha_pll cam_cc_pll3 = { 239 .offset = 0x3000, 240 .config = &cam_cc_pll3_config, 241 .vco_table = lucid_ole_vco, 242 .num_vco = ARRAY_SIZE(lucid_ole_vco), 243 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 244 .clkr = { 245 .hw.init = &(const struct clk_init_data) { 246 .name = "cam_cc_pll3", 247 .parent_data = &(const struct clk_parent_data) { 248 .index = DT_BI_TCXO, 249 }, 250 .num_parents = 1, 251 .ops = &clk_alpha_pll_lucid_evo_ops, 252 }, 253 }, 254 }; 255 256 static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { 257 { 0x1, 2 }, 258 { } 259 }; 260 261 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 262 .offset = 0x3000, 263 .post_div_shift = 10, 264 .post_div_table = post_div_table_cam_cc_pll3_out_even, 265 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even), 266 .width = 4, 267 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 268 .clkr.hw.init = &(const struct clk_init_data) { 269 .name = "cam_cc_pll3_out_even", 270 .parent_hws = (const struct clk_hw*[]) { 271 &cam_cc_pll3.clkr.hw, 272 }, 273 .num_parents = 1, 274 .flags = CLK_SET_RATE_PARENT, 275 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 276 }, 277 }; 278 279 /* 700.0 MHz Configuration */ 280 static const struct alpha_pll_config cam_cc_pll4_config = { 281 .l = 0x24, 282 .alpha = 0x7555, 283 .config_ctl_val = 0x20485699, 284 .config_ctl_hi_val = 0x00182261, 285 .config_ctl_hi1_val = 0x82aa299c, 286 .test_ctl_val = 0x00000000, 287 .test_ctl_hi_val = 0x00000003, 288 .test_ctl_hi1_val = 0x00009000, 289 .test_ctl_hi2_val = 0x00000034, 290 .user_ctl_val = 0x00000400, 291 .user_ctl_hi_val = 0x00000005, 292 }; 293 294 static struct clk_alpha_pll cam_cc_pll4 = { 295 .offset = 0x4000, 296 .config = &cam_cc_pll4_config, 297 .vco_table = lucid_ole_vco, 298 .num_vco = ARRAY_SIZE(lucid_ole_vco), 299 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 300 .clkr = { 301 .hw.init = &(const struct clk_init_data) { 302 .name = "cam_cc_pll4", 303 .parent_data = &(const struct clk_parent_data) { 304 .index = DT_BI_TCXO, 305 }, 306 .num_parents = 1, 307 .ops = &clk_alpha_pll_lucid_evo_ops, 308 }, 309 }, 310 }; 311 312 static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { 313 { 0x1, 2 }, 314 { } 315 }; 316 317 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 318 .offset = 0x4000, 319 .post_div_shift = 10, 320 .post_div_table = post_div_table_cam_cc_pll4_out_even, 321 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even), 322 .width = 4, 323 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 324 .clkr.hw.init = &(const struct clk_init_data) { 325 .name = "cam_cc_pll4_out_even", 326 .parent_hws = (const struct clk_hw*[]) { 327 &cam_cc_pll4.clkr.hw, 328 }, 329 .num_parents = 1, 330 .flags = CLK_SET_RATE_PARENT, 331 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 332 }, 333 }; 334 335 /* 700.0 MHz Configuration */ 336 static const struct alpha_pll_config cam_cc_pll5_config = { 337 .l = 0x24, 338 .alpha = 0x7555, 339 .config_ctl_val = 0x20485699, 340 .config_ctl_hi_val = 0x00182261, 341 .config_ctl_hi1_val = 0x82aa299c, 342 .test_ctl_val = 0x00000000, 343 .test_ctl_hi_val = 0x00000003, 344 .test_ctl_hi1_val = 0x00009000, 345 .test_ctl_hi2_val = 0x00000034, 346 .user_ctl_val = 0x00000400, 347 .user_ctl_hi_val = 0x00000005, 348 }; 349 350 static struct clk_alpha_pll cam_cc_pll5 = { 351 .offset = 0x5000, 352 .config = &cam_cc_pll5_config, 353 .vco_table = lucid_ole_vco, 354 .num_vco = ARRAY_SIZE(lucid_ole_vco), 355 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 356 .clkr = { 357 .hw.init = &(const struct clk_init_data) { 358 .name = "cam_cc_pll5", 359 .parent_data = &(const struct clk_parent_data) { 360 .index = DT_BI_TCXO, 361 }, 362 .num_parents = 1, 363 .ops = &clk_alpha_pll_lucid_evo_ops, 364 }, 365 }, 366 }; 367 368 static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { 369 { 0x1, 2 }, 370 { } 371 }; 372 373 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { 374 .offset = 0x5000, 375 .post_div_shift = 10, 376 .post_div_table = post_div_table_cam_cc_pll5_out_even, 377 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even), 378 .width = 4, 379 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 380 .clkr.hw.init = &(const struct clk_init_data) { 381 .name = "cam_cc_pll5_out_even", 382 .parent_hws = (const struct clk_hw*[]) { 383 &cam_cc_pll5.clkr.hw, 384 }, 385 .num_parents = 1, 386 .flags = CLK_SET_RATE_PARENT, 387 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 388 }, 389 }; 390 391 /* 700.0 MHz Configuration */ 392 static const struct alpha_pll_config cam_cc_pll6_config = { 393 .l = 0x24, 394 .alpha = 0x7555, 395 .config_ctl_val = 0x20485699, 396 .config_ctl_hi_val = 0x00182261, 397 .config_ctl_hi1_val = 0x82aa299c, 398 .test_ctl_val = 0x00000000, 399 .test_ctl_hi_val = 0x00000003, 400 .test_ctl_hi1_val = 0x00009000, 401 .test_ctl_hi2_val = 0x00000034, 402 .user_ctl_val = 0x00000400, 403 .user_ctl_hi_val = 0x00000005, 404 }; 405 406 static struct clk_alpha_pll cam_cc_pll6 = { 407 .offset = 0x6000, 408 .config = &cam_cc_pll6_config, 409 .vco_table = lucid_ole_vco, 410 .num_vco = ARRAY_SIZE(lucid_ole_vco), 411 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 412 .clkr = { 413 .hw.init = &(const struct clk_init_data) { 414 .name = "cam_cc_pll6", 415 .parent_data = &(const struct clk_parent_data) { 416 .index = DT_BI_TCXO, 417 }, 418 .num_parents = 1, 419 .ops = &clk_alpha_pll_lucid_evo_ops, 420 }, 421 }, 422 }; 423 424 static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { 425 { 0x1, 2 }, 426 { } 427 }; 428 429 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { 430 .offset = 0x6000, 431 .post_div_shift = 10, 432 .post_div_table = post_div_table_cam_cc_pll6_out_even, 433 .num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even), 434 .width = 4, 435 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 436 .clkr.hw.init = &(const struct clk_init_data) { 437 .name = "cam_cc_pll6_out_even", 438 .parent_hws = (const struct clk_hw*[]) { 439 &cam_cc_pll6.clkr.hw, 440 }, 441 .num_parents = 1, 442 .flags = CLK_SET_RATE_PARENT, 443 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 444 }, 445 }; 446 447 static const struct parent_map cam_cc_parent_map_0[] = { 448 { P_BI_TCXO, 0 }, 449 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 450 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 451 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 452 }; 453 454 static const struct clk_parent_data cam_cc_parent_data_0[] = { 455 { .index = DT_BI_TCXO }, 456 { .hw = &cam_cc_pll0.clkr.hw }, 457 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 458 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 459 }; 460 461 static const struct parent_map cam_cc_parent_map_1[] = { 462 { P_BI_TCXO, 0 }, 463 { P_CAM_CC_PLL2_OUT_MAIN, 4 }, 464 }; 465 466 static const struct clk_parent_data cam_cc_parent_data_1[] = { 467 { .index = DT_BI_TCXO }, 468 { .hw = &cam_cc_pll2.clkr.hw }, 469 }; 470 471 static const struct parent_map cam_cc_parent_map_2[] = { 472 { P_BI_TCXO, 0 }, 473 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 474 { P_CAM_CC_PLL1_OUT_MAIN, 2 }, 475 { P_CAM_CC_PLL1_OUT_EVEN, 3 }, 476 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 477 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 478 }; 479 480 static const struct clk_parent_data cam_cc_parent_data_2[] = { 481 { .index = DT_BI_TCXO }, 482 { .hw = &cam_cc_pll0.clkr.hw }, 483 { .hw = &cam_cc_pll1.clkr.hw }, 484 { .hw = &cam_cc_pll1_out_even.clkr.hw }, 485 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 486 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 487 }; 488 489 static const struct parent_map cam_cc_parent_map_3[] = { 490 { P_BI_TCXO, 0 }, 491 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 492 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 493 }; 494 495 static const struct clk_parent_data cam_cc_parent_data_3[] = { 496 { .index = DT_BI_TCXO }, 497 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 498 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 499 }; 500 501 static const struct parent_map cam_cc_parent_map_4[] = { 502 { P_BI_TCXO, 0 }, 503 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 504 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 505 }; 506 507 static const struct clk_parent_data cam_cc_parent_data_4[] = { 508 { .index = DT_BI_TCXO }, 509 { .hw = &cam_cc_pll0.clkr.hw }, 510 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 511 }; 512 513 static const struct parent_map cam_cc_parent_map_5[] = { 514 { P_BI_TCXO, 0 }, 515 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 516 { P_CAM_CC_PLL3_OUT_EVEN, 5 }, 517 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 518 }; 519 520 static const struct clk_parent_data cam_cc_parent_data_5[] = { 521 { .index = DT_BI_TCXO }, 522 { .hw = &cam_cc_pll0.clkr.hw }, 523 { .hw = &cam_cc_pll3_out_even.clkr.hw }, 524 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 525 }; 526 527 static const struct parent_map cam_cc_parent_map_6[] = { 528 { P_SLEEP_CLK, 0 }, 529 }; 530 531 static const struct clk_parent_data cam_cc_parent_data_6_ao[] = { 532 { .index = DT_SLEEP_CLK }, 533 }; 534 535 static const struct parent_map cam_cc_parent_map_7[] = { 536 { P_BI_TCXO, 0 }, 537 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 538 { P_CAM_CC_PLL4_OUT_EVEN, 2 }, 539 { P_CAM_CC_PLL4_OUT_MAIN, 3 }, 540 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 541 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 542 }; 543 544 static const struct clk_parent_data cam_cc_parent_data_7[] = { 545 { .index = DT_BI_TCXO }, 546 { .hw = &cam_cc_pll0.clkr.hw }, 547 { .hw = &cam_cc_pll4_out_even.clkr.hw }, 548 { .hw = &cam_cc_pll4.clkr.hw }, 549 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 550 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 551 }; 552 553 static const struct parent_map cam_cc_parent_map_8[] = { 554 { P_BI_TCXO, 0 }, 555 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 556 { P_CAM_CC_PLL5_OUT_EVEN, 2 }, 557 { P_CAM_CC_PLL5_OUT_MAIN, 3 }, 558 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 559 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 560 }; 561 562 static const struct clk_parent_data cam_cc_parent_data_8[] = { 563 { .index = DT_BI_TCXO }, 564 { .hw = &cam_cc_pll0.clkr.hw }, 565 { .hw = &cam_cc_pll5_out_even.clkr.hw }, 566 { .hw = &cam_cc_pll5.clkr.hw }, 567 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 568 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 569 }; 570 571 static const struct parent_map cam_cc_parent_map_9[] = { 572 { P_BI_TCXO, 0 }, 573 { P_CAM_CC_PLL0_OUT_MAIN, 1 }, 574 { P_CAM_CC_PLL6_OUT_EVEN, 2 }, 575 { P_CAM_CC_PLL6_OUT_MAIN, 3 }, 576 { P_CAM_CC_PLL0_OUT_ODD, 5 }, 577 { P_CAM_CC_PLL0_OUT_EVEN, 6 }, 578 }; 579 580 static const struct clk_parent_data cam_cc_parent_data_9[] = { 581 { .index = DT_BI_TCXO }, 582 { .hw = &cam_cc_pll0.clkr.hw }, 583 { .hw = &cam_cc_pll6_out_even.clkr.hw }, 584 { .hw = &cam_cc_pll6.clkr.hw }, 585 { .hw = &cam_cc_pll0_out_odd.clkr.hw }, 586 { .hw = &cam_cc_pll0_out_even.clkr.hw }, 587 }; 588 589 static const struct parent_map cam_cc_parent_map_10[] = { 590 { P_BI_TCXO, 0 }, 591 }; 592 593 static const struct clk_parent_data cam_cc_parent_data_10[] = { 594 { .index = DT_BI_TCXO }, 595 }; 596 597 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = { 598 F(300000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 599 F(410000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 600 F(460000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 601 F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 602 F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0), 603 { } 604 }; 605 606 static struct clk_rcg2 cam_cc_bps_clk_src = { 607 .cmd_rcgr = 0x1a004, 608 .mnd_width = 0, 609 .hid_width = 5, 610 .parent_map = cam_cc_parent_map_2, 611 .freq_tbl = ftbl_cam_cc_bps_clk_src, 612 .clkr.hw.init = &(const struct clk_init_data) { 613 .name = "cam_cc_bps_clk_src", 614 .parent_data = cam_cc_parent_data_2, 615 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 616 .flags = CLK_SET_RATE_PARENT, 617 .ops = &clk_rcg2_shared_ops, 618 }, 619 }; 620 621 static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = { 622 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 623 F(240000000, P_CAM_CC_PLL0_OUT_EVEN, 2.5, 0, 0), 624 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 625 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 626 { } 627 }; 628 629 static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = { 630 .cmd_rcgr = 0x2401c, 631 .mnd_width = 0, 632 .hid_width = 5, 633 .parent_map = cam_cc_parent_map_0, 634 .freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src, 635 .clkr.hw.init = &(const struct clk_init_data) { 636 .name = "cam_cc_camnoc_axi_clk_src", 637 .parent_data = cam_cc_parent_data_0, 638 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 639 .flags = CLK_SET_RATE_PARENT, 640 .ops = &clk_rcg2_shared_ops, 641 }, 642 }; 643 644 static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = { 645 F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0), 646 F(50000000, P_CAM_CC_PLL0_OUT_EVEN, 12, 0, 0), 647 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 648 { } 649 }; 650 651 static struct clk_rcg2 cam_cc_cci_0_clk_src = { 652 .cmd_rcgr = 0x21004, 653 .mnd_width = 8, 654 .hid_width = 5, 655 .parent_map = cam_cc_parent_map_3, 656 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 657 .clkr.hw.init = &(const struct clk_init_data) { 658 .name = "cam_cc_cci_0_clk_src", 659 .parent_data = cam_cc_parent_data_3, 660 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 661 .flags = CLK_SET_RATE_PARENT, 662 .ops = &clk_rcg2_shared_ops, 663 }, 664 }; 665 666 static struct clk_rcg2 cam_cc_cci_1_clk_src = { 667 .cmd_rcgr = 0x22004, 668 .mnd_width = 8, 669 .hid_width = 5, 670 .parent_map = cam_cc_parent_map_3, 671 .freq_tbl = ftbl_cam_cc_cci_0_clk_src, 672 .clkr.hw.init = &(const struct clk_init_data) { 673 .name = "cam_cc_cci_1_clk_src", 674 .parent_data = cam_cc_parent_data_3, 675 .num_parents = ARRAY_SIZE(cam_cc_parent_data_3), 676 .flags = CLK_SET_RATE_PARENT, 677 .ops = &clk_rcg2_shared_ops, 678 }, 679 }; 680 681 static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { 682 F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0), 683 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 684 F(400000000, P_CAM_CC_PLL0_OUT_EVEN, 1.5, 0, 0), 685 { } 686 }; 687 688 static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { 689 .cmd_rcgr = 0x1c05c, 690 .mnd_width = 0, 691 .hid_width = 5, 692 .parent_map = cam_cc_parent_map_0, 693 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 694 .clkr.hw.init = &(const struct clk_init_data) { 695 .name = "cam_cc_cphy_rx_clk_src", 696 .parent_data = cam_cc_parent_data_0, 697 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 698 .flags = CLK_SET_RATE_PARENT, 699 .ops = &clk_rcg2_shared_ops, 700 }, 701 }; 702 703 static const struct freq_tbl ftbl_cam_cc_cre_clk_src[] = { 704 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 705 F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), 706 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 707 { } 708 }; 709 710 static struct clk_rcg2 cam_cc_cre_clk_src = { 711 .cmd_rcgr = 0x27004, 712 .mnd_width = 0, 713 .hid_width = 5, 714 .parent_map = cam_cc_parent_map_2, 715 .freq_tbl = ftbl_cam_cc_cre_clk_src, 716 .clkr.hw.init = &(const struct clk_init_data) { 717 .name = "cam_cc_cre_clk_src", 718 .parent_data = cam_cc_parent_data_2, 719 .num_parents = ARRAY_SIZE(cam_cc_parent_data_2), 720 .flags = CLK_SET_RATE_PARENT, 721 .ops = &clk_rcg2_shared_ops, 722 }, 723 }; 724 725 static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { 726 F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), 727 { } 728 }; 729 730 static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { 731 .cmd_rcgr = 0x19004, 732 .mnd_width = 0, 733 .hid_width = 5, 734 .parent_map = cam_cc_parent_map_0, 735 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 736 .clkr.hw.init = &(const struct clk_init_data) { 737 .name = "cam_cc_csi0phytimer_clk_src", 738 .parent_data = cam_cc_parent_data_0, 739 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 740 .flags = CLK_SET_RATE_PARENT, 741 .ops = &clk_rcg2_shared_ops, 742 }, 743 }; 744 745 static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { 746 .cmd_rcgr = 0x19028, 747 .mnd_width = 0, 748 .hid_width = 5, 749 .parent_map = cam_cc_parent_map_0, 750 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 751 .clkr.hw.init = &(const struct clk_init_data) { 752 .name = "cam_cc_csi1phytimer_clk_src", 753 .parent_data = cam_cc_parent_data_0, 754 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 755 .flags = CLK_SET_RATE_PARENT, 756 .ops = &clk_rcg2_shared_ops, 757 }, 758 }; 759 760 static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { 761 .cmd_rcgr = 0x1904c, 762 .mnd_width = 0, 763 .hid_width = 5, 764 .parent_map = cam_cc_parent_map_0, 765 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 766 .clkr.hw.init = &(const struct clk_init_data) { 767 .name = "cam_cc_csi2phytimer_clk_src", 768 .parent_data = cam_cc_parent_data_0, 769 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 770 .flags = CLK_SET_RATE_PARENT, 771 .ops = &clk_rcg2_shared_ops, 772 }, 773 }; 774 775 static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { 776 .cmd_rcgr = 0x19070, 777 .mnd_width = 0, 778 .hid_width = 5, 779 .parent_map = cam_cc_parent_map_0, 780 .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, 781 .clkr.hw.init = &(const struct clk_init_data) { 782 .name = "cam_cc_csi3phytimer_clk_src", 783 .parent_data = cam_cc_parent_data_0, 784 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 785 .flags = CLK_SET_RATE_PARENT, 786 .ops = &clk_rcg2_shared_ops, 787 }, 788 }; 789 790 static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = { 791 F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0), 792 F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), 793 F(200000000, P_CAM_CC_PLL0_OUT_MAIN, 6, 0, 0), 794 F(240000000, P_CAM_CC_PLL0_OUT_MAIN, 5, 0, 0), 795 { } 796 }; 797 798 static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { 799 .cmd_rcgr = 0x1a030, 800 .mnd_width = 0, 801 .hid_width = 5, 802 .parent_map = cam_cc_parent_map_0, 803 .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, 804 .clkr.hw.init = &(const struct clk_init_data) { 805 .name = "cam_cc_fast_ahb_clk_src", 806 .parent_data = cam_cc_parent_data_0, 807 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 808 .flags = CLK_SET_RATE_PARENT, 809 .ops = &clk_rcg2_shared_ops, 810 }, 811 }; 812 813 static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = { 814 F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), 815 F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), 816 F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0), 817 { } 818 }; 819 820 static struct clk_rcg2 cam_cc_icp_clk_src = { 821 .cmd_rcgr = 0x20014, 822 .mnd_width = 0, 823 .hid_width = 5, 824 .parent_map = cam_cc_parent_map_4, 825 .freq_tbl = ftbl_cam_cc_icp_clk_src, 826 .clkr.hw.init = &(const struct clk_init_data) { 827 .name = "cam_cc_icp_clk_src", 828 .parent_data = cam_cc_parent_data_4, 829 .num_parents = ARRAY_SIZE(cam_cc_parent_data_4), 830 .flags = CLK_SET_RATE_PARENT, 831 .ops = &clk_rcg2_shared_ops, 832 }, 833 }; 834 835 static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { 836 F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50), 837 F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4), 838 F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0), 839 { } 840 }; 841 842 static struct clk_rcg2 cam_cc_mclk0_clk_src = { 843 .cmd_rcgr = 0x18004, 844 .mnd_width = 8, 845 .hid_width = 5, 846 .parent_map = cam_cc_parent_map_1, 847 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 848 .clkr.hw.init = &(const struct clk_init_data) { 849 .name = "cam_cc_mclk0_clk_src", 850 .parent_data = cam_cc_parent_data_1, 851 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 852 .flags = CLK_SET_RATE_PARENT, 853 .ops = &clk_rcg2_shared_ops, 854 }, 855 }; 856 857 static struct clk_rcg2 cam_cc_mclk1_clk_src = { 858 .cmd_rcgr = 0x18024, 859 .mnd_width = 8, 860 .hid_width = 5, 861 .parent_map = cam_cc_parent_map_1, 862 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 863 .clkr.hw.init = &(const struct clk_init_data) { 864 .name = "cam_cc_mclk1_clk_src", 865 .parent_data = cam_cc_parent_data_1, 866 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 867 .flags = CLK_SET_RATE_PARENT, 868 .ops = &clk_rcg2_shared_ops, 869 }, 870 }; 871 872 static struct clk_rcg2 cam_cc_mclk2_clk_src = { 873 .cmd_rcgr = 0x18044, 874 .mnd_width = 8, 875 .hid_width = 5, 876 .parent_map = cam_cc_parent_map_1, 877 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 878 .clkr.hw.init = &(const struct clk_init_data) { 879 .name = "cam_cc_mclk2_clk_src", 880 .parent_data = cam_cc_parent_data_1, 881 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 882 .flags = CLK_SET_RATE_PARENT, 883 .ops = &clk_rcg2_shared_ops, 884 }, 885 }; 886 887 static struct clk_rcg2 cam_cc_mclk3_clk_src = { 888 .cmd_rcgr = 0x18064, 889 .mnd_width = 8, 890 .hid_width = 5, 891 .parent_map = cam_cc_parent_map_1, 892 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 893 .clkr.hw.init = &(const struct clk_init_data) { 894 .name = "cam_cc_mclk3_clk_src", 895 .parent_data = cam_cc_parent_data_1, 896 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 897 .flags = CLK_SET_RATE_PARENT, 898 .ops = &clk_rcg2_shared_ops, 899 }, 900 }; 901 902 static struct clk_rcg2 cam_cc_mclk4_clk_src = { 903 .cmd_rcgr = 0x18084, 904 .mnd_width = 8, 905 .hid_width = 5, 906 .parent_map = cam_cc_parent_map_1, 907 .freq_tbl = ftbl_cam_cc_mclk0_clk_src, 908 .clkr.hw.init = &(const struct clk_init_data) { 909 .name = "cam_cc_mclk4_clk_src", 910 .parent_data = cam_cc_parent_data_1, 911 .num_parents = ARRAY_SIZE(cam_cc_parent_data_1), 912 .flags = CLK_SET_RATE_PARENT, 913 .ops = &clk_rcg2_shared_ops, 914 }, 915 }; 916 917 static const struct freq_tbl ftbl_cam_cc_ope_0_clk_src[] = { 918 F(300000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 919 F(410000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 920 F(520000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 921 F(645000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 922 F(700000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0), 923 { } 924 }; 925 926 static struct clk_rcg2 cam_cc_ope_0_clk_src = { 927 .cmd_rcgr = 0x1b004, 928 .mnd_width = 0, 929 .hid_width = 5, 930 .parent_map = cam_cc_parent_map_5, 931 .freq_tbl = ftbl_cam_cc_ope_0_clk_src, 932 .clkr.hw.init = &(const struct clk_init_data) { 933 .name = "cam_cc_ope_0_clk_src", 934 .parent_data = cam_cc_parent_data_5, 935 .num_parents = ARRAY_SIZE(cam_cc_parent_data_5), 936 .flags = CLK_SET_RATE_PARENT, 937 .ops = &clk_rcg2_shared_ops, 938 }, 939 }; 940 941 static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = { 942 F(32000, P_SLEEP_CLK, 1, 0, 0), 943 { } 944 }; 945 946 static struct clk_rcg2 cam_cc_sleep_clk_src = { 947 .cmd_rcgr = 0x25044, 948 .mnd_width = 0, 949 .hid_width = 5, 950 .parent_map = cam_cc_parent_map_6, 951 .freq_tbl = ftbl_cam_cc_sleep_clk_src, 952 .clkr.hw.init = &(const struct clk_init_data) { 953 .name = "cam_cc_sleep_clk_src", 954 .parent_data = cam_cc_parent_data_6_ao, 955 .num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao), 956 .flags = CLK_SET_RATE_PARENT, 957 .ops = &clk_rcg2_ops, 958 }, 959 }; 960 961 static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = { 962 F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0), 963 { } 964 }; 965 966 static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 967 .cmd_rcgr = 0x1a04c, 968 .mnd_width = 0, 969 .hid_width = 5, 970 .parent_map = cam_cc_parent_map_0, 971 .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, 972 .clkr.hw.init = &(const struct clk_init_data) { 973 .name = "cam_cc_slow_ahb_clk_src", 974 .parent_data = cam_cc_parent_data_0, 975 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 976 .flags = CLK_SET_RATE_PARENT, 977 .ops = &clk_rcg2_shared_ops, 978 }, 979 }; 980 981 static const struct freq_tbl ftbl_cam_cc_tfe_0_clk_src[] = { 982 F(350000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 983 F(570000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 984 F(600000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 985 F(725000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0), 986 { } 987 }; 988 989 static struct clk_rcg2 cam_cc_tfe_0_clk_src = { 990 .cmd_rcgr = 0x1c004, 991 .mnd_width = 0, 992 .hid_width = 5, 993 .parent_map = cam_cc_parent_map_7, 994 .freq_tbl = ftbl_cam_cc_tfe_0_clk_src, 995 .clkr.hw.init = &(const struct clk_init_data) { 996 .name = "cam_cc_tfe_0_clk_src", 997 .parent_data = cam_cc_parent_data_7, 998 .num_parents = ARRAY_SIZE(cam_cc_parent_data_7), 999 .flags = CLK_SET_RATE_PARENT, 1000 .ops = &clk_rcg2_shared_ops, 1001 }, 1002 }; 1003 1004 static struct clk_rcg2 cam_cc_tfe_0_csid_clk_src = { 1005 .cmd_rcgr = 0x1c030, 1006 .mnd_width = 0, 1007 .hid_width = 5, 1008 .parent_map = cam_cc_parent_map_0, 1009 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 1010 .clkr.hw.init = &(const struct clk_init_data) { 1011 .name = "cam_cc_tfe_0_csid_clk_src", 1012 .parent_data = cam_cc_parent_data_0, 1013 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_rcg2_shared_ops, 1016 }, 1017 }; 1018 1019 static const struct freq_tbl ftbl_cam_cc_tfe_1_clk_src[] = { 1020 F(350000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1021 F(570000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1022 F(600000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1023 F(725000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0), 1024 { } 1025 }; 1026 1027 static struct clk_rcg2 cam_cc_tfe_1_clk_src = { 1028 .cmd_rcgr = 0x1d004, 1029 .mnd_width = 0, 1030 .hid_width = 5, 1031 .parent_map = cam_cc_parent_map_8, 1032 .freq_tbl = ftbl_cam_cc_tfe_1_clk_src, 1033 .clkr.hw.init = &(const struct clk_init_data) { 1034 .name = "cam_cc_tfe_1_clk_src", 1035 .parent_data = cam_cc_parent_data_8, 1036 .num_parents = ARRAY_SIZE(cam_cc_parent_data_8), 1037 .flags = CLK_SET_RATE_PARENT, 1038 .ops = &clk_rcg2_shared_ops, 1039 }, 1040 }; 1041 1042 static struct clk_rcg2 cam_cc_tfe_1_csid_clk_src = { 1043 .cmd_rcgr = 0x1d030, 1044 .mnd_width = 0, 1045 .hid_width = 5, 1046 .parent_map = cam_cc_parent_map_0, 1047 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 1048 .clkr.hw.init = &(const struct clk_init_data) { 1049 .name = "cam_cc_tfe_1_csid_clk_src", 1050 .parent_data = cam_cc_parent_data_0, 1051 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1052 .flags = CLK_SET_RATE_PARENT, 1053 .ops = &clk_rcg2_shared_ops, 1054 }, 1055 }; 1056 1057 static const struct freq_tbl ftbl_cam_cc_tfe_2_clk_src[] = { 1058 F(350000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1059 F(570000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1060 F(600000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1061 F(725000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), 1062 { } 1063 }; 1064 1065 static struct clk_rcg2 cam_cc_tfe_2_clk_src = { 1066 .cmd_rcgr = 0x1e004, 1067 .mnd_width = 0, 1068 .hid_width = 5, 1069 .parent_map = cam_cc_parent_map_9, 1070 .freq_tbl = ftbl_cam_cc_tfe_2_clk_src, 1071 .clkr.hw.init = &(const struct clk_init_data) { 1072 .name = "cam_cc_tfe_2_clk_src", 1073 .parent_data = cam_cc_parent_data_9, 1074 .num_parents = ARRAY_SIZE(cam_cc_parent_data_9), 1075 .flags = CLK_SET_RATE_PARENT, 1076 .ops = &clk_rcg2_shared_ops, 1077 }, 1078 }; 1079 1080 static struct clk_rcg2 cam_cc_tfe_2_csid_clk_src = { 1081 .cmd_rcgr = 0x1e030, 1082 .mnd_width = 0, 1083 .hid_width = 5, 1084 .parent_map = cam_cc_parent_map_0, 1085 .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, 1086 .clkr.hw.init = &(const struct clk_init_data) { 1087 .name = "cam_cc_tfe_2_csid_clk_src", 1088 .parent_data = cam_cc_parent_data_0, 1089 .num_parents = ARRAY_SIZE(cam_cc_parent_data_0), 1090 .flags = CLK_SET_RATE_PARENT, 1091 .ops = &clk_rcg2_shared_ops, 1092 }, 1093 }; 1094 1095 static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = { 1096 F(19200000, P_BI_TCXO, 1, 0, 0), 1097 { } 1098 }; 1099 1100 static struct clk_rcg2 cam_cc_xo_clk_src = { 1101 .cmd_rcgr = 0x25020, 1102 .mnd_width = 0, 1103 .hid_width = 5, 1104 .parent_map = cam_cc_parent_map_10, 1105 .freq_tbl = ftbl_cam_cc_xo_clk_src, 1106 .clkr.hw.init = &(const struct clk_init_data) { 1107 .name = "cam_cc_xo_clk_src", 1108 .parent_data = cam_cc_parent_data_10, 1109 .num_parents = ARRAY_SIZE(cam_cc_parent_data_10), 1110 .flags = CLK_SET_RATE_PARENT, 1111 .ops = &clk_rcg2_ops, 1112 }, 1113 }; 1114 1115 static struct clk_branch cam_cc_bps_ahb_clk = { 1116 .halt_reg = 0x1a064, 1117 .halt_check = BRANCH_HALT, 1118 .clkr = { 1119 .enable_reg = 0x1a064, 1120 .enable_mask = BIT(0), 1121 .hw.init = &(const struct clk_init_data) { 1122 .name = "cam_cc_bps_ahb_clk", 1123 .parent_hws = (const struct clk_hw*[]) { 1124 &cam_cc_slow_ahb_clk_src.clkr.hw, 1125 }, 1126 .num_parents = 1, 1127 .flags = CLK_SET_RATE_PARENT, 1128 .ops = &clk_branch2_ops, 1129 }, 1130 }, 1131 }; 1132 1133 static struct clk_branch cam_cc_bps_areg_clk = { 1134 .halt_reg = 0x1a048, 1135 .halt_check = BRANCH_HALT, 1136 .clkr = { 1137 .enable_reg = 0x1a048, 1138 .enable_mask = BIT(0), 1139 .hw.init = &(const struct clk_init_data) { 1140 .name = "cam_cc_bps_areg_clk", 1141 .parent_hws = (const struct clk_hw*[]) { 1142 &cam_cc_fast_ahb_clk_src.clkr.hw, 1143 }, 1144 .num_parents = 1, 1145 .flags = CLK_SET_RATE_PARENT, 1146 .ops = &clk_branch2_ops, 1147 }, 1148 }, 1149 }; 1150 1151 static struct clk_branch cam_cc_bps_clk = { 1152 .halt_reg = 0x1a01c, 1153 .halt_check = BRANCH_HALT, 1154 .clkr = { 1155 .enable_reg = 0x1a01c, 1156 .enable_mask = BIT(0), 1157 .hw.init = &(const struct clk_init_data) { 1158 .name = "cam_cc_bps_clk", 1159 .parent_hws = (const struct clk_hw*[]) { 1160 &cam_cc_bps_clk_src.clkr.hw, 1161 }, 1162 .num_parents = 1, 1163 .flags = CLK_SET_RATE_PARENT, 1164 .ops = &clk_branch2_ops, 1165 }, 1166 }, 1167 }; 1168 1169 static struct clk_branch cam_cc_camnoc_atb_clk = { 1170 .halt_reg = 0x24040, 1171 .halt_check = BRANCH_HALT, 1172 .clkr = { 1173 .enable_reg = 0x24040, 1174 .enable_mask = BIT(0), 1175 .hw.init = &(const struct clk_init_data) { 1176 .name = "cam_cc_camnoc_atb_clk", 1177 .ops = &clk_branch2_ops, 1178 }, 1179 }, 1180 }; 1181 1182 static struct clk_branch cam_cc_camnoc_axi_hf_clk = { 1183 .halt_reg = 0x24010, 1184 .halt_check = BRANCH_HALT, 1185 .clkr = { 1186 .enable_reg = 0x24010, 1187 .enable_mask = BIT(0), 1188 .hw.init = &(const struct clk_init_data) { 1189 .name = "cam_cc_camnoc_axi_hf_clk", 1190 .ops = &clk_branch2_ops, 1191 }, 1192 }, 1193 }; 1194 1195 static struct clk_branch cam_cc_camnoc_axi_sf_clk = { 1196 .halt_reg = 0x24004, 1197 .halt_check = BRANCH_HALT, 1198 .clkr = { 1199 .enable_reg = 0x24004, 1200 .enable_mask = BIT(0), 1201 .hw.init = &(const struct clk_init_data) { 1202 .name = "cam_cc_camnoc_axi_sf_clk", 1203 .ops = &clk_branch2_ops, 1204 }, 1205 }, 1206 }; 1207 1208 static struct clk_branch cam_cc_camnoc_nrt_axi_clk = { 1209 .halt_reg = 0x2404c, 1210 .halt_check = BRANCH_HALT_VOTED, 1211 .hwcg_reg = 0x2404c, 1212 .hwcg_bit = 1, 1213 .clkr = { 1214 .enable_reg = 0x2404c, 1215 .enable_mask = BIT(0), 1216 .hw.init = &(const struct clk_init_data) { 1217 .name = "cam_cc_camnoc_nrt_axi_clk", 1218 .parent_hws = (const struct clk_hw*[]) { 1219 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1220 }, 1221 .num_parents = 1, 1222 .flags = CLK_SET_RATE_PARENT, 1223 .ops = &clk_branch2_ops, 1224 }, 1225 }, 1226 }; 1227 1228 static struct clk_branch cam_cc_camnoc_rt_axi_clk = { 1229 .halt_reg = 0x24034, 1230 .halt_check = BRANCH_HALT, 1231 .clkr = { 1232 .enable_reg = 0x24034, 1233 .enable_mask = BIT(0), 1234 .hw.init = &(const struct clk_init_data) { 1235 .name = "cam_cc_camnoc_rt_axi_clk", 1236 .parent_hws = (const struct clk_hw*[]) { 1237 &cam_cc_camnoc_axi_clk_src.clkr.hw, 1238 }, 1239 .num_parents = 1, 1240 .flags = CLK_SET_RATE_PARENT, 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch cam_cc_cci_0_clk = { 1247 .halt_reg = 0x2101c, 1248 .halt_check = BRANCH_HALT, 1249 .clkr = { 1250 .enable_reg = 0x2101c, 1251 .enable_mask = BIT(0), 1252 .hw.init = &(const struct clk_init_data) { 1253 .name = "cam_cc_cci_0_clk", 1254 .parent_hws = (const struct clk_hw*[]) { 1255 &cam_cc_cci_0_clk_src.clkr.hw, 1256 }, 1257 .num_parents = 1, 1258 .flags = CLK_SET_RATE_PARENT, 1259 .ops = &clk_branch2_ops, 1260 }, 1261 }, 1262 }; 1263 1264 static struct clk_branch cam_cc_cci_1_clk = { 1265 .halt_reg = 0x2201c, 1266 .halt_check = BRANCH_HALT, 1267 .clkr = { 1268 .enable_reg = 0x2201c, 1269 .enable_mask = BIT(0), 1270 .hw.init = &(const struct clk_init_data) { 1271 .name = "cam_cc_cci_1_clk", 1272 .parent_hws = (const struct clk_hw*[]) { 1273 &cam_cc_cci_1_clk_src.clkr.hw, 1274 }, 1275 .num_parents = 1, 1276 .flags = CLK_SET_RATE_PARENT, 1277 .ops = &clk_branch2_ops, 1278 }, 1279 }, 1280 }; 1281 1282 static struct clk_branch cam_cc_core_ahb_clk = { 1283 .halt_reg = 0x2501c, 1284 .halt_check = BRANCH_HALT_DELAY, 1285 .clkr = { 1286 .enable_reg = 0x2501c, 1287 .enable_mask = BIT(0), 1288 .hw.init = &(const struct clk_init_data) { 1289 .name = "cam_cc_core_ahb_clk", 1290 .parent_hws = (const struct clk_hw*[]) { 1291 &cam_cc_slow_ahb_clk_src.clkr.hw, 1292 }, 1293 .num_parents = 1, 1294 .flags = CLK_SET_RATE_PARENT, 1295 .ops = &clk_branch2_ops, 1296 }, 1297 }, 1298 }; 1299 1300 static struct clk_branch cam_cc_cpas_ahb_clk = { 1301 .halt_reg = 0x23004, 1302 .halt_check = BRANCH_HALT, 1303 .clkr = { 1304 .enable_reg = 0x23004, 1305 .enable_mask = BIT(0), 1306 .hw.init = &(const struct clk_init_data) { 1307 .name = "cam_cc_cpas_ahb_clk", 1308 .parent_hws = (const struct clk_hw*[]) { 1309 &cam_cc_slow_ahb_clk_src.clkr.hw, 1310 }, 1311 .num_parents = 1, 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_branch2_ops, 1314 }, 1315 }, 1316 }; 1317 1318 static struct clk_branch cam_cc_cre_ahb_clk = { 1319 .halt_reg = 0x27020, 1320 .halt_check = BRANCH_HALT, 1321 .clkr = { 1322 .enable_reg = 0x27020, 1323 .enable_mask = BIT(0), 1324 .hw.init = &(const struct clk_init_data) { 1325 .name = "cam_cc_cre_ahb_clk", 1326 .parent_hws = (const struct clk_hw*[]) { 1327 &cam_cc_slow_ahb_clk_src.clkr.hw, 1328 }, 1329 .num_parents = 1, 1330 .flags = CLK_SET_RATE_PARENT, 1331 .ops = &clk_branch2_ops, 1332 }, 1333 }, 1334 }; 1335 1336 static struct clk_branch cam_cc_cre_clk = { 1337 .halt_reg = 0x2701c, 1338 .halt_check = BRANCH_HALT, 1339 .clkr = { 1340 .enable_reg = 0x2701c, 1341 .enable_mask = BIT(0), 1342 .hw.init = &(const struct clk_init_data) { 1343 .name = "cam_cc_cre_clk", 1344 .parent_hws = (const struct clk_hw*[]) { 1345 &cam_cc_cre_clk_src.clkr.hw, 1346 }, 1347 .num_parents = 1, 1348 .flags = CLK_SET_RATE_PARENT, 1349 .ops = &clk_branch2_ops, 1350 }, 1351 }, 1352 }; 1353 1354 static struct clk_branch cam_cc_csi0phytimer_clk = { 1355 .halt_reg = 0x1901c, 1356 .halt_check = BRANCH_HALT, 1357 .clkr = { 1358 .enable_reg = 0x1901c, 1359 .enable_mask = BIT(0), 1360 .hw.init = &(const struct clk_init_data) { 1361 .name = "cam_cc_csi0phytimer_clk", 1362 .parent_hws = (const struct clk_hw*[]) { 1363 &cam_cc_csi0phytimer_clk_src.clkr.hw, 1364 }, 1365 .num_parents = 1, 1366 .flags = CLK_SET_RATE_PARENT, 1367 .ops = &clk_branch2_ops, 1368 }, 1369 }, 1370 }; 1371 1372 static struct clk_branch cam_cc_csi1phytimer_clk = { 1373 .halt_reg = 0x19040, 1374 .halt_check = BRANCH_HALT, 1375 .clkr = { 1376 .enable_reg = 0x19040, 1377 .enable_mask = BIT(0), 1378 .hw.init = &(const struct clk_init_data) { 1379 .name = "cam_cc_csi1phytimer_clk", 1380 .parent_hws = (const struct clk_hw*[]) { 1381 &cam_cc_csi1phytimer_clk_src.clkr.hw, 1382 }, 1383 .num_parents = 1, 1384 .flags = CLK_SET_RATE_PARENT, 1385 .ops = &clk_branch2_ops, 1386 }, 1387 }, 1388 }; 1389 1390 static struct clk_branch cam_cc_csi2phytimer_clk = { 1391 .halt_reg = 0x19064, 1392 .halt_check = BRANCH_HALT, 1393 .clkr = { 1394 .enable_reg = 0x19064, 1395 .enable_mask = BIT(0), 1396 .hw.init = &(const struct clk_init_data) { 1397 .name = "cam_cc_csi2phytimer_clk", 1398 .parent_hws = (const struct clk_hw*[]) { 1399 &cam_cc_csi2phytimer_clk_src.clkr.hw, 1400 }, 1401 .num_parents = 1, 1402 .flags = CLK_SET_RATE_PARENT, 1403 .ops = &clk_branch2_ops, 1404 }, 1405 }, 1406 }; 1407 1408 static struct clk_branch cam_cc_csi3phytimer_clk = { 1409 .halt_reg = 0x19088, 1410 .halt_check = BRANCH_HALT, 1411 .clkr = { 1412 .enable_reg = 0x19088, 1413 .enable_mask = BIT(0), 1414 .hw.init = &(const struct clk_init_data) { 1415 .name = "cam_cc_csi3phytimer_clk", 1416 .parent_hws = (const struct clk_hw*[]) { 1417 &cam_cc_csi3phytimer_clk_src.clkr.hw, 1418 }, 1419 .num_parents = 1, 1420 .flags = CLK_SET_RATE_PARENT, 1421 .ops = &clk_branch2_ops, 1422 }, 1423 }, 1424 }; 1425 1426 static struct clk_branch cam_cc_csiphy0_clk = { 1427 .halt_reg = 0x19020, 1428 .halt_check = BRANCH_HALT, 1429 .clkr = { 1430 .enable_reg = 0x19020, 1431 .enable_mask = BIT(0), 1432 .hw.init = &(const struct clk_init_data) { 1433 .name = "cam_cc_csiphy0_clk", 1434 .parent_hws = (const struct clk_hw*[]) { 1435 &cam_cc_cphy_rx_clk_src.clkr.hw, 1436 }, 1437 .num_parents = 1, 1438 .flags = CLK_SET_RATE_PARENT, 1439 .ops = &clk_branch2_ops, 1440 }, 1441 }, 1442 }; 1443 1444 static struct clk_branch cam_cc_csiphy1_clk = { 1445 .halt_reg = 0x19044, 1446 .halt_check = BRANCH_HALT, 1447 .clkr = { 1448 .enable_reg = 0x19044, 1449 .enable_mask = BIT(0), 1450 .hw.init = &(const struct clk_init_data) { 1451 .name = "cam_cc_csiphy1_clk", 1452 .parent_hws = (const struct clk_hw*[]) { 1453 &cam_cc_cphy_rx_clk_src.clkr.hw, 1454 }, 1455 .num_parents = 1, 1456 .flags = CLK_SET_RATE_PARENT, 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch cam_cc_csiphy2_clk = { 1463 .halt_reg = 0x19068, 1464 .halt_check = BRANCH_HALT, 1465 .clkr = { 1466 .enable_reg = 0x19068, 1467 .enable_mask = BIT(0), 1468 .hw.init = &(const struct clk_init_data) { 1469 .name = "cam_cc_csiphy2_clk", 1470 .parent_hws = (const struct clk_hw*[]) { 1471 &cam_cc_cphy_rx_clk_src.clkr.hw, 1472 }, 1473 .num_parents = 1, 1474 .flags = CLK_SET_RATE_PARENT, 1475 .ops = &clk_branch2_ops, 1476 }, 1477 }, 1478 }; 1479 1480 static struct clk_branch cam_cc_csiphy3_clk = { 1481 .halt_reg = 0x1908c, 1482 .halt_check = BRANCH_HALT, 1483 .clkr = { 1484 .enable_reg = 0x1908c, 1485 .enable_mask = BIT(0), 1486 .hw.init = &(const struct clk_init_data) { 1487 .name = "cam_cc_csiphy3_clk", 1488 .parent_hws = (const struct clk_hw*[]) { 1489 &cam_cc_cphy_rx_clk_src.clkr.hw, 1490 }, 1491 .num_parents = 1, 1492 .flags = CLK_SET_RATE_PARENT, 1493 .ops = &clk_branch2_ops, 1494 }, 1495 }, 1496 }; 1497 1498 static struct clk_branch cam_cc_icp_atb_clk = { 1499 .halt_reg = 0x20004, 1500 .halt_check = BRANCH_HALT, 1501 .clkr = { 1502 .enable_reg = 0x20004, 1503 .enable_mask = BIT(0), 1504 .hw.init = &(const struct clk_init_data) { 1505 .name = "cam_cc_icp_atb_clk", 1506 .ops = &clk_branch2_ops, 1507 }, 1508 }, 1509 }; 1510 1511 static struct clk_branch cam_cc_icp_clk = { 1512 .halt_reg = 0x2002c, 1513 .halt_check = BRANCH_HALT, 1514 .clkr = { 1515 .enable_reg = 0x2002c, 1516 .enable_mask = BIT(0), 1517 .hw.init = &(const struct clk_init_data) { 1518 .name = "cam_cc_icp_clk", 1519 .parent_hws = (const struct clk_hw*[]) { 1520 &cam_cc_icp_clk_src.clkr.hw, 1521 }, 1522 .num_parents = 1, 1523 .flags = CLK_SET_RATE_PARENT, 1524 .ops = &clk_branch2_ops, 1525 }, 1526 }, 1527 }; 1528 1529 static struct clk_branch cam_cc_icp_cti_clk = { 1530 .halt_reg = 0x20008, 1531 .halt_check = BRANCH_HALT, 1532 .clkr = { 1533 .enable_reg = 0x20008, 1534 .enable_mask = BIT(0), 1535 .hw.init = &(const struct clk_init_data) { 1536 .name = "cam_cc_icp_cti_clk", 1537 .ops = &clk_branch2_ops, 1538 }, 1539 }, 1540 }; 1541 1542 static struct clk_branch cam_cc_icp_ts_clk = { 1543 .halt_reg = 0x2000c, 1544 .halt_check = BRANCH_HALT, 1545 .clkr = { 1546 .enable_reg = 0x2000c, 1547 .enable_mask = BIT(0), 1548 .hw.init = &(const struct clk_init_data) { 1549 .name = "cam_cc_icp_ts_clk", 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553 }; 1554 1555 static struct clk_branch cam_cc_mclk0_clk = { 1556 .halt_reg = 0x1801c, 1557 .halt_check = BRANCH_HALT, 1558 .clkr = { 1559 .enable_reg = 0x1801c, 1560 .enable_mask = BIT(0), 1561 .hw.init = &(const struct clk_init_data) { 1562 .name = "cam_cc_mclk0_clk", 1563 .parent_hws = (const struct clk_hw*[]) { 1564 &cam_cc_mclk0_clk_src.clkr.hw, 1565 }, 1566 .num_parents = 1, 1567 .flags = CLK_SET_RATE_PARENT, 1568 .ops = &clk_branch2_ops, 1569 }, 1570 }, 1571 }; 1572 1573 static struct clk_branch cam_cc_mclk1_clk = { 1574 .halt_reg = 0x1803c, 1575 .halt_check = BRANCH_HALT, 1576 .clkr = { 1577 .enable_reg = 0x1803c, 1578 .enable_mask = BIT(0), 1579 .hw.init = &(const struct clk_init_data) { 1580 .name = "cam_cc_mclk1_clk", 1581 .parent_hws = (const struct clk_hw*[]) { 1582 &cam_cc_mclk1_clk_src.clkr.hw, 1583 }, 1584 .num_parents = 1, 1585 .flags = CLK_SET_RATE_PARENT, 1586 .ops = &clk_branch2_ops, 1587 }, 1588 }, 1589 }; 1590 1591 static struct clk_branch cam_cc_mclk2_clk = { 1592 .halt_reg = 0x1805c, 1593 .halt_check = BRANCH_HALT, 1594 .clkr = { 1595 .enable_reg = 0x1805c, 1596 .enable_mask = BIT(0), 1597 .hw.init = &(const struct clk_init_data) { 1598 .name = "cam_cc_mclk2_clk", 1599 .parent_hws = (const struct clk_hw*[]) { 1600 &cam_cc_mclk2_clk_src.clkr.hw, 1601 }, 1602 .num_parents = 1, 1603 .flags = CLK_SET_RATE_PARENT, 1604 .ops = &clk_branch2_ops, 1605 }, 1606 }, 1607 }; 1608 1609 static struct clk_branch cam_cc_mclk3_clk = { 1610 .halt_reg = 0x1807c, 1611 .halt_check = BRANCH_HALT, 1612 .clkr = { 1613 .enable_reg = 0x1807c, 1614 .enable_mask = BIT(0), 1615 .hw.init = &(const struct clk_init_data) { 1616 .name = "cam_cc_mclk3_clk", 1617 .parent_hws = (const struct clk_hw*[]) { 1618 &cam_cc_mclk3_clk_src.clkr.hw, 1619 }, 1620 .num_parents = 1, 1621 .flags = CLK_SET_RATE_PARENT, 1622 .ops = &clk_branch2_ops, 1623 }, 1624 }, 1625 }; 1626 1627 static struct clk_branch cam_cc_mclk4_clk = { 1628 .halt_reg = 0x1809c, 1629 .halt_check = BRANCH_HALT, 1630 .clkr = { 1631 .enable_reg = 0x1809c, 1632 .enable_mask = BIT(0), 1633 .hw.init = &(const struct clk_init_data) { 1634 .name = "cam_cc_mclk4_clk", 1635 .parent_hws = (const struct clk_hw*[]) { 1636 &cam_cc_mclk4_clk_src.clkr.hw, 1637 }, 1638 .num_parents = 1, 1639 .flags = CLK_SET_RATE_PARENT, 1640 .ops = &clk_branch2_ops, 1641 }, 1642 }, 1643 }; 1644 1645 static struct clk_branch cam_cc_ope_0_ahb_clk = { 1646 .halt_reg = 0x1b034, 1647 .halt_check = BRANCH_HALT, 1648 .clkr = { 1649 .enable_reg = 0x1b034, 1650 .enable_mask = BIT(0), 1651 .hw.init = &(const struct clk_init_data) { 1652 .name = "cam_cc_ope_0_ahb_clk", 1653 .parent_hws = (const struct clk_hw*[]) { 1654 &cam_cc_slow_ahb_clk_src.clkr.hw, 1655 }, 1656 .num_parents = 1, 1657 .flags = CLK_SET_RATE_PARENT, 1658 .ops = &clk_branch2_ops, 1659 }, 1660 }, 1661 }; 1662 1663 static struct clk_branch cam_cc_ope_0_areg_clk = { 1664 .halt_reg = 0x1b030, 1665 .halt_check = BRANCH_HALT, 1666 .clkr = { 1667 .enable_reg = 0x1b030, 1668 .enable_mask = BIT(0), 1669 .hw.init = &(const struct clk_init_data) { 1670 .name = "cam_cc_ope_0_areg_clk", 1671 .parent_hws = (const struct clk_hw*[]) { 1672 &cam_cc_fast_ahb_clk_src.clkr.hw, 1673 }, 1674 .num_parents = 1, 1675 .flags = CLK_SET_RATE_PARENT, 1676 .ops = &clk_branch2_ops, 1677 }, 1678 }, 1679 }; 1680 1681 static struct clk_branch cam_cc_ope_0_clk = { 1682 .halt_reg = 0x1b01c, 1683 .halt_check = BRANCH_HALT, 1684 .clkr = { 1685 .enable_reg = 0x1b01c, 1686 .enable_mask = BIT(0), 1687 .hw.init = &(const struct clk_init_data) { 1688 .name = "cam_cc_ope_0_clk", 1689 .parent_hws = (const struct clk_hw*[]) { 1690 &cam_cc_ope_0_clk_src.clkr.hw, 1691 }, 1692 .num_parents = 1, 1693 .flags = CLK_SET_RATE_PARENT, 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch cam_cc_soc_ahb_clk = { 1700 .halt_reg = 0x25018, 1701 .halt_check = BRANCH_HALT, 1702 .clkr = { 1703 .enable_reg = 0x25018, 1704 .enable_mask = BIT(0), 1705 .hw.init = &(const struct clk_init_data) { 1706 .name = "cam_cc_soc_ahb_clk", 1707 .ops = &clk_branch2_ops, 1708 }, 1709 }, 1710 }; 1711 1712 static struct clk_branch cam_cc_sys_tmr_clk = { 1713 .halt_reg = 0x20038, 1714 .halt_check = BRANCH_HALT, 1715 .clkr = { 1716 .enable_reg = 0x20038, 1717 .enable_mask = BIT(0), 1718 .hw.init = &(const struct clk_init_data) { 1719 .name = "cam_cc_sys_tmr_clk", 1720 .parent_hws = (const struct clk_hw*[]) { 1721 &cam_cc_xo_clk_src.clkr.hw, 1722 }, 1723 .num_parents = 1, 1724 .flags = CLK_SET_RATE_PARENT, 1725 .ops = &clk_branch2_ops, 1726 }, 1727 }, 1728 }; 1729 1730 static struct clk_branch cam_cc_tfe_0_ahb_clk = { 1731 .halt_reg = 0x1c078, 1732 .halt_check = BRANCH_HALT, 1733 .clkr = { 1734 .enable_reg = 0x1c078, 1735 .enable_mask = BIT(0), 1736 .hw.init = &(const struct clk_init_data) { 1737 .name = "cam_cc_tfe_0_ahb_clk", 1738 .parent_hws = (const struct clk_hw*[]) { 1739 &cam_cc_slow_ahb_clk_src.clkr.hw, 1740 }, 1741 .num_parents = 1, 1742 .flags = CLK_SET_RATE_PARENT, 1743 .ops = &clk_branch2_ops, 1744 }, 1745 }, 1746 }; 1747 1748 static struct clk_branch cam_cc_tfe_0_clk = { 1749 .halt_reg = 0x1c01c, 1750 .halt_check = BRANCH_HALT, 1751 .clkr = { 1752 .enable_reg = 0x1c01c, 1753 .enable_mask = BIT(0), 1754 .hw.init = &(const struct clk_init_data) { 1755 .name = "cam_cc_tfe_0_clk", 1756 .parent_hws = (const struct clk_hw*[]) { 1757 &cam_cc_tfe_0_clk_src.clkr.hw, 1758 }, 1759 .num_parents = 1, 1760 .flags = CLK_SET_RATE_PARENT, 1761 .ops = &clk_branch2_ops, 1762 }, 1763 }, 1764 }; 1765 1766 static struct clk_branch cam_cc_tfe_0_cphy_rx_clk = { 1767 .halt_reg = 0x1c074, 1768 .halt_check = BRANCH_HALT, 1769 .clkr = { 1770 .enable_reg = 0x1c074, 1771 .enable_mask = BIT(0), 1772 .hw.init = &(const struct clk_init_data) { 1773 .name = "cam_cc_tfe_0_cphy_rx_clk", 1774 .parent_hws = (const struct clk_hw*[]) { 1775 &cam_cc_cphy_rx_clk_src.clkr.hw, 1776 }, 1777 .num_parents = 1, 1778 .flags = CLK_SET_RATE_PARENT, 1779 .ops = &clk_branch2_ops, 1780 }, 1781 }, 1782 }; 1783 1784 static struct clk_branch cam_cc_tfe_0_csid_clk = { 1785 .halt_reg = 0x1c048, 1786 .halt_check = BRANCH_HALT, 1787 .clkr = { 1788 .enable_reg = 0x1c048, 1789 .enable_mask = BIT(0), 1790 .hw.init = &(const struct clk_init_data) { 1791 .name = "cam_cc_tfe_0_csid_clk", 1792 .parent_hws = (const struct clk_hw*[]) { 1793 &cam_cc_tfe_0_csid_clk_src.clkr.hw, 1794 }, 1795 .num_parents = 1, 1796 .flags = CLK_SET_RATE_PARENT, 1797 .ops = &clk_branch2_ops, 1798 }, 1799 }, 1800 }; 1801 1802 static struct clk_branch cam_cc_tfe_1_ahb_clk = { 1803 .halt_reg = 0x1d058, 1804 .halt_check = BRANCH_HALT, 1805 .clkr = { 1806 .enable_reg = 0x1d058, 1807 .enable_mask = BIT(0), 1808 .hw.init = &(const struct clk_init_data) { 1809 .name = "cam_cc_tfe_1_ahb_clk", 1810 .parent_hws = (const struct clk_hw*[]) { 1811 &cam_cc_slow_ahb_clk_src.clkr.hw, 1812 }, 1813 .num_parents = 1, 1814 .flags = CLK_SET_RATE_PARENT, 1815 .ops = &clk_branch2_ops, 1816 }, 1817 }, 1818 }; 1819 1820 static struct clk_branch cam_cc_tfe_1_clk = { 1821 .halt_reg = 0x1d01c, 1822 .halt_check = BRANCH_HALT, 1823 .clkr = { 1824 .enable_reg = 0x1d01c, 1825 .enable_mask = BIT(0), 1826 .hw.init = &(const struct clk_init_data) { 1827 .name = "cam_cc_tfe_1_clk", 1828 .parent_hws = (const struct clk_hw*[]) { 1829 &cam_cc_tfe_1_clk_src.clkr.hw, 1830 }, 1831 .num_parents = 1, 1832 .flags = CLK_SET_RATE_PARENT, 1833 .ops = &clk_branch2_ops, 1834 }, 1835 }, 1836 }; 1837 1838 static struct clk_branch cam_cc_tfe_1_cphy_rx_clk = { 1839 .halt_reg = 0x1d054, 1840 .halt_check = BRANCH_HALT, 1841 .clkr = { 1842 .enable_reg = 0x1d054, 1843 .enable_mask = BIT(0), 1844 .hw.init = &(const struct clk_init_data) { 1845 .name = "cam_cc_tfe_1_cphy_rx_clk", 1846 .parent_hws = (const struct clk_hw*[]) { 1847 &cam_cc_cphy_rx_clk_src.clkr.hw, 1848 }, 1849 .num_parents = 1, 1850 .flags = CLK_SET_RATE_PARENT, 1851 .ops = &clk_branch2_ops, 1852 }, 1853 }, 1854 }; 1855 1856 static struct clk_branch cam_cc_tfe_1_csid_clk = { 1857 .halt_reg = 0x1d048, 1858 .halt_check = BRANCH_HALT, 1859 .clkr = { 1860 .enable_reg = 0x1d048, 1861 .enable_mask = BIT(0), 1862 .hw.init = &(const struct clk_init_data) { 1863 .name = "cam_cc_tfe_1_csid_clk", 1864 .parent_hws = (const struct clk_hw*[]) { 1865 &cam_cc_tfe_1_csid_clk_src.clkr.hw, 1866 }, 1867 .num_parents = 1, 1868 .flags = CLK_SET_RATE_PARENT, 1869 .ops = &clk_branch2_ops, 1870 }, 1871 }, 1872 }; 1873 1874 static struct clk_branch cam_cc_tfe_2_ahb_clk = { 1875 .halt_reg = 0x1e058, 1876 .halt_check = BRANCH_HALT, 1877 .clkr = { 1878 .enable_reg = 0x1e058, 1879 .enable_mask = BIT(0), 1880 .hw.init = &(const struct clk_init_data) { 1881 .name = "cam_cc_tfe_2_ahb_clk", 1882 .parent_hws = (const struct clk_hw*[]) { 1883 &cam_cc_slow_ahb_clk_src.clkr.hw, 1884 }, 1885 .num_parents = 1, 1886 .flags = CLK_SET_RATE_PARENT, 1887 .ops = &clk_branch2_ops, 1888 }, 1889 }, 1890 }; 1891 1892 static struct clk_branch cam_cc_tfe_2_clk = { 1893 .halt_reg = 0x1e01c, 1894 .halt_check = BRANCH_HALT, 1895 .clkr = { 1896 .enable_reg = 0x1e01c, 1897 .enable_mask = BIT(0), 1898 .hw.init = &(const struct clk_init_data) { 1899 .name = "cam_cc_tfe_2_clk", 1900 .parent_hws = (const struct clk_hw*[]) { 1901 &cam_cc_tfe_2_clk_src.clkr.hw, 1902 }, 1903 .num_parents = 1, 1904 .flags = CLK_SET_RATE_PARENT, 1905 .ops = &clk_branch2_ops, 1906 }, 1907 }, 1908 }; 1909 1910 static struct clk_branch cam_cc_tfe_2_cphy_rx_clk = { 1911 .halt_reg = 0x1e054, 1912 .halt_check = BRANCH_HALT, 1913 .clkr = { 1914 .enable_reg = 0x1e054, 1915 .enable_mask = BIT(0), 1916 .hw.init = &(const struct clk_init_data) { 1917 .name = "cam_cc_tfe_2_cphy_rx_clk", 1918 .parent_hws = (const struct clk_hw*[]) { 1919 &cam_cc_cphy_rx_clk_src.clkr.hw, 1920 }, 1921 .num_parents = 1, 1922 .flags = CLK_SET_RATE_PARENT, 1923 .ops = &clk_branch2_ops, 1924 }, 1925 }, 1926 }; 1927 1928 static struct clk_branch cam_cc_tfe_2_csid_clk = { 1929 .halt_reg = 0x1e048, 1930 .halt_check = BRANCH_HALT, 1931 .clkr = { 1932 .enable_reg = 0x1e048, 1933 .enable_mask = BIT(0), 1934 .hw.init = &(const struct clk_init_data) { 1935 .name = "cam_cc_tfe_2_csid_clk", 1936 .parent_hws = (const struct clk_hw*[]) { 1937 &cam_cc_tfe_2_csid_clk_src.clkr.hw, 1938 }, 1939 .num_parents = 1, 1940 .flags = CLK_SET_RATE_PARENT, 1941 .ops = &clk_branch2_ops, 1942 }, 1943 }, 1944 }; 1945 1946 static struct clk_branch cam_cc_top_shift_clk = { 1947 .halt_reg = 0x25040, 1948 .halt_check = BRANCH_HALT_VOTED, 1949 .clkr = { 1950 .enable_reg = 0x25040, 1951 .enable_mask = BIT(0), 1952 .hw.init = &(const struct clk_init_data) { 1953 .name = "cam_cc_top_shift_clk", 1954 .parent_hws = (const struct clk_hw*[]) { 1955 &cam_cc_xo_clk_src.clkr.hw, 1956 }, 1957 .num_parents = 1, 1958 .flags = CLK_SET_RATE_PARENT, 1959 .ops = &clk_branch2_ops, 1960 }, 1961 }, 1962 }; 1963 1964 static struct gdsc cam_cc_camss_top_gdsc = { 1965 .gdscr = 0x25004, 1966 .en_rest_wait_val = 0x2, 1967 .en_few_wait_val = 0x2, 1968 .clk_dis_wait_val = 0xf, 1969 .pd = { 1970 .name = "cam_cc_camss_top_gdsc", 1971 }, 1972 .pwrsts = PWRSTS_OFF_ON, 1973 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 1974 }; 1975 1976 static struct clk_regmap *cam_cc_milos_clocks[] = { 1977 [CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr, 1978 [CAM_CC_BPS_AREG_CLK] = &cam_cc_bps_areg_clk.clkr, 1979 [CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr, 1980 [CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr, 1981 [CAM_CC_CAMNOC_ATB_CLK] = &cam_cc_camnoc_atb_clk.clkr, 1982 [CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr, 1983 [CAM_CC_CAMNOC_AXI_HF_CLK] = &cam_cc_camnoc_axi_hf_clk.clkr, 1984 [CAM_CC_CAMNOC_AXI_SF_CLK] = &cam_cc_camnoc_axi_sf_clk.clkr, 1985 [CAM_CC_CAMNOC_NRT_AXI_CLK] = &cam_cc_camnoc_nrt_axi_clk.clkr, 1986 [CAM_CC_CAMNOC_RT_AXI_CLK] = &cam_cc_camnoc_rt_axi_clk.clkr, 1987 [CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr, 1988 [CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr, 1989 [CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr, 1990 [CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr, 1991 [CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr, 1992 [CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr, 1993 [CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr, 1994 [CAM_CC_CRE_AHB_CLK] = &cam_cc_cre_ahb_clk.clkr, 1995 [CAM_CC_CRE_CLK] = &cam_cc_cre_clk.clkr, 1996 [CAM_CC_CRE_CLK_SRC] = &cam_cc_cre_clk_src.clkr, 1997 [CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr, 1998 [CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr, 1999 [CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr, 2000 [CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr, 2001 [CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr, 2002 [CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr, 2003 [CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr, 2004 [CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr, 2005 [CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr, 2006 [CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr, 2007 [CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr, 2008 [CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr, 2009 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2010 [CAM_CC_ICP_ATB_CLK] = &cam_cc_icp_atb_clk.clkr, 2011 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2012 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, 2013 [CAM_CC_ICP_CTI_CLK] = &cam_cc_icp_cti_clk.clkr, 2014 [CAM_CC_ICP_TS_CLK] = &cam_cc_icp_ts_clk.clkr, 2015 [CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr, 2016 [CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr, 2017 [CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr, 2018 [CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr, 2019 [CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr, 2020 [CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr, 2021 [CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr, 2022 [CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr, 2023 [CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr, 2024 [CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr, 2025 [CAM_CC_OPE_0_AHB_CLK] = &cam_cc_ope_0_ahb_clk.clkr, 2026 [CAM_CC_OPE_0_AREG_CLK] = &cam_cc_ope_0_areg_clk.clkr, 2027 [CAM_CC_OPE_0_CLK] = &cam_cc_ope_0_clk.clkr, 2028 [CAM_CC_OPE_0_CLK_SRC] = &cam_cc_ope_0_clk_src.clkr, 2029 [CAM_CC_PLL0] = &cam_cc_pll0.clkr, 2030 [CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr, 2031 [CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr, 2032 [CAM_CC_PLL1] = &cam_cc_pll1.clkr, 2033 [CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr, 2034 [CAM_CC_PLL2] = &cam_cc_pll2.clkr, 2035 [CAM_CC_PLL3] = &cam_cc_pll3.clkr, 2036 [CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr, 2037 [CAM_CC_PLL4] = &cam_cc_pll4.clkr, 2038 [CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr, 2039 [CAM_CC_PLL5] = &cam_cc_pll5.clkr, 2040 [CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr, 2041 [CAM_CC_PLL6] = &cam_cc_pll6.clkr, 2042 [CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr, 2043 [CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr, 2044 [CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr, 2045 [CAM_CC_SOC_AHB_CLK] = &cam_cc_soc_ahb_clk.clkr, 2046 [CAM_CC_SYS_TMR_CLK] = &cam_cc_sys_tmr_clk.clkr, 2047 [CAM_CC_TFE_0_AHB_CLK] = &cam_cc_tfe_0_ahb_clk.clkr, 2048 [CAM_CC_TFE_0_CLK] = &cam_cc_tfe_0_clk.clkr, 2049 [CAM_CC_TFE_0_CLK_SRC] = &cam_cc_tfe_0_clk_src.clkr, 2050 [CAM_CC_TFE_0_CPHY_RX_CLK] = &cam_cc_tfe_0_cphy_rx_clk.clkr, 2051 [CAM_CC_TFE_0_CSID_CLK] = &cam_cc_tfe_0_csid_clk.clkr, 2052 [CAM_CC_TFE_0_CSID_CLK_SRC] = &cam_cc_tfe_0_csid_clk_src.clkr, 2053 [CAM_CC_TFE_1_AHB_CLK] = &cam_cc_tfe_1_ahb_clk.clkr, 2054 [CAM_CC_TFE_1_CLK] = &cam_cc_tfe_1_clk.clkr, 2055 [CAM_CC_TFE_1_CLK_SRC] = &cam_cc_tfe_1_clk_src.clkr, 2056 [CAM_CC_TFE_1_CPHY_RX_CLK] = &cam_cc_tfe_1_cphy_rx_clk.clkr, 2057 [CAM_CC_TFE_1_CSID_CLK] = &cam_cc_tfe_1_csid_clk.clkr, 2058 [CAM_CC_TFE_1_CSID_CLK_SRC] = &cam_cc_tfe_1_csid_clk_src.clkr, 2059 [CAM_CC_TFE_2_AHB_CLK] = &cam_cc_tfe_2_ahb_clk.clkr, 2060 [CAM_CC_TFE_2_CLK] = &cam_cc_tfe_2_clk.clkr, 2061 [CAM_CC_TFE_2_CLK_SRC] = &cam_cc_tfe_2_clk_src.clkr, 2062 [CAM_CC_TFE_2_CPHY_RX_CLK] = &cam_cc_tfe_2_cphy_rx_clk.clkr, 2063 [CAM_CC_TFE_2_CSID_CLK] = &cam_cc_tfe_2_csid_clk.clkr, 2064 [CAM_CC_TFE_2_CSID_CLK_SRC] = &cam_cc_tfe_2_csid_clk_src.clkr, 2065 [CAM_CC_TOP_SHIFT_CLK] = &cam_cc_top_shift_clk.clkr, 2066 [CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr, 2067 }; 2068 2069 static const struct qcom_reset_map cam_cc_milos_resets[] = { 2070 [CAM_CC_BPS_BCR] = { 0x1a000 }, 2071 [CAM_CC_CAMNOC_BCR] = { 0x24000 }, 2072 [CAM_CC_CAMSS_TOP_BCR] = { 0x25000 }, 2073 [CAM_CC_CCI_0_BCR] = { 0x21000 }, 2074 [CAM_CC_CCI_1_BCR] = { 0x22000 }, 2075 [CAM_CC_CPAS_BCR] = { 0x23000 }, 2076 [CAM_CC_CRE_BCR] = { 0x27000 }, 2077 [CAM_CC_CSI0PHY_BCR] = { 0x19000 }, 2078 [CAM_CC_CSI1PHY_BCR] = { 0x19024 }, 2079 [CAM_CC_CSI2PHY_BCR] = { 0x19048 }, 2080 [CAM_CC_CSI3PHY_BCR] = { 0x1906c }, 2081 [CAM_CC_ICP_BCR] = { 0x20000 }, 2082 [CAM_CC_MCLK0_BCR] = { 0x18000 }, 2083 [CAM_CC_MCLK1_BCR] = { 0x18020 }, 2084 [CAM_CC_MCLK2_BCR] = { 0x18040 }, 2085 [CAM_CC_MCLK3_BCR] = { 0x18060 }, 2086 [CAM_CC_MCLK4_BCR] = { 0x18080 }, 2087 [CAM_CC_OPE_0_BCR] = { 0x1b000 }, 2088 [CAM_CC_TFE_0_BCR] = { 0x1c000 }, 2089 [CAM_CC_TFE_1_BCR] = { 0x1d000 }, 2090 [CAM_CC_TFE_2_BCR] = { 0x1e000 }, 2091 }; 2092 2093 static struct gdsc *cam_cc_milos_gdscs[] = { 2094 [CAM_CC_CAMSS_TOP_GDSC] = &cam_cc_camss_top_gdsc, 2095 }; 2096 2097 static struct clk_alpha_pll *cam_cc_milos_plls[] = { 2098 &cam_cc_pll0, 2099 &cam_cc_pll1, 2100 &cam_cc_pll2, 2101 &cam_cc_pll3, 2102 &cam_cc_pll4, 2103 &cam_cc_pll5, 2104 &cam_cc_pll6, 2105 }; 2106 2107 static u32 cam_cc_milos_critical_cbcrs[] = { 2108 0x25038, /* CAM_CC_GDSC_CLK */ 2109 0x2505c, /* CAM_CC_SLEEP_CLK */ 2110 }; 2111 2112 static const struct regmap_config cam_cc_milos_regmap_config = { 2113 .reg_bits = 32, 2114 .reg_stride = 4, 2115 .val_bits = 32, 2116 .max_register = 0x30728, 2117 .fast_io = true, 2118 }; 2119 2120 static struct qcom_cc_driver_data cam_cc_milos_driver_data = { 2121 .alpha_plls = cam_cc_milos_plls, 2122 .num_alpha_plls = ARRAY_SIZE(cam_cc_milos_plls), 2123 .clk_cbcrs = cam_cc_milos_critical_cbcrs, 2124 .num_clk_cbcrs = ARRAY_SIZE(cam_cc_milos_critical_cbcrs), 2125 }; 2126 2127 static struct qcom_cc_desc cam_cc_milos_desc = { 2128 .config = &cam_cc_milos_regmap_config, 2129 .clks = cam_cc_milos_clocks, 2130 .num_clks = ARRAY_SIZE(cam_cc_milos_clocks), 2131 .resets = cam_cc_milos_resets, 2132 .num_resets = ARRAY_SIZE(cam_cc_milos_resets), 2133 .gdscs = cam_cc_milos_gdscs, 2134 .num_gdscs = ARRAY_SIZE(cam_cc_milos_gdscs), 2135 .use_rpm = true, 2136 .driver_data = &cam_cc_milos_driver_data, 2137 }; 2138 2139 static const struct of_device_id cam_cc_milos_match_table[] = { 2140 { .compatible = "qcom,milos-camcc" }, 2141 { } 2142 }; 2143 MODULE_DEVICE_TABLE(of, cam_cc_milos_match_table); 2144 2145 static int cam_cc_milos_probe(struct platform_device *pdev) 2146 { 2147 return qcom_cc_probe(pdev, &cam_cc_milos_desc); 2148 } 2149 2150 static struct platform_driver cam_cc_milos_driver = { 2151 .probe = cam_cc_milos_probe, 2152 .driver = { 2153 .name = "cam_cc-milos", 2154 .of_match_table = cam_cc_milos_match_table, 2155 }, 2156 }; 2157 2158 module_platform_driver(cam_cc_milos_driver); 2159 2160 MODULE_DESCRIPTION("QTI CAM_CC Milos Driver"); 2161 MODULE_LICENSE("GPL"); 2162