1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/clock/qcom,hawi-gcc.h> 14 15 #include "clk-alpha-pll.h" 16 #include "clk-branch.h" 17 #include "clk-pll.h" 18 #include "clk-rcg.h" 19 #include "clk-regmap.h" 20 #include "clk-regmap-divider.h" 21 #include "clk-regmap-mux.h" 22 #include "clk-regmap-phy-mux.h" 23 #include "common.h" 24 #include "gdsc.h" 25 #include "reset.h" 26 27 enum { 28 DT_BI_TCXO, 29 DT_BI_TCXO_AO, 30 DT_SLEEP_CLK, 31 DT_PCIE_0_PIPE_CLK, 32 DT_PCIE_1_PIPE_CLK, 33 DT_UFS_PHY_RX_SYMBOL_0_CLK, 34 DT_UFS_PHY_RX_SYMBOL_1_CLK, 35 DT_UFS_PHY_TX_SYMBOL_0_CLK, 36 DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 37 }; 38 39 enum { 40 P_BI_TCXO, 41 P_GCC_GPLL0_OUT_EVEN, 42 P_GCC_GPLL0_OUT_MAIN, 43 P_GCC_GPLL4_OUT_MAIN, 44 P_GCC_GPLL5_OUT_MAIN, 45 P_GCC_GPLL7_OUT_MAIN, 46 P_GCC_GPLL9_OUT_MAIN, 47 P_PCIE_0_PIPE_CLK, 48 P_PCIE_1_PIPE_CLK, 49 P_SLEEP_CLK, 50 P_UFS_PHY_RX_SYMBOL_0_CLK, 51 P_UFS_PHY_RX_SYMBOL_1_CLK, 52 P_UFS_PHY_TX_SYMBOL_0_CLK, 53 P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 54 }; 55 56 static struct clk_alpha_pll gcc_gpll0 = { 57 .offset = 0x0, 58 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], 59 .clkr = { 60 .enable_reg = 0x52028, 61 .enable_mask = BIT(0), 62 .hw.init = &(const struct clk_init_data) { 63 .name = "gcc_gpll0", 64 .parent_data = &(const struct clk_parent_data) { 65 .index = DT_BI_TCXO, 66 }, 67 .num_parents = 1, 68 .ops = &clk_alpha_pll_fixed_taycan_eha_t_ops, 69 }, 70 }, 71 }; 72 73 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 74 { 0x1, 2 }, 75 { } 76 }; 77 78 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 79 .offset = 0x0, 80 .post_div_shift = 10, 81 .post_div_table = post_div_table_gcc_gpll0_out_even, 82 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 83 .width = 4, 84 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], 85 .clkr.hw.init = &(const struct clk_init_data) { 86 .name = "gcc_gpll0_out_even", 87 .parent_hws = (const struct clk_hw*[]) { 88 &gcc_gpll0.clkr.hw, 89 }, 90 .num_parents = 1, 91 .ops = &clk_alpha_pll_postdiv_taycan_eha_t_ops, 92 }, 93 }; 94 95 static struct clk_alpha_pll gcc_gpll4 = { 96 .offset = 0x4000, 97 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], 98 .clkr = { 99 .enable_reg = 0x52028, 100 .enable_mask = BIT(4), 101 .hw.init = &(const struct clk_init_data) { 102 .name = "gcc_gpll4", 103 .parent_data = &(const struct clk_parent_data) { 104 .index = DT_BI_TCXO, 105 }, 106 .num_parents = 1, 107 .ops = &clk_alpha_pll_fixed_taycan_eha_t_ops, 108 }, 109 }, 110 }; 111 112 static struct clk_alpha_pll gcc_gpll5 = { 113 .offset = 0x5000, 114 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], 115 .clkr = { 116 .enable_reg = 0x52028, 117 .enable_mask = BIT(5), 118 .hw.init = &(const struct clk_init_data) { 119 .name = "gcc_gpll5", 120 .parent_data = &(const struct clk_parent_data) { 121 .index = DT_BI_TCXO, 122 }, 123 .num_parents = 1, 124 .ops = &clk_alpha_pll_fixed_taycan_eha_t_ops, 125 }, 126 }, 127 }; 128 129 static struct clk_alpha_pll gcc_gpll7 = { 130 .offset = 0x7000, 131 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], 132 .clkr = { 133 .enable_reg = 0x52028, 134 .enable_mask = BIT(7), 135 .hw.init = &(const struct clk_init_data) { 136 .name = "gcc_gpll7", 137 .parent_data = &(const struct clk_parent_data) { 138 .index = DT_BI_TCXO, 139 }, 140 .num_parents = 1, 141 .ops = &clk_alpha_pll_fixed_taycan_eha_t_ops, 142 }, 143 }, 144 }; 145 146 static struct clk_alpha_pll gcc_gpll9 = { 147 .offset = 0x9000, 148 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], 149 .clkr = { 150 .enable_reg = 0x52028, 151 .enable_mask = BIT(9), 152 .hw.init = &(const struct clk_init_data) { 153 .name = "gcc_gpll9", 154 .parent_data = &(const struct clk_parent_data) { 155 .index = DT_BI_TCXO, 156 }, 157 .num_parents = 1, 158 .ops = &clk_alpha_pll_fixed_taycan_eha_t_ops, 159 }, 160 }, 161 }; 162 163 static const struct parent_map gcc_parent_map_0[] = { 164 { P_BI_TCXO, 0 }, 165 { P_GCC_GPLL0_OUT_MAIN, 1 }, 166 { P_GCC_GPLL0_OUT_EVEN, 6 }, 167 }; 168 169 static const struct clk_parent_data gcc_parent_data_0[] = { 170 { .index = DT_BI_TCXO }, 171 { .hw = &gcc_gpll0.clkr.hw }, 172 { .hw = &gcc_gpll0_out_even.clkr.hw }, 173 }; 174 175 static const struct parent_map gcc_parent_map_1[] = { 176 { P_BI_TCXO, 0 }, 177 { P_GCC_GPLL0_OUT_MAIN, 1 }, 178 { P_GCC_GPLL7_OUT_MAIN, 2 }, 179 { P_GCC_GPLL0_OUT_EVEN, 6 }, 180 }; 181 182 static const struct clk_parent_data gcc_parent_data_1[] = { 183 { .index = DT_BI_TCXO }, 184 { .hw = &gcc_gpll0.clkr.hw }, 185 { .hw = &gcc_gpll7.clkr.hw }, 186 { .hw = &gcc_gpll0_out_even.clkr.hw }, 187 }; 188 189 static const struct parent_map gcc_parent_map_2[] = { 190 { P_BI_TCXO, 0 }, 191 { P_GCC_GPLL0_OUT_MAIN, 1 }, 192 { P_SLEEP_CLK, 5 }, 193 { P_GCC_GPLL0_OUT_EVEN, 6 }, 194 }; 195 196 static const struct clk_parent_data gcc_parent_data_2[] = { 197 { .index = DT_BI_TCXO }, 198 { .hw = &gcc_gpll0.clkr.hw }, 199 { .index = DT_SLEEP_CLK }, 200 { .hw = &gcc_gpll0_out_even.clkr.hw }, 201 }; 202 203 static const struct parent_map gcc_parent_map_3[] = { 204 { P_BI_TCXO, 0 }, 205 }; 206 207 static const struct clk_parent_data gcc_parent_data_3[] = { 208 { .index = DT_BI_TCXO }, 209 }; 210 211 static const struct parent_map gcc_parent_map_4[] = { 212 { P_BI_TCXO, 0 }, 213 { P_SLEEP_CLK, 5 }, 214 }; 215 216 static const struct clk_parent_data gcc_parent_data_4[] = { 217 { .index = DT_BI_TCXO }, 218 { .index = DT_SLEEP_CLK }, 219 }; 220 221 static const struct parent_map gcc_parent_map_5[] = { 222 { P_BI_TCXO, 0 }, 223 { P_GCC_GPLL0_OUT_MAIN, 1 }, 224 { P_GCC_GPLL5_OUT_MAIN, 3 }, 225 { P_GCC_GPLL4_OUT_MAIN, 5 }, 226 { P_GCC_GPLL0_OUT_EVEN, 6 }, 227 }; 228 229 static const struct clk_parent_data gcc_parent_data_5[] = { 230 { .index = DT_BI_TCXO }, 231 { .hw = &gcc_gpll0.clkr.hw }, 232 { .hw = &gcc_gpll5.clkr.hw }, 233 { .hw = &gcc_gpll4.clkr.hw }, 234 { .hw = &gcc_gpll0_out_even.clkr.hw }, 235 }; 236 237 static const struct parent_map gcc_parent_map_8[] = { 238 { P_BI_TCXO, 0 }, 239 { P_GCC_GPLL0_OUT_MAIN, 1 }, 240 { P_GCC_GPLL9_OUT_MAIN, 2 }, 241 { P_GCC_GPLL4_OUT_MAIN, 5 }, 242 { P_GCC_GPLL0_OUT_EVEN, 6 }, 243 }; 244 245 static const struct clk_parent_data gcc_parent_data_8[] = { 246 { .index = DT_BI_TCXO }, 247 { .hw = &gcc_gpll0.clkr.hw }, 248 { .hw = &gcc_gpll9.clkr.hw }, 249 { .hw = &gcc_gpll4.clkr.hw }, 250 { .hw = &gcc_gpll0_out_even.clkr.hw }, 251 }; 252 253 static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = { 254 .reg = 0x6b0a8, 255 .clkr = { 256 .hw.init = &(const struct clk_init_data) { 257 .name = "gcc_pcie_0_pipe_clk_src", 258 .parent_data = &(const struct clk_parent_data){ 259 .index = DT_PCIE_0_PIPE_CLK, 260 }, 261 .num_parents = 1, 262 .ops = &clk_regmap_phy_mux_ops, 263 }, 264 }, 265 }; 266 267 static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = { 268 .reg = 0x670a4, 269 .clkr = { 270 .hw.init = &(const struct clk_init_data) { 271 .name = "gcc_pcie_1_pipe_clk_src", 272 .parent_data = &(const struct clk_parent_data){ 273 .index = DT_PCIE_1_PIPE_CLK, 274 }, 275 .num_parents = 1, 276 .ops = &clk_regmap_phy_mux_ops, 277 }, 278 }, 279 }; 280 281 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = { 282 .reg = 0x77068, 283 .clkr = { 284 .hw.init = &(const struct clk_init_data) { 285 .name = "gcc_ufs_phy_rx_symbol_0_clk_src", 286 .parent_data = &(const struct clk_parent_data){ 287 .index = DT_UFS_PHY_RX_SYMBOL_0_CLK, 288 }, 289 .num_parents = 1, 290 .ops = &clk_regmap_phy_mux_ops, 291 }, 292 }, 293 }; 294 295 static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = { 296 .reg = 0x770ec, 297 .clkr = { 298 .hw.init = &(const struct clk_init_data) { 299 .name = "gcc_ufs_phy_rx_symbol_1_clk_src", 300 .parent_data = &(const struct clk_parent_data){ 301 .index = DT_UFS_PHY_RX_SYMBOL_1_CLK, 302 }, 303 .num_parents = 1, 304 .ops = &clk_regmap_phy_mux_ops, 305 }, 306 }, 307 }; 308 309 static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = { 310 .reg = 0x77058, 311 .clkr = { 312 .hw.init = &(const struct clk_init_data) { 313 .name = "gcc_ufs_phy_tx_symbol_0_clk_src", 314 .parent_data = &(const struct clk_parent_data){ 315 .index = DT_UFS_PHY_TX_SYMBOL_0_CLK, 316 }, 317 .num_parents = 1, 318 .ops = &clk_regmap_phy_mux_ops, 319 }, 320 }, 321 }; 322 323 static struct clk_regmap_phy_mux gcc_usb3_prim_phy_pipe_clk_src = { 324 .reg = 0x39074, 325 .clkr = { 326 .hw.init = &(const struct clk_init_data) { 327 .name = "gcc_usb3_prim_phy_pipe_clk_src", 328 .parent_data = &(const struct clk_parent_data){ 329 .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 330 }, 331 .num_parents = 1, 332 .ops = &clk_regmap_phy_mux_ops, 333 }, 334 }, 335 }; 336 337 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 338 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 339 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 340 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 341 { } 342 }; 343 344 static struct clk_rcg2 gcc_gp1_clk_src = { 345 .cmd_rcgr = 0x64004, 346 .mnd_width = 16, 347 .hid_width = 5, 348 .parent_map = gcc_parent_map_2, 349 .freq_tbl = ftbl_gcc_gp1_clk_src, 350 .hw_clk_ctrl = true, 351 .clkr.hw.init = &(const struct clk_init_data) { 352 .name = "gcc_gp1_clk_src", 353 .parent_data = gcc_parent_data_2, 354 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 355 .flags = CLK_SET_RATE_PARENT, 356 .ops = &clk_rcg2_shared_no_init_park_ops, 357 }, 358 }; 359 360 static struct clk_rcg2 gcc_gp2_clk_src = { 361 .cmd_rcgr = 0x65004, 362 .mnd_width = 16, 363 .hid_width = 5, 364 .parent_map = gcc_parent_map_2, 365 .freq_tbl = ftbl_gcc_gp1_clk_src, 366 .hw_clk_ctrl = true, 367 .clkr.hw.init = &(const struct clk_init_data) { 368 .name = "gcc_gp2_clk_src", 369 .parent_data = gcc_parent_data_2, 370 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 371 .flags = CLK_SET_RATE_PARENT, 372 .ops = &clk_rcg2_shared_no_init_park_ops, 373 }, 374 }; 375 376 static struct clk_rcg2 gcc_gp3_clk_src = { 377 .cmd_rcgr = 0x66004, 378 .mnd_width = 16, 379 .hid_width = 5, 380 .parent_map = gcc_parent_map_2, 381 .freq_tbl = ftbl_gcc_gp1_clk_src, 382 .hw_clk_ctrl = true, 383 .clkr.hw.init = &(const struct clk_init_data) { 384 .name = "gcc_gp3_clk_src", 385 .parent_data = gcc_parent_data_2, 386 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 387 .flags = CLK_SET_RATE_PARENT, 388 .ops = &clk_rcg2_shared_no_init_park_ops, 389 }, 390 }; 391 392 static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { 393 F(19200000, P_BI_TCXO, 1, 0, 0), 394 { } 395 }; 396 397 static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { 398 .cmd_rcgr = 0x6b0ac, 399 .mnd_width = 16, 400 .hid_width = 5, 401 .parent_map = gcc_parent_map_4, 402 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 403 .hw_clk_ctrl = true, 404 .clkr.hw.init = &(const struct clk_init_data) { 405 .name = "gcc_pcie_0_aux_clk_src", 406 .parent_data = gcc_parent_data_4, 407 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 408 .flags = CLK_SET_RATE_PARENT, 409 .ops = &clk_rcg2_shared_no_init_park_ops, 410 }, 411 }; 412 413 static struct clk_rcg2 gcc_pcie_0_phy_aux_clk_src = { 414 .cmd_rcgr = 0x6b0c4, 415 .mnd_width = 0, 416 .hid_width = 5, 417 .parent_map = gcc_parent_map_0, 418 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 419 .hw_clk_ctrl = true, 420 .clkr.hw.init = &(const struct clk_init_data) { 421 .name = "gcc_pcie_0_phy_aux_clk_src", 422 .parent_data = gcc_parent_data_0, 423 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 424 .flags = CLK_SET_RATE_PARENT, 425 .ops = &clk_rcg2_shared_no_init_park_ops, 426 }, 427 }; 428 429 static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { 430 F(19200000, P_BI_TCXO, 1, 0, 0), 431 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 432 { } 433 }; 434 435 static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { 436 .cmd_rcgr = 0x6b08c, 437 .mnd_width = 0, 438 .hid_width = 5, 439 .parent_map = gcc_parent_map_0, 440 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 441 .hw_clk_ctrl = true, 442 .clkr.hw.init = &(const struct clk_init_data) { 443 .name = "gcc_pcie_0_phy_rchng_clk_src", 444 .parent_data = gcc_parent_data_0, 445 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 446 .flags = CLK_SET_RATE_PARENT, 447 .ops = &clk_rcg2_shared_no_init_park_ops, 448 }, 449 }; 450 451 static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { 452 .cmd_rcgr = 0x670a8, 453 .mnd_width = 16, 454 .hid_width = 5, 455 .parent_map = gcc_parent_map_4, 456 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 457 .hw_clk_ctrl = true, 458 .clkr.hw.init = &(const struct clk_init_data) { 459 .name = "gcc_pcie_1_aux_clk_src", 460 .parent_data = gcc_parent_data_4, 461 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 462 .flags = CLK_SET_RATE_PARENT, 463 .ops = &clk_rcg2_shared_no_init_park_ops, 464 }, 465 }; 466 467 static struct clk_rcg2 gcc_pcie_1_phy_aux_clk_src = { 468 .cmd_rcgr = 0x670c0, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = gcc_parent_map_0, 472 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 473 .hw_clk_ctrl = true, 474 .clkr.hw.init = &(const struct clk_init_data) { 475 .name = "gcc_pcie_1_phy_aux_clk_src", 476 .parent_data = gcc_parent_data_0, 477 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 478 .flags = CLK_SET_RATE_PARENT, 479 .ops = &clk_rcg2_shared_no_init_park_ops, 480 }, 481 }; 482 483 static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { 484 .cmd_rcgr = 0x67088, 485 .mnd_width = 0, 486 .hid_width = 5, 487 .parent_map = gcc_parent_map_0, 488 .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, 489 .hw_clk_ctrl = true, 490 .clkr.hw.init = &(const struct clk_init_data) { 491 .name = "gcc_pcie_1_phy_rchng_clk_src", 492 .parent_data = gcc_parent_data_0, 493 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 494 .flags = CLK_SET_RATE_PARENT, 495 .ops = &clk_rcg2_shared_no_init_park_ops, 496 }, 497 }; 498 499 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 500 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 501 { } 502 }; 503 504 static struct clk_rcg2 gcc_pdm2_clk_src = { 505 .cmd_rcgr = 0x33010, 506 .mnd_width = 0, 507 .hid_width = 5, 508 .parent_map = gcc_parent_map_0, 509 .freq_tbl = ftbl_gcc_pdm2_clk_src, 510 .hw_clk_ctrl = true, 511 .clkr.hw.init = &(const struct clk_init_data) { 512 .name = "gcc_pdm2_clk_src", 513 .parent_data = gcc_parent_data_0, 514 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 515 .flags = CLK_SET_RATE_PARENT, 516 .ops = &clk_rcg2_shared_no_init_park_ops, 517 }, 518 }; 519 520 static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { 521 .cmd_rcgr = 0x17008, 522 .mnd_width = 0, 523 .hid_width = 5, 524 .parent_map = gcc_parent_map_0, 525 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 526 .hw_clk_ctrl = true, 527 .clkr.hw.init = &(const struct clk_init_data) { 528 .name = "gcc_qupv3_i2c_s0_clk_src", 529 .parent_data = gcc_parent_data_0, 530 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 531 .flags = CLK_SET_RATE_PARENT, 532 .ops = &clk_rcg2_shared_no_init_park_ops, 533 }, 534 }; 535 536 static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { 537 .cmd_rcgr = 0x17024, 538 .mnd_width = 0, 539 .hid_width = 5, 540 .parent_map = gcc_parent_map_0, 541 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 542 .hw_clk_ctrl = true, 543 .clkr.hw.init = &(const struct clk_init_data) { 544 .name = "gcc_qupv3_i2c_s1_clk_src", 545 .parent_data = gcc_parent_data_0, 546 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 547 .flags = CLK_SET_RATE_PARENT, 548 .ops = &clk_rcg2_shared_no_init_park_ops, 549 }, 550 }; 551 552 static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { 553 .cmd_rcgr = 0x17040, 554 .mnd_width = 0, 555 .hid_width = 5, 556 .parent_map = gcc_parent_map_0, 557 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 558 .hw_clk_ctrl = true, 559 .clkr.hw.init = &(const struct clk_init_data) { 560 .name = "gcc_qupv3_i2c_s2_clk_src", 561 .parent_data = gcc_parent_data_0, 562 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 563 .flags = CLK_SET_RATE_PARENT, 564 .ops = &clk_rcg2_shared_no_init_park_ops, 565 }, 566 }; 567 568 static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { 569 .cmd_rcgr = 0x1705c, 570 .mnd_width = 0, 571 .hid_width = 5, 572 .parent_map = gcc_parent_map_0, 573 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 574 .hw_clk_ctrl = true, 575 .clkr.hw.init = &(const struct clk_init_data) { 576 .name = "gcc_qupv3_i2c_s3_clk_src", 577 .parent_data = gcc_parent_data_0, 578 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 579 .flags = CLK_SET_RATE_PARENT, 580 .ops = &clk_rcg2_shared_no_init_park_ops, 581 }, 582 }; 583 584 static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { 585 .cmd_rcgr = 0x17078, 586 .mnd_width = 0, 587 .hid_width = 5, 588 .parent_map = gcc_parent_map_0, 589 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 590 .hw_clk_ctrl = true, 591 .clkr.hw.init = &(const struct clk_init_data) { 592 .name = "gcc_qupv3_i2c_s4_clk_src", 593 .parent_data = gcc_parent_data_0, 594 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 595 .flags = CLK_SET_RATE_PARENT, 596 .ops = &clk_rcg2_shared_no_init_park_ops, 597 }, 598 }; 599 600 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = { 601 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 602 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 603 F(19200000, P_BI_TCXO, 1, 0, 0), 604 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 605 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 606 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 607 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 608 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 609 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 610 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 611 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 612 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 613 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 614 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 615 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 616 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 617 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0), 618 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 619 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 620 { } 621 }; 622 623 static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = { 624 .name = "gcc_qupv3_wrap1_qspi_ref_clk_src", 625 .parent_data = gcc_parent_data_0, 626 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 627 .flags = CLK_SET_RATE_PARENT, 628 .ops = &clk_rcg2_shared_no_init_park_ops, 629 }; 630 631 static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = { 632 .cmd_rcgr = 0x188c0, 633 .mnd_width = 16, 634 .hid_width = 5, 635 .parent_map = gcc_parent_map_0, 636 .freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src, 637 .hw_clk_ctrl = true, 638 .clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init, 639 }; 640 641 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = { 642 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 643 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 644 F(19200000, P_BI_TCXO, 1, 0, 0), 645 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 646 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 647 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 648 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 649 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 650 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 651 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 652 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 653 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 654 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 655 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 656 { } 657 }; 658 659 static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 660 .name = "gcc_qupv3_wrap1_s0_clk_src", 661 .parent_data = gcc_parent_data_0, 662 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 663 .flags = CLK_SET_RATE_PARENT, 664 .ops = &clk_rcg2_shared_no_init_park_ops, 665 }; 666 667 static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { 668 .cmd_rcgr = 0x18014, 669 .mnd_width = 16, 670 .hid_width = 5, 671 .parent_map = gcc_parent_map_0, 672 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 673 .hw_clk_ctrl = true, 674 .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, 675 }; 676 677 static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 678 .name = "gcc_qupv3_wrap1_s1_clk_src", 679 .parent_data = gcc_parent_data_0, 680 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 681 .flags = CLK_SET_RATE_PARENT, 682 .ops = &clk_rcg2_shared_no_init_park_ops, 683 }; 684 685 static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { 686 .cmd_rcgr = 0x18150, 687 .mnd_width = 16, 688 .hid_width = 5, 689 .parent_map = gcc_parent_map_0, 690 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 691 .hw_clk_ctrl = true, 692 .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, 693 }; 694 695 static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 696 .name = "gcc_qupv3_wrap1_s3_clk_src", 697 .parent_data = gcc_parent_data_0, 698 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 699 .flags = CLK_SET_RATE_PARENT, 700 .ops = &clk_rcg2_shared_no_init_park_ops, 701 }; 702 703 static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { 704 .cmd_rcgr = 0x182a0, 705 .mnd_width = 16, 706 .hid_width = 5, 707 .parent_map = gcc_parent_map_0, 708 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 709 .hw_clk_ctrl = true, 710 .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, 711 }; 712 713 static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s4_clk_src[] = { 714 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 715 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 716 F(19200000, P_BI_TCXO, 1, 0, 0), 717 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 718 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 719 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 720 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 721 F(60000000, P_GCC_GPLL0_OUT_EVEN, 5, 0, 0), 722 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 723 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 724 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 725 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 726 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 727 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 728 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 729 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 730 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 731 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 732 { } 733 }; 734 735 static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 736 .name = "gcc_qupv3_wrap1_s4_clk_src", 737 .parent_data = gcc_parent_data_0, 738 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 739 .flags = CLK_SET_RATE_PARENT, 740 .ops = &clk_rcg2_shared_no_init_park_ops, 741 }; 742 743 static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { 744 .cmd_rcgr = 0x183dc, 745 .mnd_width = 16, 746 .hid_width = 5, 747 .parent_map = gcc_parent_map_0, 748 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 749 .hw_clk_ctrl = true, 750 .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, 751 }; 752 753 static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 754 .name = "gcc_qupv3_wrap1_s5_clk_src", 755 .parent_data = gcc_parent_data_0, 756 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 757 .flags = CLK_SET_RATE_PARENT, 758 .ops = &clk_rcg2_shared_no_init_park_ops, 759 }; 760 761 static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { 762 .cmd_rcgr = 0x18518, 763 .mnd_width = 16, 764 .hid_width = 5, 765 .parent_map = gcc_parent_map_0, 766 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 767 .hw_clk_ctrl = true, 768 .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, 769 }; 770 771 static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 772 .name = "gcc_qupv3_wrap1_s6_clk_src", 773 .parent_data = gcc_parent_data_0, 774 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 775 .flags = CLK_SET_RATE_PARENT, 776 .ops = &clk_rcg2_shared_no_init_park_ops, 777 }; 778 779 static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { 780 .cmd_rcgr = 0x18654, 781 .mnd_width = 16, 782 .hid_width = 5, 783 .parent_map = gcc_parent_map_0, 784 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 785 .hw_clk_ctrl = true, 786 .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, 787 }; 788 789 static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 790 .name = "gcc_qupv3_wrap1_s7_clk_src", 791 .parent_data = gcc_parent_data_0, 792 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 793 .flags = CLK_SET_RATE_PARENT, 794 .ops = &clk_rcg2_shared_no_init_park_ops, 795 }; 796 797 static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { 798 .cmd_rcgr = 0x18790, 799 .mnd_width = 16, 800 .hid_width = 5, 801 .parent_map = gcc_parent_map_0, 802 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 803 .hw_clk_ctrl = true, 804 .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, 805 }; 806 807 static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 808 .name = "gcc_qupv3_wrap2_s0_clk_src", 809 .parent_data = gcc_parent_data_1, 810 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 811 .flags = CLK_SET_RATE_PARENT, 812 .ops = &clk_rcg2_shared_no_init_park_ops, 813 }; 814 815 static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { 816 .cmd_rcgr = 0x1e01c, 817 .mnd_width = 16, 818 .hid_width = 5, 819 .parent_map = gcc_parent_map_1, 820 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 821 .hw_clk_ctrl = true, 822 .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, 823 }; 824 825 static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 826 .name = "gcc_qupv3_wrap2_s1_clk_src", 827 .parent_data = gcc_parent_data_1, 828 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 829 .flags = CLK_SET_RATE_PARENT, 830 .ops = &clk_rcg2_shared_no_init_park_ops, 831 }; 832 833 static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { 834 .cmd_rcgr = 0x1e160, 835 .mnd_width = 16, 836 .hid_width = 5, 837 .parent_map = gcc_parent_map_1, 838 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 839 .hw_clk_ctrl = true, 840 .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, 841 }; 842 843 static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 844 .name = "gcc_qupv3_wrap2_s2_clk_src", 845 .parent_data = gcc_parent_data_0, 846 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 847 .flags = CLK_SET_RATE_PARENT, 848 .ops = &clk_rcg2_shared_no_init_park_ops, 849 }; 850 851 static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { 852 .cmd_rcgr = 0x1e29c, 853 .mnd_width = 16, 854 .hid_width = 5, 855 .parent_map = gcc_parent_map_0, 856 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 857 .hw_clk_ctrl = true, 858 .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, 859 }; 860 861 static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 862 .name = "gcc_qupv3_wrap2_s3_clk_src", 863 .parent_data = gcc_parent_data_0, 864 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 865 .flags = CLK_SET_RATE_PARENT, 866 .ops = &clk_rcg2_shared_no_init_park_ops, 867 }; 868 869 static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { 870 .cmd_rcgr = 0x1e3d8, 871 .mnd_width = 16, 872 .hid_width = 5, 873 .parent_map = gcc_parent_map_0, 874 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 875 .hw_clk_ctrl = true, 876 .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, 877 }; 878 879 static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 880 .name = "gcc_qupv3_wrap2_s4_clk_src", 881 .parent_data = gcc_parent_data_0, 882 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 883 .flags = CLK_SET_RATE_PARENT, 884 .ops = &clk_rcg2_shared_no_init_park_ops, 885 }; 886 887 static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { 888 .cmd_rcgr = 0x1e514, 889 .mnd_width = 16, 890 .hid_width = 5, 891 .parent_map = gcc_parent_map_0, 892 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 893 .hw_clk_ctrl = true, 894 .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, 895 }; 896 897 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = { 898 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 899 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 900 F(19200000, P_BI_TCXO, 1, 0, 0), 901 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 902 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 903 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 904 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 905 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 906 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 907 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 908 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 909 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 910 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 911 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 912 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 913 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 914 F(120000000, P_GCC_GPLL0_OUT_EVEN, 2.5, 0, 0), 915 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 916 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 917 { } 918 }; 919 920 static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = { 921 .name = "gcc_qupv3_wrap3_qspi_ref_clk_src", 922 .parent_data = gcc_parent_data_1, 923 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 924 .flags = CLK_SET_RATE_PARENT, 925 .ops = &clk_rcg2_shared_no_init_park_ops, 926 }; 927 928 static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = { 929 .cmd_rcgr = 0xa8650, 930 .mnd_width = 16, 931 .hid_width = 5, 932 .parent_map = gcc_parent_map_1, 933 .freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src, 934 .hw_clk_ctrl = true, 935 .clkr.hw.init = &gcc_qupv3_wrap3_qspi_ref_clk_src_init, 936 }; 937 938 static struct clk_init_data gcc_qupv3_wrap3_s0_clk_src_init = { 939 .name = "gcc_qupv3_wrap3_s0_clk_src", 940 .parent_data = gcc_parent_data_0, 941 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 942 .flags = CLK_SET_RATE_PARENT, 943 .ops = &clk_rcg2_shared_no_init_park_ops, 944 }; 945 946 static struct clk_rcg2 gcc_qupv3_wrap3_s0_clk_src = { 947 .cmd_rcgr = 0xa8014, 948 .mnd_width = 16, 949 .hid_width = 5, 950 .parent_map = gcc_parent_map_0, 951 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 952 .hw_clk_ctrl = true, 953 .clkr.hw.init = &gcc_qupv3_wrap3_s0_clk_src_init, 954 }; 955 956 static struct clk_init_data gcc_qupv3_wrap3_s2_clk_src_init = { 957 .name = "gcc_qupv3_wrap3_s2_clk_src", 958 .parent_data = gcc_parent_data_0, 959 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 960 .flags = CLK_SET_RATE_PARENT, 961 .ops = &clk_rcg2_shared_no_init_park_ops, 962 }; 963 964 static struct clk_rcg2 gcc_qupv3_wrap3_s2_clk_src = { 965 .cmd_rcgr = 0xa8168, 966 .mnd_width = 16, 967 .hid_width = 5, 968 .parent_map = gcc_parent_map_0, 969 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 970 .hw_clk_ctrl = true, 971 .clkr.hw.init = &gcc_qupv3_wrap3_s2_clk_src_init, 972 }; 973 974 static struct clk_init_data gcc_qupv3_wrap3_s3_clk_src_init = { 975 .name = "gcc_qupv3_wrap3_s3_clk_src", 976 .parent_data = gcc_parent_data_0, 977 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 978 .flags = CLK_SET_RATE_PARENT, 979 .ops = &clk_rcg2_shared_no_init_park_ops, 980 }; 981 982 static struct clk_rcg2 gcc_qupv3_wrap3_s3_clk_src = { 983 .cmd_rcgr = 0xa82a4, 984 .mnd_width = 16, 985 .hid_width = 5, 986 .parent_map = gcc_parent_map_0, 987 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 988 .hw_clk_ctrl = true, 989 .clkr.hw.init = &gcc_qupv3_wrap3_s3_clk_src_init, 990 }; 991 992 static struct clk_init_data gcc_qupv3_wrap3_s4_clk_src_init = { 993 .name = "gcc_qupv3_wrap3_s4_clk_src", 994 .parent_data = gcc_parent_data_0, 995 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 996 .flags = CLK_SET_RATE_PARENT, 997 .ops = &clk_rcg2_shared_no_init_park_ops, 998 }; 999 1000 static struct clk_rcg2 gcc_qupv3_wrap3_s4_clk_src = { 1001 .cmd_rcgr = 0xa83e0, 1002 .mnd_width = 16, 1003 .hid_width = 5, 1004 .parent_map = gcc_parent_map_0, 1005 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1006 .hw_clk_ctrl = true, 1007 .clkr.hw.init = &gcc_qupv3_wrap3_s4_clk_src_init, 1008 }; 1009 1010 static struct clk_init_data gcc_qupv3_wrap3_s5_clk_src_init = { 1011 .name = "gcc_qupv3_wrap3_s5_clk_src", 1012 .parent_data = gcc_parent_data_0, 1013 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1014 .flags = CLK_SET_RATE_PARENT, 1015 .ops = &clk_rcg2_shared_no_init_park_ops, 1016 }; 1017 1018 static struct clk_rcg2 gcc_qupv3_wrap3_s5_clk_src = { 1019 .cmd_rcgr = 0xa851c, 1020 .mnd_width = 16, 1021 .hid_width = 5, 1022 .parent_map = gcc_parent_map_0, 1023 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1024 .hw_clk_ctrl = true, 1025 .clkr.hw.init = &gcc_qupv3_wrap3_s5_clk_src_init, 1026 }; 1027 1028 static struct clk_init_data gcc_qupv3_wrap4_s0_clk_src_init = { 1029 .name = "gcc_qupv3_wrap4_s0_clk_src", 1030 .parent_data = gcc_parent_data_1, 1031 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1032 .flags = CLK_SET_RATE_PARENT, 1033 .ops = &clk_rcg2_shared_no_init_park_ops, 1034 }; 1035 1036 static struct clk_rcg2 gcc_qupv3_wrap4_s0_clk_src = { 1037 .cmd_rcgr = 0xa9014, 1038 .mnd_width = 16, 1039 .hid_width = 5, 1040 .parent_map = gcc_parent_map_1, 1041 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1042 .hw_clk_ctrl = true, 1043 .clkr.hw.init = &gcc_qupv3_wrap4_s0_clk_src_init, 1044 }; 1045 1046 static struct clk_init_data gcc_qupv3_wrap4_s1_clk_src_init = { 1047 .name = "gcc_qupv3_wrap4_s1_clk_src", 1048 .parent_data = gcc_parent_data_1, 1049 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1050 .flags = CLK_SET_RATE_PARENT, 1051 .ops = &clk_rcg2_shared_no_init_park_ops, 1052 }; 1053 1054 static struct clk_rcg2 gcc_qupv3_wrap4_s1_clk_src = { 1055 .cmd_rcgr = 0xa9150, 1056 .mnd_width = 16, 1057 .hid_width = 5, 1058 .parent_map = gcc_parent_map_1, 1059 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1060 .hw_clk_ctrl = true, 1061 .clkr.hw.init = &gcc_qupv3_wrap4_s1_clk_src_init, 1062 }; 1063 1064 static struct clk_init_data gcc_qupv3_wrap4_s2_clk_src_init = { 1065 .name = "gcc_qupv3_wrap4_s2_clk_src", 1066 .parent_data = gcc_parent_data_1, 1067 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1068 .flags = CLK_SET_RATE_PARENT, 1069 .ops = &clk_rcg2_shared_no_init_park_ops, 1070 }; 1071 1072 static struct clk_rcg2 gcc_qupv3_wrap4_s2_clk_src = { 1073 .cmd_rcgr = 0xa928c, 1074 .mnd_width = 16, 1075 .hid_width = 5, 1076 .parent_map = gcc_parent_map_1, 1077 .freq_tbl = ftbl_gcc_qupv3_wrap1_s4_clk_src, 1078 .hw_clk_ctrl = true, 1079 .clkr.hw.init = &gcc_qupv3_wrap4_s2_clk_src_init, 1080 }; 1081 1082 static struct clk_init_data gcc_qupv3_wrap4_s3_clk_src_init = { 1083 .name = "gcc_qupv3_wrap4_s3_clk_src", 1084 .parent_data = gcc_parent_data_1, 1085 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1086 .flags = CLK_SET_RATE_PARENT, 1087 .ops = &clk_rcg2_shared_no_init_park_ops, 1088 }; 1089 1090 static struct clk_rcg2 gcc_qupv3_wrap4_s3_clk_src = { 1091 .cmd_rcgr = 0xa93c8, 1092 .mnd_width = 16, 1093 .hid_width = 5, 1094 .parent_map = gcc_parent_map_1, 1095 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1096 .hw_clk_ctrl = true, 1097 .clkr.hw.init = &gcc_qupv3_wrap4_s3_clk_src_init, 1098 }; 1099 1100 static struct clk_init_data gcc_qupv3_wrap4_s4_clk_src_init = { 1101 .name = "gcc_qupv3_wrap4_s4_clk_src", 1102 .parent_data = gcc_parent_data_1, 1103 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 1104 .flags = CLK_SET_RATE_PARENT, 1105 .ops = &clk_rcg2_shared_no_init_park_ops, 1106 }; 1107 1108 static struct clk_rcg2 gcc_qupv3_wrap4_s4_clk_src = { 1109 .cmd_rcgr = 0xa9504, 1110 .mnd_width = 16, 1111 .hid_width = 5, 1112 .parent_map = gcc_parent_map_1, 1113 .freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src, 1114 .hw_clk_ctrl = true, 1115 .clkr.hw.init = &gcc_qupv3_wrap4_s4_clk_src_init, 1116 }; 1117 1118 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { 1119 F(400000, P_BI_TCXO, 12, 1, 4), 1120 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1121 F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0), 1122 F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), 1123 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1124 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1125 F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), 1126 { } 1127 }; 1128 1129 static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 1130 .cmd_rcgr = 0x1401c, 1131 .mnd_width = 8, 1132 .hid_width = 5, 1133 .parent_map = gcc_parent_map_8, 1134 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, 1135 .hw_clk_ctrl = true, 1136 .clkr.hw.init = &(const struct clk_init_data) { 1137 .name = "gcc_sdcc2_apps_clk_src", 1138 .parent_data = gcc_parent_data_8, 1139 .num_parents = ARRAY_SIZE(gcc_parent_data_8), 1140 .flags = CLK_SET_RATE_PARENT, 1141 .ops = &clk_rcg2_shared_floor_ops, 1142 }, 1143 }; 1144 1145 static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { 1146 F(400000, P_BI_TCXO, 12, 1, 4), 1147 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1148 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1149 { } 1150 }; 1151 1152 static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { 1153 .cmd_rcgr = 0x1601c, 1154 .mnd_width = 8, 1155 .hid_width = 5, 1156 .parent_map = gcc_parent_map_0, 1157 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, 1158 .hw_clk_ctrl = true, 1159 .clkr.hw.init = &(const struct clk_init_data) { 1160 .name = "gcc_sdcc4_apps_clk_src", 1161 .parent_data = gcc_parent_data_0, 1162 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1163 .flags = CLK_SET_RATE_PARENT, 1164 .ops = &clk_rcg2_shared_floor_ops, 1165 }, 1166 }; 1167 1168 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { 1169 F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), 1170 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1171 F(225000000, P_GCC_GPLL5_OUT_MAIN, 4, 0, 0), 1172 F(450000000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), 1173 { } 1174 }; 1175 1176 static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 1177 .cmd_rcgr = 0x77034, 1178 .mnd_width = 8, 1179 .hid_width = 5, 1180 .parent_map = gcc_parent_map_5, 1181 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, 1182 .hw_clk_ctrl = true, 1183 .clkr.hw.init = &(const struct clk_init_data) { 1184 .name = "gcc_ufs_phy_axi_clk_src", 1185 .parent_data = gcc_parent_data_5, 1186 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1187 .flags = CLK_SET_RATE_PARENT, 1188 .ops = &clk_rcg2_shared_ops, 1189 }, 1190 }; 1191 1192 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { 1193 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1194 F(225000000, P_GCC_GPLL5_OUT_MAIN, 4, 0, 0), 1195 F(450000000, P_GCC_GPLL5_OUT_MAIN, 2, 0, 0), 1196 { } 1197 }; 1198 1199 static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 1200 .cmd_rcgr = 0x7708c, 1201 .mnd_width = 0, 1202 .hid_width = 5, 1203 .parent_map = gcc_parent_map_5, 1204 .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, 1205 .hw_clk_ctrl = true, 1206 .clkr.hw.init = &(const struct clk_init_data) { 1207 .name = "gcc_ufs_phy_ice_core_clk_src", 1208 .parent_data = gcc_parent_data_5, 1209 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1210 .flags = CLK_SET_RATE_PARENT, 1211 .ops = &clk_rcg2_shared_ops, 1212 }, 1213 }; 1214 1215 static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { 1216 F(9600000, P_BI_TCXO, 2, 0, 0), 1217 F(19200000, P_BI_TCXO, 1, 0, 0), 1218 { } 1219 }; 1220 1221 static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 1222 .cmd_rcgr = 0x770c0, 1223 .mnd_width = 0, 1224 .hid_width = 5, 1225 .parent_map = gcc_parent_map_3, 1226 .freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src, 1227 .hw_clk_ctrl = true, 1228 .clkr.hw.init = &(const struct clk_init_data) { 1229 .name = "gcc_ufs_phy_phy_aux_clk_src", 1230 .parent_data = gcc_parent_data_3, 1231 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 1232 .flags = CLK_SET_RATE_PARENT, 1233 .ops = &clk_rcg2_shared_ops, 1234 }, 1235 }; 1236 1237 static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_5_core_clk_src[] = { 1238 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 1239 F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), 1240 F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), 1241 F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), 1242 { } 1243 }; 1244 1245 static struct clk_rcg2 gcc_ufs_phy_unipro_5_core_clk_src = { 1246 .cmd_rcgr = 0x770a4, 1247 .mnd_width = 0, 1248 .hid_width = 5, 1249 .parent_map = gcc_parent_map_5, 1250 .freq_tbl = ftbl_gcc_ufs_phy_unipro_5_core_clk_src, 1251 .hw_clk_ctrl = true, 1252 .clkr.hw.init = &(const struct clk_init_data) { 1253 .name = "gcc_ufs_phy_unipro_5_core_clk_src", 1254 .parent_data = gcc_parent_data_5, 1255 .num_parents = ARRAY_SIZE(gcc_parent_data_5), 1256 .flags = CLK_SET_RATE_PARENT, 1257 .ops = &clk_rcg2_shared_ops, 1258 }, 1259 }; 1260 1261 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { 1262 F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), 1263 F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), 1264 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 1265 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 1266 { } 1267 }; 1268 1269 static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 1270 .cmd_rcgr = 0x39034, 1271 .mnd_width = 8, 1272 .hid_width = 5, 1273 .parent_map = gcc_parent_map_0, 1274 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, 1275 .hw_clk_ctrl = true, 1276 .clkr.hw.init = &(const struct clk_init_data) { 1277 .name = "gcc_usb30_prim_master_clk_src", 1278 .parent_data = gcc_parent_data_0, 1279 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1280 .flags = CLK_SET_RATE_PARENT, 1281 .ops = &clk_rcg2_shared_no_init_park_ops, 1282 }, 1283 }; 1284 1285 static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 1286 .cmd_rcgr = 0x3904c, 1287 .mnd_width = 0, 1288 .hid_width = 5, 1289 .parent_map = gcc_parent_map_0, 1290 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1291 .hw_clk_ctrl = true, 1292 .clkr.hw.init = &(const struct clk_init_data) { 1293 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1294 .parent_data = gcc_parent_data_0, 1295 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 1296 .flags = CLK_SET_RATE_PARENT, 1297 .ops = &clk_rcg2_shared_no_init_park_ops, 1298 }, 1299 }; 1300 1301 static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 1302 .cmd_rcgr = 0x39078, 1303 .mnd_width = 0, 1304 .hid_width = 5, 1305 .parent_map = gcc_parent_map_4, 1306 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, 1307 .hw_clk_ctrl = true, 1308 .clkr.hw.init = &(const struct clk_init_data) { 1309 .name = "gcc_usb3_prim_phy_aux_clk_src", 1310 .parent_data = gcc_parent_data_4, 1311 .num_parents = ARRAY_SIZE(gcc_parent_data_4), 1312 .flags = CLK_SET_RATE_PARENT, 1313 .ops = &clk_rcg2_shared_no_init_park_ops, 1314 }, 1315 }; 1316 1317 static struct clk_regmap_div gcc_pcie_0_pipe_div_clk_src = { 1318 .reg = 0x6b0a4, 1319 .shift = 0, 1320 .width = 4, 1321 .clkr.hw.init = &(const struct clk_init_data) { 1322 .name = "gcc_pcie_0_pipe_div_clk_src", 1323 .parent_hws = (const struct clk_hw*[]) { 1324 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1325 }, 1326 .num_parents = 1, 1327 .flags = CLK_SET_RATE_PARENT, 1328 .ops = &clk_regmap_div_ro_ops, 1329 }, 1330 }; 1331 1332 static struct clk_regmap_div gcc_pcie_1_pipe_div_clk_src = { 1333 .reg = 0x670a0, 1334 .shift = 0, 1335 .width = 4, 1336 .clkr.hw.init = &(const struct clk_init_data) { 1337 .name = "gcc_pcie_1_pipe_div_clk_src", 1338 .parent_hws = (const struct clk_hw*[]) { 1339 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1340 }, 1341 .num_parents = 1, 1342 .flags = CLK_SET_RATE_PARENT, 1343 .ops = &clk_regmap_div_ro_ops, 1344 }, 1345 }; 1346 1347 static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = { 1348 .reg = 0x1828c, 1349 .shift = 0, 1350 .width = 4, 1351 .clkr.hw.init = &(const struct clk_init_data) { 1352 .name = "gcc_qupv3_wrap1_s2_clk_src", 1353 .parent_hws = (const struct clk_hw*[]) { 1354 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 1355 }, 1356 .num_parents = 1, 1357 .flags = CLK_SET_RATE_PARENT, 1358 .ops = &clk_regmap_div_ro_ops, 1359 }, 1360 }; 1361 1362 static struct clk_regmap_div gcc_qupv3_wrap3_s1_clk_src = { 1363 .reg = 0xa8154, 1364 .shift = 0, 1365 .width = 4, 1366 .clkr.hw.init = &(const struct clk_init_data) { 1367 .name = "gcc_qupv3_wrap3_s1_clk_src", 1368 .parent_hws = (const struct clk_hw*[]) { 1369 &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, 1370 }, 1371 .num_parents = 1, 1372 .flags = CLK_SET_RATE_PARENT, 1373 .ops = &clk_regmap_div_ro_ops, 1374 }, 1375 }; 1376 1377 static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { 1378 .reg = 0x39064, 1379 .shift = 0, 1380 .width = 4, 1381 .clkr.hw.init = &(const struct clk_init_data) { 1382 .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", 1383 .parent_hws = (const struct clk_hw*[]) { 1384 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, 1385 }, 1386 .num_parents = 1, 1387 .flags = CLK_SET_RATE_PARENT, 1388 .ops = &clk_regmap_div_ro_ops, 1389 }, 1390 }; 1391 1392 static struct clk_branch gcc_aggre_noc_pcie_axi_clk = { 1393 .halt_reg = 0x10068, 1394 .halt_check = BRANCH_HALT_SKIP, 1395 .hwcg_reg = 0x10068, 1396 .hwcg_bit = 1, 1397 .clkr = { 1398 .enable_reg = 0x52000, 1399 .enable_mask = BIT(24), 1400 .hw.init = &(const struct clk_init_data) { 1401 .name = "gcc_aggre_noc_pcie_axi_clk", 1402 .ops = &clk_branch2_ops, 1403 }, 1404 }, 1405 }; 1406 1407 static struct clk_branch gcc_aggre_stardustnoc_usb3_prim_axi_clk = { 1408 .halt_reg = 0x39094, 1409 .halt_check = BRANCH_HALT_VOTED, 1410 .hwcg_reg = 0x39094, 1411 .hwcg_bit = 1, 1412 .clkr = { 1413 .enable_reg = 0x39094, 1414 .enable_mask = BIT(0), 1415 .hw.init = &(const struct clk_init_data) { 1416 .name = "gcc_aggre_stardustnoc_usb3_prim_axi_clk", 1417 .parent_hws = (const struct clk_hw*[]) { 1418 &gcc_usb30_prim_master_clk_src.clkr.hw, 1419 }, 1420 .num_parents = 1, 1421 .flags = CLK_SET_RATE_PARENT, 1422 .ops = &clk_branch2_ops, 1423 }, 1424 }, 1425 }; 1426 1427 static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 1428 .halt_reg = 0x770f0, 1429 .halt_check = BRANCH_HALT_VOTED, 1430 .hwcg_reg = 0x770f0, 1431 .hwcg_bit = 1, 1432 .clkr = { 1433 .enable_reg = 0x770f0, 1434 .enable_mask = BIT(0), 1435 .hw.init = &(const struct clk_init_data) { 1436 .name = "gcc_aggre_ufs_phy_axi_clk", 1437 .parent_hws = (const struct clk_hw*[]) { 1438 &gcc_ufs_phy_axi_clk_src.clkr.hw, 1439 }, 1440 .num_parents = 1, 1441 .flags = CLK_SET_RATE_PARENT, 1442 .ops = &clk_branch2_ops, 1443 }, 1444 }, 1445 }; 1446 1447 static struct clk_branch gcc_boot_rom_ahb_clk = { 1448 .halt_reg = 0x38004, 1449 .halt_check = BRANCH_HALT_VOTED, 1450 .hwcg_reg = 0x38004, 1451 .hwcg_bit = 1, 1452 .clkr = { 1453 .enable_reg = 0x52010, 1454 .enable_mask = BIT(18), 1455 .hw.init = &(const struct clk_init_data) { 1456 .name = "gcc_boot_rom_ahb_clk", 1457 .ops = &clk_branch2_ops, 1458 }, 1459 }, 1460 }; 1461 1462 static struct clk_branch gcc_camera_hf_axi_clk = { 1463 .halt_reg = 0x26014, 1464 .halt_check = BRANCH_HALT_SKIP, 1465 .hwcg_reg = 0x26014, 1466 .hwcg_bit = 1, 1467 .clkr = { 1468 .enable_reg = 0x26014, 1469 .enable_mask = BIT(0), 1470 .hw.init = &(const struct clk_init_data) { 1471 .name = "gcc_camera_hf_axi_clk", 1472 .ops = &clk_branch2_ops, 1473 }, 1474 }, 1475 }; 1476 1477 static struct clk_branch gcc_camera_sf_axi_clk = { 1478 .halt_reg = 0x2601c, 1479 .halt_check = BRANCH_HALT_SKIP, 1480 .hwcg_reg = 0x2601c, 1481 .hwcg_bit = 1, 1482 .clkr = { 1483 .enable_reg = 0x2601c, 1484 .enable_mask = BIT(0), 1485 .hw.init = &(const struct clk_init_data) { 1486 .name = "gcc_camera_sf_axi_clk", 1487 .ops = &clk_branch2_ops, 1488 }, 1489 }, 1490 }; 1491 1492 static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = { 1493 .halt_reg = 0x10050, 1494 .halt_check = BRANCH_HALT_SKIP, 1495 .hwcg_reg = 0x10050, 1496 .hwcg_bit = 1, 1497 .clkr = { 1498 .enable_reg = 0x52000, 1499 .enable_mask = BIT(20), 1500 .hw.init = &(const struct clk_init_data) { 1501 .name = "gcc_cfg_noc_pcie_anoc_ahb_clk", 1502 .ops = &clk_branch2_ops, 1503 }, 1504 }, 1505 }; 1506 1507 static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { 1508 .halt_reg = 0x39090, 1509 .halt_check = BRANCH_HALT_VOTED, 1510 .hwcg_reg = 0x39090, 1511 .hwcg_bit = 1, 1512 .clkr = { 1513 .enable_reg = 0x39090, 1514 .enable_mask = BIT(0), 1515 .hw.init = &(const struct clk_init_data) { 1516 .name = "gcc_cfg_noc_usb3_prim_axi_clk", 1517 .parent_hws = (const struct clk_hw*[]) { 1518 &gcc_usb30_prim_master_clk_src.clkr.hw, 1519 }, 1520 .num_parents = 1, 1521 .flags = CLK_SET_RATE_PARENT, 1522 .ops = &clk_branch2_ops, 1523 }, 1524 }, 1525 }; 1526 1527 static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = { 1528 .halt_reg = 0x10058, 1529 .halt_check = BRANCH_HALT_VOTED, 1530 .clkr = { 1531 .enable_reg = 0x52008, 1532 .enable_mask = BIT(6), 1533 .hw.init = &(const struct clk_init_data) { 1534 .name = "gcc_cnoc_pcie_sf_axi_clk", 1535 .ops = &clk_branch2_ops, 1536 }, 1537 }, 1538 }; 1539 1540 static struct clk_branch gcc_eva_axi0_clk = { 1541 .halt_reg = 0x9f008, 1542 .halt_check = BRANCH_HALT_SKIP, 1543 .hwcg_reg = 0x9f008, 1544 .hwcg_bit = 1, 1545 .clkr = { 1546 .enable_reg = 0x9f008, 1547 .enable_mask = BIT(0), 1548 .hw.init = &(const struct clk_init_data) { 1549 .name = "gcc_eva_axi0_clk", 1550 .ops = &clk_branch2_ops, 1551 }, 1552 }, 1553 }; 1554 1555 static struct clk_branch gcc_eva_axi0c_clk = { 1556 .halt_reg = 0x9f010, 1557 .halt_check = BRANCH_HALT_SKIP, 1558 .hwcg_reg = 0x9f010, 1559 .hwcg_bit = 1, 1560 .clkr = { 1561 .enable_reg = 0x9f010, 1562 .enable_mask = BIT(0), 1563 .hw.init = &(const struct clk_init_data) { 1564 .name = "gcc_eva_axi0c_clk", 1565 .ops = &clk_branch2_ops, 1566 }, 1567 }, 1568 }; 1569 1570 static struct clk_branch gcc_gp1_clk = { 1571 .halt_reg = 0x64000, 1572 .halt_check = BRANCH_HALT, 1573 .clkr = { 1574 .enable_reg = 0x64000, 1575 .enable_mask = BIT(0), 1576 .hw.init = &(const struct clk_init_data) { 1577 .name = "gcc_gp1_clk", 1578 .parent_hws = (const struct clk_hw*[]) { 1579 &gcc_gp1_clk_src.clkr.hw, 1580 }, 1581 .num_parents = 1, 1582 .flags = CLK_SET_RATE_PARENT, 1583 .ops = &clk_branch2_ops, 1584 }, 1585 }, 1586 }; 1587 1588 static struct clk_branch gcc_gp2_clk = { 1589 .halt_reg = 0x65000, 1590 .halt_check = BRANCH_HALT, 1591 .clkr = { 1592 .enable_reg = 0x65000, 1593 .enable_mask = BIT(0), 1594 .hw.init = &(const struct clk_init_data) { 1595 .name = "gcc_gp2_clk", 1596 .parent_hws = (const struct clk_hw*[]) { 1597 &gcc_gp2_clk_src.clkr.hw, 1598 }, 1599 .num_parents = 1, 1600 .flags = CLK_SET_RATE_PARENT, 1601 .ops = &clk_branch2_ops, 1602 }, 1603 }, 1604 }; 1605 1606 static struct clk_branch gcc_gp3_clk = { 1607 .halt_reg = 0x66000, 1608 .halt_check = BRANCH_HALT, 1609 .clkr = { 1610 .enable_reg = 0x66000, 1611 .enable_mask = BIT(0), 1612 .hw.init = &(const struct clk_init_data) { 1613 .name = "gcc_gp3_clk", 1614 .parent_hws = (const struct clk_hw*[]) { 1615 &gcc_gp3_clk_src.clkr.hw, 1616 }, 1617 .num_parents = 1, 1618 .flags = CLK_SET_RATE_PARENT, 1619 .ops = &clk_branch2_ops, 1620 }, 1621 }, 1622 }; 1623 1624 static struct clk_branch gcc_gpu_gemnoc_gfx_clk = { 1625 .halt_reg = 0x71010, 1626 .halt_check = BRANCH_HALT_VOTED, 1627 .hwcg_reg = 0x71010, 1628 .hwcg_bit = 1, 1629 .clkr = { 1630 .enable_reg = 0x71010, 1631 .enable_mask = BIT(0), 1632 .hw.init = &(const struct clk_init_data) { 1633 .name = "gcc_gpu_gemnoc_gfx_clk", 1634 .ops = &clk_branch2_ops, 1635 }, 1636 }, 1637 }; 1638 1639 static struct clk_branch gcc_gpu_gpll0_clk_src = { 1640 .halt_check = BRANCH_HALT_DELAY, 1641 .clkr = { 1642 .enable_reg = 0x52000, 1643 .enable_mask = BIT(15), 1644 .hw.init = &(const struct clk_init_data) { 1645 .name = "gcc_gpu_gpll0_clk_src", 1646 .parent_hws = (const struct clk_hw*[]) { 1647 &gcc_gpll0.clkr.hw, 1648 }, 1649 .num_parents = 1, 1650 .flags = CLK_SET_RATE_PARENT, 1651 .ops = &clk_branch2_ops, 1652 }, 1653 }, 1654 }; 1655 1656 static struct clk_branch gcc_gpu_gpll0_div_clk_src = { 1657 .halt_check = BRANCH_HALT_DELAY, 1658 .clkr = { 1659 .enable_reg = 0x52000, 1660 .enable_mask = BIT(16), 1661 .hw.init = &(const struct clk_init_data) { 1662 .name = "gcc_gpu_gpll0_div_clk_src", 1663 .parent_hws = (const struct clk_hw*[]) { 1664 &gcc_gpll0_out_even.clkr.hw, 1665 }, 1666 .num_parents = 1, 1667 .flags = CLK_SET_RATE_PARENT, 1668 .ops = &clk_branch2_ops, 1669 }, 1670 }, 1671 }; 1672 1673 static struct clk_branch gcc_gpu_smmu_vote_clk = { 1674 .halt_reg = 0x7d000, 1675 .halt_check = BRANCH_HALT_VOTED, 1676 .clkr = { 1677 .enable_reg = 0x7d000, 1678 .enable_mask = BIT(0), 1679 .hw.init = &(const struct clk_init_data) { 1680 .name = "gcc_gpu_smmu_vote_clk", 1681 .ops = &clk_branch2_ops, 1682 }, 1683 }, 1684 }; 1685 1686 static struct clk_branch gcc_mmu_tcu_vote_clk = { 1687 .halt_reg = 0x7d02c, 1688 .halt_check = BRANCH_HALT_VOTED, 1689 .clkr = { 1690 .enable_reg = 0x7d02c, 1691 .enable_mask = BIT(0), 1692 .hw.init = &(const struct clk_init_data) { 1693 .name = "gcc_mmu_tcu_vote_clk", 1694 .ops = &clk_branch2_ops, 1695 }, 1696 }, 1697 }; 1698 1699 static struct clk_branch gcc_pcie_0_aux_clk = { 1700 .halt_reg = 0x6b044, 1701 .halt_check = BRANCH_HALT_VOTED, 1702 .hwcg_reg = 0x6b044, 1703 .hwcg_bit = 1, 1704 .clkr = { 1705 .enable_reg = 0x52020, 1706 .enable_mask = BIT(4), 1707 .hw.init = &(const struct clk_init_data) { 1708 .name = "gcc_pcie_0_aux_clk", 1709 .parent_hws = (const struct clk_hw*[]) { 1710 &gcc_pcie_0_aux_clk_src.clkr.hw, 1711 }, 1712 .num_parents = 1, 1713 .flags = CLK_SET_RATE_PARENT, 1714 .ops = &clk_branch2_ops, 1715 }, 1716 }, 1717 }; 1718 1719 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 1720 .halt_reg = 0x6b040, 1721 .halt_check = BRANCH_HALT_VOTED, 1722 .hwcg_reg = 0x6b040, 1723 .hwcg_bit = 1, 1724 .clkr = { 1725 .enable_reg = 0x52020, 1726 .enable_mask = BIT(3), 1727 .hw.init = &(const struct clk_init_data) { 1728 .name = "gcc_pcie_0_cfg_ahb_clk", 1729 .ops = &clk_branch2_ops, 1730 }, 1731 }, 1732 }; 1733 1734 static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 1735 .halt_reg = 0x6b030, 1736 .halt_check = BRANCH_HALT_SKIP, 1737 .hwcg_reg = 0x6b030, 1738 .hwcg_bit = 1, 1739 .clkr = { 1740 .enable_reg = 0x52020, 1741 .enable_mask = BIT(2), 1742 .hw.init = &(const struct clk_init_data) { 1743 .name = "gcc_pcie_0_mstr_axi_clk", 1744 .ops = &clk_branch2_ops, 1745 }, 1746 }, 1747 }; 1748 1749 static struct clk_branch gcc_pcie_0_phy_aux_clk = { 1750 .halt_reg = 0x6b054, 1751 .halt_check = BRANCH_HALT_VOTED, 1752 .hwcg_reg = 0x6b054, 1753 .hwcg_bit = 1, 1754 .clkr = { 1755 .enable_reg = 0x52020, 1756 .enable_mask = BIT(5), 1757 .hw.init = &(const struct clk_init_data) { 1758 .name = "gcc_pcie_0_phy_aux_clk", 1759 .parent_hws = (const struct clk_hw*[]) { 1760 &gcc_pcie_0_phy_aux_clk_src.clkr.hw, 1761 }, 1762 .num_parents = 1, 1763 .flags = CLK_SET_RATE_PARENT, 1764 .ops = &clk_branch2_ops, 1765 }, 1766 }, 1767 }; 1768 1769 static struct clk_branch gcc_pcie_0_phy_rchng_clk = { 1770 .halt_reg = 0x6b084, 1771 .halt_check = BRANCH_HALT_VOTED, 1772 .hwcg_reg = 0x6b084, 1773 .hwcg_bit = 1, 1774 .clkr = { 1775 .enable_reg = 0x52020, 1776 .enable_mask = BIT(8), 1777 .hw.init = &(const struct clk_init_data) { 1778 .name = "gcc_pcie_0_phy_rchng_clk", 1779 .parent_hws = (const struct clk_hw*[]) { 1780 &gcc_pcie_0_phy_rchng_clk_src.clkr.hw, 1781 }, 1782 .num_parents = 1, 1783 .flags = CLK_SET_RATE_PARENT, 1784 .ops = &clk_branch2_ops, 1785 }, 1786 }, 1787 }; 1788 1789 static struct clk_branch gcc_pcie_0_pipe_clk = { 1790 .halt_reg = 0x6b074, 1791 .halt_check = BRANCH_HALT_SKIP, 1792 .hwcg_reg = 0x6b074, 1793 .hwcg_bit = 1, 1794 .clkr = { 1795 .enable_reg = 0x52020, 1796 .enable_mask = BIT(7), 1797 .hw.init = &(const struct clk_init_data) { 1798 .name = "gcc_pcie_0_pipe_clk", 1799 .parent_hws = (const struct clk_hw*[]) { 1800 &gcc_pcie_0_pipe_clk_src.clkr.hw, 1801 }, 1802 .num_parents = 1, 1803 .flags = CLK_SET_RATE_PARENT, 1804 .ops = &clk_branch2_ops, 1805 }, 1806 }, 1807 }; 1808 1809 static struct clk_branch gcc_pcie_0_pipe_div2_clk = { 1810 .halt_reg = 0x6b064, 1811 .halt_check = BRANCH_HALT_SKIP, 1812 .hwcg_reg = 0x6b064, 1813 .hwcg_bit = 1, 1814 .clkr = { 1815 .enable_reg = 0x52020, 1816 .enable_mask = BIT(6), 1817 .hw.init = &(const struct clk_init_data) { 1818 .name = "gcc_pcie_0_pipe_div2_clk", 1819 .parent_hws = (const struct clk_hw*[]) { 1820 &gcc_pcie_0_pipe_div_clk_src.clkr.hw, 1821 }, 1822 .num_parents = 1, 1823 .flags = CLK_SET_RATE_PARENT, 1824 .ops = &clk_branch2_ops, 1825 }, 1826 }, 1827 }; 1828 1829 static struct clk_branch gcc_pcie_0_slv_axi_clk = { 1830 .halt_reg = 0x6b020, 1831 .halt_check = BRANCH_HALT_VOTED, 1832 .hwcg_reg = 0x6b020, 1833 .hwcg_bit = 1, 1834 .clkr = { 1835 .enable_reg = 0x52020, 1836 .enable_mask = BIT(1), 1837 .hw.init = &(const struct clk_init_data) { 1838 .name = "gcc_pcie_0_slv_axi_clk", 1839 .ops = &clk_branch2_ops, 1840 }, 1841 }, 1842 }; 1843 1844 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { 1845 .halt_reg = 0x6b01c, 1846 .halt_check = BRANCH_HALT_VOTED, 1847 .hwcg_reg = 0x6b01c, 1848 .hwcg_bit = 1, 1849 .clkr = { 1850 .enable_reg = 0x52020, 1851 .enable_mask = BIT(0), 1852 .hw.init = &(const struct clk_init_data) { 1853 .name = "gcc_pcie_0_slv_q2a_axi_clk", 1854 .ops = &clk_branch2_ops, 1855 }, 1856 }, 1857 }; 1858 1859 static struct clk_branch gcc_pcie_1_aux_clk = { 1860 .halt_reg = 0x67040, 1861 .halt_check = BRANCH_HALT_VOTED, 1862 .clkr = { 1863 .enable_reg = 0x52010, 1864 .enable_mask = BIT(10), 1865 .hw.init = &(const struct clk_init_data) { 1866 .name = "gcc_pcie_1_aux_clk", 1867 .parent_hws = (const struct clk_hw*[]) { 1868 &gcc_pcie_1_aux_clk_src.clkr.hw, 1869 }, 1870 .num_parents = 1, 1871 .flags = CLK_SET_RATE_PARENT, 1872 .ops = &clk_branch2_ops, 1873 }, 1874 }, 1875 }; 1876 1877 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 1878 .halt_reg = 0x6703c, 1879 .halt_check = BRANCH_HALT_VOTED, 1880 .hwcg_reg = 0x6703c, 1881 .hwcg_bit = 1, 1882 .clkr = { 1883 .enable_reg = 0x52010, 1884 .enable_mask = BIT(9), 1885 .hw.init = &(const struct clk_init_data) { 1886 .name = "gcc_pcie_1_cfg_ahb_clk", 1887 .ops = &clk_branch2_ops, 1888 }, 1889 }, 1890 }; 1891 1892 static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 1893 .halt_reg = 0x6702c, 1894 .halt_check = BRANCH_HALT_SKIP, 1895 .hwcg_reg = 0x6702c, 1896 .hwcg_bit = 1, 1897 .clkr = { 1898 .enable_reg = 0x52008, 1899 .enable_mask = BIT(17), 1900 .hw.init = &(const struct clk_init_data) { 1901 .name = "gcc_pcie_1_mstr_axi_clk", 1902 .ops = &clk_branch2_ops, 1903 }, 1904 }, 1905 }; 1906 1907 static struct clk_branch gcc_pcie_1_phy_aux_clk = { 1908 .halt_reg = 0x67050, 1909 .halt_check = BRANCH_HALT_VOTED, 1910 .clkr = { 1911 .enable_reg = 0x52010, 1912 .enable_mask = BIT(14), 1913 .hw.init = &(const struct clk_init_data) { 1914 .name = "gcc_pcie_1_phy_aux_clk", 1915 .parent_hws = (const struct clk_hw*[]) { 1916 &gcc_pcie_1_phy_aux_clk_src.clkr.hw, 1917 }, 1918 .num_parents = 1, 1919 .flags = CLK_SET_RATE_PARENT, 1920 .ops = &clk_branch2_ops, 1921 }, 1922 }, 1923 }; 1924 1925 static struct clk_branch gcc_pcie_1_phy_rchng_clk = { 1926 .halt_reg = 0x67080, 1927 .halt_check = BRANCH_HALT_VOTED, 1928 .clkr = { 1929 .enable_reg = 0x52010, 1930 .enable_mask = BIT(26), 1931 .hw.init = &(const struct clk_init_data) { 1932 .name = "gcc_pcie_1_phy_rchng_clk", 1933 .parent_hws = (const struct clk_hw*[]) { 1934 &gcc_pcie_1_phy_rchng_clk_src.clkr.hw, 1935 }, 1936 .num_parents = 1, 1937 .flags = CLK_SET_RATE_PARENT, 1938 .ops = &clk_branch2_ops, 1939 }, 1940 }, 1941 }; 1942 1943 static struct clk_branch gcc_pcie_1_pipe_clk = { 1944 .halt_reg = 0x67070, 1945 .halt_check = BRANCH_HALT_SKIP, 1946 .clkr = { 1947 .enable_reg = 0x52010, 1948 .enable_mask = BIT(17), 1949 .hw.init = &(const struct clk_init_data) { 1950 .name = "gcc_pcie_1_pipe_clk", 1951 .parent_hws = (const struct clk_hw*[]) { 1952 &gcc_pcie_1_pipe_clk_src.clkr.hw, 1953 }, 1954 .num_parents = 1, 1955 .flags = CLK_SET_RATE_PARENT, 1956 .ops = &clk_branch2_ops, 1957 }, 1958 }, 1959 }; 1960 1961 static struct clk_branch gcc_pcie_1_pipe_div2_clk = { 1962 .halt_reg = 0x67060, 1963 .halt_check = BRANCH_HALT_SKIP, 1964 .clkr = { 1965 .enable_reg = 0x52010, 1966 .enable_mask = BIT(15), 1967 .hw.init = &(const struct clk_init_data) { 1968 .name = "gcc_pcie_1_pipe_div2_clk", 1969 .parent_hws = (const struct clk_hw*[]) { 1970 &gcc_pcie_1_pipe_div_clk_src.clkr.hw, 1971 }, 1972 .num_parents = 1, 1973 .flags = CLK_SET_RATE_PARENT, 1974 .ops = &clk_branch2_ops, 1975 }, 1976 }, 1977 }; 1978 1979 static struct clk_branch gcc_pcie_1_slv_axi_clk = { 1980 .halt_reg = 0x6701c, 1981 .halt_check = BRANCH_HALT_VOTED, 1982 .hwcg_reg = 0x6701c, 1983 .hwcg_bit = 1, 1984 .clkr = { 1985 .enable_reg = 0x52008, 1986 .enable_mask = BIT(16), 1987 .hw.init = &(const struct clk_init_data) { 1988 .name = "gcc_pcie_1_slv_axi_clk", 1989 .ops = &clk_branch2_ops, 1990 }, 1991 }, 1992 }; 1993 1994 static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { 1995 .halt_reg = 0x67018, 1996 .halt_check = BRANCH_HALT_VOTED, 1997 .clkr = { 1998 .enable_reg = 0x52008, 1999 .enable_mask = BIT(15), 2000 .hw.init = &(const struct clk_init_data) { 2001 .name = "gcc_pcie_1_slv_q2a_axi_clk", 2002 .ops = &clk_branch2_ops, 2003 }, 2004 }, 2005 }; 2006 2007 static struct clk_branch gcc_pdm2_clk = { 2008 .halt_reg = 0x3300c, 2009 .halt_check = BRANCH_HALT, 2010 .clkr = { 2011 .enable_reg = 0x3300c, 2012 .enable_mask = BIT(0), 2013 .hw.init = &(const struct clk_init_data) { 2014 .name = "gcc_pdm2_clk", 2015 .parent_hws = (const struct clk_hw*[]) { 2016 &gcc_pdm2_clk_src.clkr.hw, 2017 }, 2018 .num_parents = 1, 2019 .flags = CLK_SET_RATE_PARENT, 2020 .ops = &clk_branch2_ops, 2021 }, 2022 }, 2023 }; 2024 2025 static struct clk_branch gcc_pdm_ahb_clk = { 2026 .halt_reg = 0x33004, 2027 .halt_check = BRANCH_HALT_VOTED, 2028 .hwcg_reg = 0x33004, 2029 .hwcg_bit = 1, 2030 .clkr = { 2031 .enable_reg = 0x33004, 2032 .enable_mask = BIT(0), 2033 .hw.init = &(const struct clk_init_data) { 2034 .name = "gcc_pdm_ahb_clk", 2035 .ops = &clk_branch2_ops, 2036 }, 2037 }, 2038 }; 2039 2040 static struct clk_branch gcc_pdm_xo4_clk = { 2041 .halt_reg = 0x33008, 2042 .halt_check = BRANCH_HALT, 2043 .clkr = { 2044 .enable_reg = 0x33008, 2045 .enable_mask = BIT(0), 2046 .hw.init = &(const struct clk_init_data) { 2047 .name = "gcc_pdm_xo4_clk", 2048 .ops = &clk_branch2_ops, 2049 }, 2050 }, 2051 }; 2052 2053 static struct clk_branch gcc_qupv3_i2c_core_clk = { 2054 .halt_reg = 0x23004, 2055 .halt_check = BRANCH_HALT_VOTED, 2056 .clkr = { 2057 .enable_reg = 0x52008, 2058 .enable_mask = BIT(8), 2059 .hw.init = &(const struct clk_init_data) { 2060 .name = "gcc_qupv3_i2c_core_clk", 2061 .ops = &clk_branch2_ops, 2062 }, 2063 }, 2064 }; 2065 2066 static struct clk_branch gcc_qupv3_i2c_s0_clk = { 2067 .halt_reg = 0x17004, 2068 .halt_check = BRANCH_HALT_VOTED, 2069 .clkr = { 2070 .enable_reg = 0x52008, 2071 .enable_mask = BIT(10), 2072 .hw.init = &(const struct clk_init_data) { 2073 .name = "gcc_qupv3_i2c_s0_clk", 2074 .parent_hws = (const struct clk_hw*[]) { 2075 &gcc_qupv3_i2c_s0_clk_src.clkr.hw, 2076 }, 2077 .num_parents = 1, 2078 .flags = CLK_SET_RATE_PARENT, 2079 .ops = &clk_branch2_ops, 2080 }, 2081 }, 2082 }; 2083 2084 static struct clk_branch gcc_qupv3_i2c_s1_clk = { 2085 .halt_reg = 0x17020, 2086 .halt_check = BRANCH_HALT_VOTED, 2087 .clkr = { 2088 .enable_reg = 0x52008, 2089 .enable_mask = BIT(11), 2090 .hw.init = &(const struct clk_init_data) { 2091 .name = "gcc_qupv3_i2c_s1_clk", 2092 .parent_hws = (const struct clk_hw*[]) { 2093 &gcc_qupv3_i2c_s1_clk_src.clkr.hw, 2094 }, 2095 .num_parents = 1, 2096 .flags = CLK_SET_RATE_PARENT, 2097 .ops = &clk_branch2_ops, 2098 }, 2099 }, 2100 }; 2101 2102 static struct clk_branch gcc_qupv3_i2c_s2_clk = { 2103 .halt_reg = 0x1703c, 2104 .halt_check = BRANCH_HALT_VOTED, 2105 .clkr = { 2106 .enable_reg = 0x52008, 2107 .enable_mask = BIT(12), 2108 .hw.init = &(const struct clk_init_data) { 2109 .name = "gcc_qupv3_i2c_s2_clk", 2110 .parent_hws = (const struct clk_hw*[]) { 2111 &gcc_qupv3_i2c_s2_clk_src.clkr.hw, 2112 }, 2113 .num_parents = 1, 2114 .flags = CLK_SET_RATE_PARENT, 2115 .ops = &clk_branch2_ops, 2116 }, 2117 }, 2118 }; 2119 2120 static struct clk_branch gcc_qupv3_i2c_s3_clk = { 2121 .halt_reg = 0x17058, 2122 .halt_check = BRANCH_HALT_VOTED, 2123 .clkr = { 2124 .enable_reg = 0x52008, 2125 .enable_mask = BIT(13), 2126 .hw.init = &(const struct clk_init_data) { 2127 .name = "gcc_qupv3_i2c_s3_clk", 2128 .parent_hws = (const struct clk_hw*[]) { 2129 &gcc_qupv3_i2c_s3_clk_src.clkr.hw, 2130 }, 2131 .num_parents = 1, 2132 .flags = CLK_SET_RATE_PARENT, 2133 .ops = &clk_branch2_ops, 2134 }, 2135 }, 2136 }; 2137 2138 static struct clk_branch gcc_qupv3_i2c_s4_clk = { 2139 .halt_reg = 0x17074, 2140 .halt_check = BRANCH_HALT_VOTED, 2141 .clkr = { 2142 .enable_reg = 0x52008, 2143 .enable_mask = BIT(14), 2144 .hw.init = &(const struct clk_init_data) { 2145 .name = "gcc_qupv3_i2c_s4_clk", 2146 .parent_hws = (const struct clk_hw*[]) { 2147 &gcc_qupv3_i2c_s4_clk_src.clkr.hw, 2148 }, 2149 .num_parents = 1, 2150 .flags = CLK_SET_RATE_PARENT, 2151 .ops = &clk_branch2_ops, 2152 }, 2153 }, 2154 }; 2155 2156 static struct clk_branch gcc_qupv3_i2c_s_ahb_clk = { 2157 .halt_reg = 0x23000, 2158 .halt_check = BRANCH_HALT_VOTED, 2159 .hwcg_reg = 0x23000, 2160 .hwcg_bit = 1, 2161 .clkr = { 2162 .enable_reg = 0x52008, 2163 .enable_mask = BIT(7), 2164 .hw.init = &(const struct clk_init_data) { 2165 .name = "gcc_qupv3_i2c_s_ahb_clk", 2166 .ops = &clk_branch2_ops, 2167 }, 2168 }, 2169 }; 2170 2171 static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { 2172 .halt_reg = 0x2315c, 2173 .halt_check = BRANCH_HALT_VOTED, 2174 .clkr = { 2175 .enable_reg = 0x52008, 2176 .enable_mask = BIT(18), 2177 .hw.init = &(const struct clk_init_data) { 2178 .name = "gcc_qupv3_wrap1_core_2x_clk", 2179 .ops = &clk_branch2_ops, 2180 }, 2181 }, 2182 }; 2183 2184 static struct clk_branch gcc_qupv3_wrap1_core_clk = { 2185 .halt_reg = 0x23148, 2186 .halt_check = BRANCH_HALT_VOTED, 2187 .clkr = { 2188 .enable_reg = 0x52008, 2189 .enable_mask = BIT(19), 2190 .hw.init = &(const struct clk_init_data) { 2191 .name = "gcc_qupv3_wrap1_core_clk", 2192 .ops = &clk_branch2_ops, 2193 }, 2194 }, 2195 }; 2196 2197 static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = { 2198 .halt_reg = 0x188bc, 2199 .halt_check = BRANCH_HALT_VOTED, 2200 .clkr = { 2201 .enable_reg = 0x52010, 2202 .enable_mask = BIT(29), 2203 .hw.init = &(const struct clk_init_data) { 2204 .name = "gcc_qupv3_wrap1_qspi_ref_clk", 2205 .parent_hws = (const struct clk_hw*[]) { 2206 &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw, 2207 }, 2208 .num_parents = 1, 2209 .flags = CLK_SET_RATE_PARENT, 2210 .ops = &clk_branch2_ops, 2211 }, 2212 }, 2213 }; 2214 2215 static struct clk_branch gcc_qupv3_wrap1_s0_clk = { 2216 .halt_reg = 0x18004, 2217 .halt_check = BRANCH_HALT_VOTED, 2218 .clkr = { 2219 .enable_reg = 0x52008, 2220 .enable_mask = BIT(22), 2221 .hw.init = &(const struct clk_init_data) { 2222 .name = "gcc_qupv3_wrap1_s0_clk", 2223 .parent_hws = (const struct clk_hw*[]) { 2224 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, 2225 }, 2226 .num_parents = 1, 2227 .flags = CLK_SET_RATE_PARENT, 2228 .ops = &clk_branch2_ops, 2229 }, 2230 }, 2231 }; 2232 2233 static struct clk_branch gcc_qupv3_wrap1_s1_clk = { 2234 .halt_reg = 0x18140, 2235 .halt_check = BRANCH_HALT_VOTED, 2236 .clkr = { 2237 .enable_reg = 0x52008, 2238 .enable_mask = BIT(23), 2239 .hw.init = &(const struct clk_init_data) { 2240 .name = "gcc_qupv3_wrap1_s1_clk", 2241 .parent_hws = (const struct clk_hw*[]) { 2242 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, 2243 }, 2244 .num_parents = 1, 2245 .flags = CLK_SET_RATE_PARENT, 2246 .ops = &clk_branch2_ops, 2247 }, 2248 }, 2249 }; 2250 2251 static struct clk_branch gcc_qupv3_wrap1_s2_clk = { 2252 .halt_reg = 0x1827c, 2253 .halt_check = BRANCH_HALT_VOTED, 2254 .clkr = { 2255 .enable_reg = 0x52008, 2256 .enable_mask = BIT(24), 2257 .hw.init = &(const struct clk_init_data) { 2258 .name = "gcc_qupv3_wrap1_s2_clk", 2259 .parent_hws = (const struct clk_hw*[]) { 2260 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, 2261 }, 2262 .num_parents = 1, 2263 .flags = CLK_SET_RATE_PARENT, 2264 .ops = &clk_branch2_ops, 2265 }, 2266 }, 2267 }; 2268 2269 static struct clk_branch gcc_qupv3_wrap1_s3_clk = { 2270 .halt_reg = 0x18290, 2271 .halt_check = BRANCH_HALT_VOTED, 2272 .clkr = { 2273 .enable_reg = 0x52008, 2274 .enable_mask = BIT(25), 2275 .hw.init = &(const struct clk_init_data) { 2276 .name = "gcc_qupv3_wrap1_s3_clk", 2277 .parent_hws = (const struct clk_hw*[]) { 2278 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, 2279 }, 2280 .num_parents = 1, 2281 .flags = CLK_SET_RATE_PARENT, 2282 .ops = &clk_branch2_ops, 2283 }, 2284 }, 2285 }; 2286 2287 static struct clk_branch gcc_qupv3_wrap1_s4_clk = { 2288 .halt_reg = 0x183cc, 2289 .halt_check = BRANCH_HALT_VOTED, 2290 .clkr = { 2291 .enable_reg = 0x52008, 2292 .enable_mask = BIT(26), 2293 .hw.init = &(const struct clk_init_data) { 2294 .name = "gcc_qupv3_wrap1_s4_clk", 2295 .parent_hws = (const struct clk_hw*[]) { 2296 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, 2297 }, 2298 .num_parents = 1, 2299 .flags = CLK_SET_RATE_PARENT, 2300 .ops = &clk_branch2_ops, 2301 }, 2302 }, 2303 }; 2304 2305 static struct clk_branch gcc_qupv3_wrap1_s5_clk = { 2306 .halt_reg = 0x18508, 2307 .halt_check = BRANCH_HALT_VOTED, 2308 .clkr = { 2309 .enable_reg = 0x52008, 2310 .enable_mask = BIT(27), 2311 .hw.init = &(const struct clk_init_data) { 2312 .name = "gcc_qupv3_wrap1_s5_clk", 2313 .parent_hws = (const struct clk_hw*[]) { 2314 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, 2315 }, 2316 .num_parents = 1, 2317 .flags = CLK_SET_RATE_PARENT, 2318 .ops = &clk_branch2_ops, 2319 }, 2320 }, 2321 }; 2322 2323 static struct clk_branch gcc_qupv3_wrap1_s6_clk = { 2324 .halt_reg = 0x18644, 2325 .halt_check = BRANCH_HALT_VOTED, 2326 .clkr = { 2327 .enable_reg = 0x52008, 2328 .enable_mask = BIT(28), 2329 .hw.init = &(const struct clk_init_data) { 2330 .name = "gcc_qupv3_wrap1_s6_clk", 2331 .parent_hws = (const struct clk_hw*[]) { 2332 &gcc_qupv3_wrap1_s6_clk_src.clkr.hw, 2333 }, 2334 .num_parents = 1, 2335 .flags = CLK_SET_RATE_PARENT, 2336 .ops = &clk_branch2_ops, 2337 }, 2338 }, 2339 }; 2340 2341 static struct clk_branch gcc_qupv3_wrap1_s7_clk = { 2342 .halt_reg = 0x18780, 2343 .halt_check = BRANCH_HALT_VOTED, 2344 .clkr = { 2345 .enable_reg = 0x52010, 2346 .enable_mask = BIT(16), 2347 .hw.init = &(const struct clk_init_data) { 2348 .name = "gcc_qupv3_wrap1_s7_clk", 2349 .parent_hws = (const struct clk_hw*[]) { 2350 &gcc_qupv3_wrap1_s7_clk_src.clkr.hw, 2351 }, 2352 .num_parents = 1, 2353 .flags = CLK_SET_RATE_PARENT, 2354 .ops = &clk_branch2_ops, 2355 }, 2356 }, 2357 }; 2358 2359 static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { 2360 .halt_reg = 0x232b4, 2361 .halt_check = BRANCH_HALT_VOTED, 2362 .clkr = { 2363 .enable_reg = 0x52010, 2364 .enable_mask = BIT(3), 2365 .hw.init = &(const struct clk_init_data) { 2366 .name = "gcc_qupv3_wrap2_core_2x_clk", 2367 .ops = &clk_branch2_ops, 2368 }, 2369 }, 2370 }; 2371 2372 static struct clk_branch gcc_qupv3_wrap2_core_clk = { 2373 .halt_reg = 0x232a0, 2374 .halt_check = BRANCH_HALT_VOTED, 2375 .clkr = { 2376 .enable_reg = 0x52010, 2377 .enable_mask = BIT(0), 2378 .hw.init = &(const struct clk_init_data) { 2379 .name = "gcc_qupv3_wrap2_core_clk", 2380 .ops = &clk_branch2_ops, 2381 }, 2382 }, 2383 }; 2384 2385 static struct clk_branch gcc_qupv3_wrap2_s0_clk = { 2386 .halt_reg = 0x1e004, 2387 .halt_check = BRANCH_HALT_VOTED, 2388 .clkr = { 2389 .enable_reg = 0x52010, 2390 .enable_mask = BIT(4), 2391 .hw.init = &(const struct clk_init_data) { 2392 .name = "gcc_qupv3_wrap2_s0_clk", 2393 .parent_hws = (const struct clk_hw*[]) { 2394 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, 2395 }, 2396 .num_parents = 1, 2397 .flags = CLK_SET_RATE_PARENT, 2398 .ops = &clk_branch2_ops, 2399 }, 2400 }, 2401 }; 2402 2403 static struct clk_branch gcc_qupv3_wrap2_s1_clk = { 2404 .halt_reg = 0x1e148, 2405 .halt_check = BRANCH_HALT_VOTED, 2406 .clkr = { 2407 .enable_reg = 0x52010, 2408 .enable_mask = BIT(5), 2409 .hw.init = &(const struct clk_init_data) { 2410 .name = "gcc_qupv3_wrap2_s1_clk", 2411 .parent_hws = (const struct clk_hw*[]) { 2412 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, 2413 }, 2414 .num_parents = 1, 2415 .flags = CLK_SET_RATE_PARENT, 2416 .ops = &clk_branch2_ops, 2417 }, 2418 }, 2419 }; 2420 2421 static struct clk_branch gcc_qupv3_wrap2_s2_clk = { 2422 .halt_reg = 0x1e28c, 2423 .halt_check = BRANCH_HALT_VOTED, 2424 .clkr = { 2425 .enable_reg = 0x52010, 2426 .enable_mask = BIT(6), 2427 .hw.init = &(const struct clk_init_data) { 2428 .name = "gcc_qupv3_wrap2_s2_clk", 2429 .parent_hws = (const struct clk_hw*[]) { 2430 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, 2431 }, 2432 .num_parents = 1, 2433 .flags = CLK_SET_RATE_PARENT, 2434 .ops = &clk_branch2_ops, 2435 }, 2436 }, 2437 }; 2438 2439 static struct clk_branch gcc_qupv3_wrap2_s3_clk = { 2440 .halt_reg = 0x1e3c8, 2441 .halt_check = BRANCH_HALT_VOTED, 2442 .clkr = { 2443 .enable_reg = 0x52010, 2444 .enable_mask = BIT(7), 2445 .hw.init = &(const struct clk_init_data) { 2446 .name = "gcc_qupv3_wrap2_s3_clk", 2447 .parent_hws = (const struct clk_hw*[]) { 2448 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, 2449 }, 2450 .num_parents = 1, 2451 .flags = CLK_SET_RATE_PARENT, 2452 .ops = &clk_branch2_ops, 2453 }, 2454 }, 2455 }; 2456 2457 static struct clk_branch gcc_qupv3_wrap2_s4_clk = { 2458 .halt_reg = 0x1e504, 2459 .halt_check = BRANCH_HALT_VOTED, 2460 .clkr = { 2461 .enable_reg = 0x52010, 2462 .enable_mask = BIT(8), 2463 .hw.init = &(const struct clk_init_data) { 2464 .name = "gcc_qupv3_wrap2_s4_clk", 2465 .parent_hws = (const struct clk_hw*[]) { 2466 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, 2467 }, 2468 .num_parents = 1, 2469 .flags = CLK_SET_RATE_PARENT, 2470 .ops = &clk_branch2_ops, 2471 }, 2472 }, 2473 }; 2474 2475 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { 2476 .halt_reg = 0x2340c, 2477 .halt_check = BRANCH_HALT_VOTED, 2478 .clkr = { 2479 .enable_reg = 0x52018, 2480 .enable_mask = BIT(11), 2481 .hw.init = &(const struct clk_init_data) { 2482 .name = "gcc_qupv3_wrap3_core_2x_clk", 2483 .ops = &clk_branch2_ops, 2484 }, 2485 }, 2486 }; 2487 2488 static struct clk_branch gcc_qupv3_wrap3_core_clk = { 2489 .halt_reg = 0x233f8, 2490 .halt_check = BRANCH_HALT_VOTED, 2491 .clkr = { 2492 .enable_reg = 0x52018, 2493 .enable_mask = BIT(10), 2494 .hw.init = &(const struct clk_init_data) { 2495 .name = "gcc_qupv3_wrap3_core_clk", 2496 .ops = &clk_branch2_ops, 2497 }, 2498 }, 2499 }; 2500 2501 static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = { 2502 .halt_reg = 0xa8648, 2503 .halt_check = BRANCH_HALT_VOTED, 2504 .clkr = { 2505 .enable_reg = 0x52010, 2506 .enable_mask = BIT(25), 2507 .hw.init = &(const struct clk_init_data) { 2508 .name = "gcc_qupv3_wrap3_qspi_ref_clk", 2509 .parent_hws = (const struct clk_hw*[]) { 2510 &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, 2511 }, 2512 .num_parents = 1, 2513 .flags = CLK_SET_RATE_PARENT, 2514 .ops = &clk_branch2_ops, 2515 }, 2516 }, 2517 }; 2518 2519 static struct clk_branch gcc_qupv3_wrap3_s0_clk = { 2520 .halt_reg = 0xa8004, 2521 .halt_check = BRANCH_HALT_VOTED, 2522 .clkr = { 2523 .enable_reg = 0x52018, 2524 .enable_mask = BIT(12), 2525 .hw.init = &(const struct clk_init_data) { 2526 .name = "gcc_qupv3_wrap3_s0_clk", 2527 .parent_hws = (const struct clk_hw*[]) { 2528 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 2529 }, 2530 .num_parents = 1, 2531 .flags = CLK_SET_RATE_PARENT, 2532 .ops = &clk_branch2_ops, 2533 }, 2534 }, 2535 }; 2536 2537 static struct clk_branch gcc_qupv3_wrap3_s1_clk = { 2538 .halt_reg = 0xa8140, 2539 .halt_check = BRANCH_HALT_VOTED, 2540 .clkr = { 2541 .enable_reg = 0x52018, 2542 .enable_mask = BIT(13), 2543 .hw.init = &(const struct clk_init_data) { 2544 .name = "gcc_qupv3_wrap3_s1_clk", 2545 .parent_hws = (const struct clk_hw*[]) { 2546 &gcc_qupv3_wrap3_s1_clk_src.clkr.hw, 2547 }, 2548 .num_parents = 1, 2549 .flags = CLK_SET_RATE_PARENT, 2550 .ops = &clk_branch2_ops, 2551 }, 2552 }, 2553 }; 2554 2555 static struct clk_branch gcc_qupv3_wrap3_s2_clk = { 2556 .halt_reg = 0xa8158, 2557 .halt_check = BRANCH_HALT_VOTED, 2558 .clkr = { 2559 .enable_reg = 0x52018, 2560 .enable_mask = BIT(14), 2561 .hw.init = &(const struct clk_init_data) { 2562 .name = "gcc_qupv3_wrap3_s2_clk", 2563 .parent_hws = (const struct clk_hw*[]) { 2564 &gcc_qupv3_wrap3_s2_clk_src.clkr.hw, 2565 }, 2566 .num_parents = 1, 2567 .flags = CLK_SET_RATE_PARENT, 2568 .ops = &clk_branch2_ops, 2569 }, 2570 }, 2571 }; 2572 2573 static struct clk_branch gcc_qupv3_wrap3_s3_clk = { 2574 .halt_reg = 0xa8294, 2575 .halt_check = BRANCH_HALT_VOTED, 2576 .clkr = { 2577 .enable_reg = 0x52018, 2578 .enable_mask = BIT(15), 2579 .hw.init = &(const struct clk_init_data) { 2580 .name = "gcc_qupv3_wrap3_s3_clk", 2581 .parent_hws = (const struct clk_hw*[]) { 2582 &gcc_qupv3_wrap3_s3_clk_src.clkr.hw, 2583 }, 2584 .num_parents = 1, 2585 .flags = CLK_SET_RATE_PARENT, 2586 .ops = &clk_branch2_ops, 2587 }, 2588 }, 2589 }; 2590 2591 static struct clk_branch gcc_qupv3_wrap3_s4_clk = { 2592 .halt_reg = 0xa83d0, 2593 .halt_check = BRANCH_HALT_VOTED, 2594 .clkr = { 2595 .enable_reg = 0x52018, 2596 .enable_mask = BIT(16), 2597 .hw.init = &(const struct clk_init_data) { 2598 .name = "gcc_qupv3_wrap3_s4_clk", 2599 .parent_hws = (const struct clk_hw*[]) { 2600 &gcc_qupv3_wrap3_s4_clk_src.clkr.hw, 2601 }, 2602 .num_parents = 1, 2603 .flags = CLK_SET_RATE_PARENT, 2604 .ops = &clk_branch2_ops, 2605 }, 2606 }, 2607 }; 2608 2609 static struct clk_branch gcc_qupv3_wrap3_s5_clk = { 2610 .halt_reg = 0xa850c, 2611 .halt_check = BRANCH_HALT_VOTED, 2612 .clkr = { 2613 .enable_reg = 0x52018, 2614 .enable_mask = BIT(17), 2615 .hw.init = &(const struct clk_init_data) { 2616 .name = "gcc_qupv3_wrap3_s5_clk", 2617 .parent_hws = (const struct clk_hw*[]) { 2618 &gcc_qupv3_wrap3_s5_clk_src.clkr.hw, 2619 }, 2620 .num_parents = 1, 2621 .flags = CLK_SET_RATE_PARENT, 2622 .ops = &clk_branch2_ops, 2623 }, 2624 }, 2625 }; 2626 2627 static struct clk_branch gcc_qupv3_wrap4_core_2x_clk = { 2628 .halt_reg = 0x23564, 2629 .halt_check = BRANCH_HALT_VOTED, 2630 .clkr = { 2631 .enable_reg = 0x52018, 2632 .enable_mask = BIT(25), 2633 .hw.init = &(const struct clk_init_data) { 2634 .name = "gcc_qupv3_wrap4_core_2x_clk", 2635 .ops = &clk_branch2_ops, 2636 }, 2637 }, 2638 }; 2639 2640 static struct clk_branch gcc_qupv3_wrap4_core_clk = { 2641 .halt_reg = 0x23550, 2642 .halt_check = BRANCH_HALT_VOTED, 2643 .clkr = { 2644 .enable_reg = 0x52018, 2645 .enable_mask = BIT(24), 2646 .hw.init = &(const struct clk_init_data) { 2647 .name = "gcc_qupv3_wrap4_core_clk", 2648 .ops = &clk_branch2_ops, 2649 }, 2650 }, 2651 }; 2652 2653 static struct clk_branch gcc_qupv3_wrap4_s0_clk = { 2654 .halt_reg = 0xa9004, 2655 .halt_check = BRANCH_HALT_VOTED, 2656 .clkr = { 2657 .enable_reg = 0x52018, 2658 .enable_mask = BIT(26), 2659 .hw.init = &(const struct clk_init_data) { 2660 .name = "gcc_qupv3_wrap4_s0_clk", 2661 .parent_hws = (const struct clk_hw*[]) { 2662 &gcc_qupv3_wrap4_s0_clk_src.clkr.hw, 2663 }, 2664 .num_parents = 1, 2665 .flags = CLK_SET_RATE_PARENT, 2666 .ops = &clk_branch2_ops, 2667 }, 2668 }, 2669 }; 2670 2671 static struct clk_branch gcc_qupv3_wrap4_s1_clk = { 2672 .halt_reg = 0xa9140, 2673 .halt_check = BRANCH_HALT_VOTED, 2674 .clkr = { 2675 .enable_reg = 0x52018, 2676 .enable_mask = BIT(27), 2677 .hw.init = &(const struct clk_init_data) { 2678 .name = "gcc_qupv3_wrap4_s1_clk", 2679 .parent_hws = (const struct clk_hw*[]) { 2680 &gcc_qupv3_wrap4_s1_clk_src.clkr.hw, 2681 }, 2682 .num_parents = 1, 2683 .flags = CLK_SET_RATE_PARENT, 2684 .ops = &clk_branch2_ops, 2685 }, 2686 }, 2687 }; 2688 2689 static struct clk_branch gcc_qupv3_wrap4_s2_clk = { 2690 .halt_reg = 0xa927c, 2691 .halt_check = BRANCH_HALT_VOTED, 2692 .clkr = { 2693 .enable_reg = 0x52018, 2694 .enable_mask = BIT(28), 2695 .hw.init = &(const struct clk_init_data) { 2696 .name = "gcc_qupv3_wrap4_s2_clk", 2697 .parent_hws = (const struct clk_hw*[]) { 2698 &gcc_qupv3_wrap4_s2_clk_src.clkr.hw, 2699 }, 2700 .num_parents = 1, 2701 .flags = CLK_SET_RATE_PARENT, 2702 .ops = &clk_branch2_ops, 2703 }, 2704 }, 2705 }; 2706 2707 static struct clk_branch gcc_qupv3_wrap4_s3_clk = { 2708 .halt_reg = 0xa93b8, 2709 .halt_check = BRANCH_HALT_VOTED, 2710 .clkr = { 2711 .enable_reg = 0x52018, 2712 .enable_mask = BIT(29), 2713 .hw.init = &(const struct clk_init_data) { 2714 .name = "gcc_qupv3_wrap4_s3_clk", 2715 .parent_hws = (const struct clk_hw*[]) { 2716 &gcc_qupv3_wrap4_s3_clk_src.clkr.hw, 2717 }, 2718 .num_parents = 1, 2719 .flags = CLK_SET_RATE_PARENT, 2720 .ops = &clk_branch2_ops, 2721 }, 2722 }, 2723 }; 2724 2725 static struct clk_branch gcc_qupv3_wrap4_s4_clk = { 2726 .halt_reg = 0xa94f4, 2727 .halt_check = BRANCH_HALT_VOTED, 2728 .clkr = { 2729 .enable_reg = 0x52018, 2730 .enable_mask = BIT(30), 2731 .hw.init = &(const struct clk_init_data) { 2732 .name = "gcc_qupv3_wrap4_s4_clk", 2733 .parent_hws = (const struct clk_hw*[]) { 2734 &gcc_qupv3_wrap4_s4_clk_src.clkr.hw, 2735 }, 2736 .num_parents = 1, 2737 .flags = CLK_SET_RATE_PARENT, 2738 .ops = &clk_branch2_ops, 2739 }, 2740 }, 2741 }; 2742 2743 static struct clk_branch gcc_qupv3_wrap_1_m_axi_clk = { 2744 .halt_reg = 0x23140, 2745 .halt_check = BRANCH_HALT_VOTED, 2746 .hwcg_reg = 0x23140, 2747 .hwcg_bit = 1, 2748 .clkr = { 2749 .enable_reg = 0x52008, 2750 .enable_mask = BIT(20), 2751 .hw.init = &(const struct clk_init_data) { 2752 .name = "gcc_qupv3_wrap_1_m_axi_clk", 2753 .ops = &clk_branch2_ops, 2754 }, 2755 }, 2756 }; 2757 2758 static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { 2759 .halt_reg = 0x23144, 2760 .halt_check = BRANCH_HALT_VOTED, 2761 .hwcg_reg = 0x23144, 2762 .hwcg_bit = 1, 2763 .clkr = { 2764 .enable_reg = 0x52008, 2765 .enable_mask = BIT(21), 2766 .hw.init = &(const struct clk_init_data) { 2767 .name = "gcc_qupv3_wrap_1_s_ahb_clk", 2768 .ops = &clk_branch2_ops, 2769 }, 2770 }, 2771 }; 2772 2773 static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { 2774 .halt_reg = 0x23298, 2775 .halt_check = BRANCH_HALT_VOTED, 2776 .hwcg_reg = 0x23298, 2777 .hwcg_bit = 1, 2778 .clkr = { 2779 .enable_reg = 0x52010, 2780 .enable_mask = BIT(2), 2781 .hw.init = &(const struct clk_init_data) { 2782 .name = "gcc_qupv3_wrap_2_m_ahb_clk", 2783 .ops = &clk_branch2_ops, 2784 }, 2785 }, 2786 }; 2787 2788 static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { 2789 .halt_reg = 0x2329c, 2790 .halt_check = BRANCH_HALT_VOTED, 2791 .hwcg_reg = 0x2329c, 2792 .hwcg_bit = 1, 2793 .clkr = { 2794 .enable_reg = 0x52010, 2795 .enable_mask = BIT(1), 2796 .hw.init = &(const struct clk_init_data) { 2797 .name = "gcc_qupv3_wrap_2_s_ahb_clk", 2798 .ops = &clk_branch2_ops, 2799 }, 2800 }, 2801 }; 2802 2803 static struct clk_branch gcc_qupv3_wrap_3_m_ahb_clk = { 2804 .halt_reg = 0x233f0, 2805 .halt_check = BRANCH_HALT_VOTED, 2806 .hwcg_reg = 0x233f0, 2807 .hwcg_bit = 1, 2808 .clkr = { 2809 .enable_reg = 0x52018, 2810 .enable_mask = BIT(8), 2811 .hw.init = &(const struct clk_init_data) { 2812 .name = "gcc_qupv3_wrap_3_m_ahb_clk", 2813 .ops = &clk_branch2_ops, 2814 }, 2815 }, 2816 }; 2817 2818 static struct clk_branch gcc_qupv3_wrap_3_s_ahb_clk = { 2819 .halt_reg = 0x233f4, 2820 .halt_check = BRANCH_HALT_VOTED, 2821 .hwcg_reg = 0x233f4, 2822 .hwcg_bit = 1, 2823 .clkr = { 2824 .enable_reg = 0x52018, 2825 .enable_mask = BIT(9), 2826 .hw.init = &(const struct clk_init_data) { 2827 .name = "gcc_qupv3_wrap_3_s_ahb_clk", 2828 .ops = &clk_branch2_ops, 2829 }, 2830 }, 2831 }; 2832 2833 static struct clk_branch gcc_qupv3_wrap_4_m_ahb_clk = { 2834 .halt_reg = 0x23548, 2835 .halt_check = BRANCH_HALT_VOTED, 2836 .hwcg_reg = 0x23548, 2837 .hwcg_bit = 1, 2838 .clkr = { 2839 .enable_reg = 0x52018, 2840 .enable_mask = BIT(22), 2841 .hw.init = &(const struct clk_init_data) { 2842 .name = "gcc_qupv3_wrap_4_m_ahb_clk", 2843 .ops = &clk_branch2_ops, 2844 }, 2845 }, 2846 }; 2847 2848 static struct clk_branch gcc_qupv3_wrap_4_s_ahb_clk = { 2849 .halt_reg = 0x2354c, 2850 .halt_check = BRANCH_HALT_VOTED, 2851 .hwcg_reg = 0x2354c, 2852 .hwcg_bit = 1, 2853 .clkr = { 2854 .enable_reg = 0x52018, 2855 .enable_mask = BIT(23), 2856 .hw.init = &(const struct clk_init_data) { 2857 .name = "gcc_qupv3_wrap_4_s_ahb_clk", 2858 .ops = &clk_branch2_ops, 2859 }, 2860 }, 2861 }; 2862 2863 static struct clk_branch gcc_sdcc2_ahb_clk = { 2864 .halt_reg = 0x14014, 2865 .halt_check = BRANCH_HALT, 2866 .clkr = { 2867 .enable_reg = 0x14014, 2868 .enable_mask = BIT(0), 2869 .hw.init = &(const struct clk_init_data) { 2870 .name = "gcc_sdcc2_ahb_clk", 2871 .ops = &clk_branch2_ops, 2872 }, 2873 }, 2874 }; 2875 2876 static struct clk_branch gcc_sdcc2_apps_clk = { 2877 .halt_reg = 0x14004, 2878 .halt_check = BRANCH_HALT, 2879 .clkr = { 2880 .enable_reg = 0x14004, 2881 .enable_mask = BIT(0), 2882 .hw.init = &(const struct clk_init_data) { 2883 .name = "gcc_sdcc2_apps_clk", 2884 .parent_hws = (const struct clk_hw*[]) { 2885 &gcc_sdcc2_apps_clk_src.clkr.hw, 2886 }, 2887 .num_parents = 1, 2888 .flags = CLK_SET_RATE_PARENT, 2889 .ops = &clk_branch2_ops, 2890 }, 2891 }, 2892 }; 2893 2894 static struct clk_branch gcc_sdcc4_ahb_clk = { 2895 .halt_reg = 0x16014, 2896 .halt_check = BRANCH_HALT, 2897 .clkr = { 2898 .enable_reg = 0x16014, 2899 .enable_mask = BIT(0), 2900 .hw.init = &(const struct clk_init_data) { 2901 .name = "gcc_sdcc4_ahb_clk", 2902 .ops = &clk_branch2_ops, 2903 }, 2904 }, 2905 }; 2906 2907 static struct clk_branch gcc_sdcc4_apps_clk = { 2908 .halt_reg = 0x16004, 2909 .halt_check = BRANCH_HALT, 2910 .clkr = { 2911 .enable_reg = 0x16004, 2912 .enable_mask = BIT(0), 2913 .hw.init = &(const struct clk_init_data) { 2914 .name = "gcc_sdcc4_apps_clk", 2915 .parent_hws = (const struct clk_hw*[]) { 2916 &gcc_sdcc4_apps_clk_src.clkr.hw, 2917 }, 2918 .num_parents = 1, 2919 .flags = CLK_SET_RATE_PARENT, 2920 .ops = &clk_branch2_ops, 2921 }, 2922 }, 2923 }; 2924 2925 static struct clk_branch gcc_ufs_phy_ahb_clk = { 2926 .halt_reg = 0x77028, 2927 .halt_check = BRANCH_HALT_VOTED, 2928 .hwcg_reg = 0x77028, 2929 .hwcg_bit = 1, 2930 .clkr = { 2931 .enable_reg = 0x77028, 2932 .enable_mask = BIT(0), 2933 .hw.init = &(const struct clk_init_data) { 2934 .name = "gcc_ufs_phy_ahb_clk", 2935 .ops = &clk_branch2_ops, 2936 }, 2937 }, 2938 }; 2939 2940 static struct clk_branch gcc_ufs_phy_axi_clk = { 2941 .halt_reg = 0x77018, 2942 .halt_check = BRANCH_HALT_VOTED, 2943 .hwcg_reg = 0x77018, 2944 .hwcg_bit = 1, 2945 .clkr = { 2946 .enable_reg = 0x77018, 2947 .enable_mask = BIT(0), 2948 .hw.init = &(const struct clk_init_data) { 2949 .name = "gcc_ufs_phy_axi_clk", 2950 .parent_hws = (const struct clk_hw*[]) { 2951 &gcc_ufs_phy_axi_clk_src.clkr.hw, 2952 }, 2953 .num_parents = 1, 2954 .flags = CLK_SET_RATE_PARENT, 2955 .ops = &clk_branch2_ops, 2956 }, 2957 }, 2958 }; 2959 2960 static struct clk_branch gcc_ufs_phy_ice_core_clk = { 2961 .halt_reg = 0x7707c, 2962 .halt_check = BRANCH_HALT_VOTED, 2963 .hwcg_reg = 0x7707c, 2964 .hwcg_bit = 1, 2965 .clkr = { 2966 .enable_reg = 0x7707c, 2967 .enable_mask = BIT(0), 2968 .hw.init = &(const struct clk_init_data) { 2969 .name = "gcc_ufs_phy_ice_core_clk", 2970 .parent_hws = (const struct clk_hw*[]) { 2971 &gcc_ufs_phy_ice_core_clk_src.clkr.hw, 2972 }, 2973 .num_parents = 1, 2974 .flags = CLK_SET_RATE_PARENT, 2975 .ops = &clk_branch2_ops, 2976 }, 2977 }, 2978 }; 2979 2980 static struct clk_branch gcc_ufs_phy_phy_aux_clk = { 2981 .halt_reg = 0x770bc, 2982 .halt_check = BRANCH_HALT_VOTED, 2983 .hwcg_reg = 0x770bc, 2984 .hwcg_bit = 1, 2985 .clkr = { 2986 .enable_reg = 0x770bc, 2987 .enable_mask = BIT(0), 2988 .hw.init = &(const struct clk_init_data) { 2989 .name = "gcc_ufs_phy_phy_aux_clk", 2990 .parent_hws = (const struct clk_hw*[]) { 2991 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, 2992 }, 2993 .num_parents = 1, 2994 .flags = CLK_SET_RATE_PARENT, 2995 .ops = &clk_branch2_ops, 2996 }, 2997 }, 2998 }; 2999 3000 static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 3001 .halt_reg = 0x77030, 3002 .halt_check = BRANCH_HALT_DELAY, 3003 .clkr = { 3004 .enable_reg = 0x77030, 3005 .enable_mask = BIT(0), 3006 .hw.init = &(const struct clk_init_data) { 3007 .name = "gcc_ufs_phy_rx_symbol_0_clk", 3008 .parent_hws = (const struct clk_hw*[]) { 3009 &gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw, 3010 }, 3011 .num_parents = 1, 3012 .flags = CLK_SET_RATE_PARENT, 3013 .ops = &clk_branch2_ops, 3014 }, 3015 }, 3016 }; 3017 3018 static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { 3019 .halt_reg = 0x770d8, 3020 .halt_check = BRANCH_HALT_DELAY, 3021 .clkr = { 3022 .enable_reg = 0x770d8, 3023 .enable_mask = BIT(0), 3024 .hw.init = &(const struct clk_init_data) { 3025 .name = "gcc_ufs_phy_rx_symbol_1_clk", 3026 .parent_hws = (const struct clk_hw*[]) { 3027 &gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw, 3028 }, 3029 .num_parents = 1, 3030 .flags = CLK_SET_RATE_PARENT, 3031 .ops = &clk_branch2_ops, 3032 }, 3033 }, 3034 }; 3035 3036 static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { 3037 .halt_reg = 0x7702c, 3038 .halt_check = BRANCH_HALT_DELAY, 3039 .clkr = { 3040 .enable_reg = 0x7702c, 3041 .enable_mask = BIT(0), 3042 .hw.init = &(const struct clk_init_data) { 3043 .name = "gcc_ufs_phy_tx_symbol_0_clk", 3044 .parent_hws = (const struct clk_hw*[]) { 3045 &gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw, 3046 }, 3047 .num_parents = 1, 3048 .flags = CLK_SET_RATE_PARENT, 3049 .ops = &clk_branch2_ops, 3050 }, 3051 }, 3052 }; 3053 3054 static struct clk_branch gcc_ufs_phy_unipro_5_core_clk = { 3055 .halt_reg = 0x7706c, 3056 .halt_check = BRANCH_HALT_VOTED, 3057 .hwcg_reg = 0x7706c, 3058 .hwcg_bit = 1, 3059 .clkr = { 3060 .enable_reg = 0x7706c, 3061 .enable_mask = BIT(0), 3062 .hw.init = &(const struct clk_init_data) { 3063 .name = "gcc_ufs_phy_unipro_5_core_clk", 3064 .parent_hws = (const struct clk_hw*[]) { 3065 &gcc_ufs_phy_unipro_5_core_clk_src.clkr.hw, 3066 }, 3067 .num_parents = 1, 3068 .flags = CLK_SET_RATE_PARENT, 3069 .ops = &clk_branch2_ops, 3070 }, 3071 }, 3072 }; 3073 3074 static struct clk_branch gcc_usb30_prim_master_clk = { 3075 .halt_reg = 0x39018, 3076 .halt_check = BRANCH_HALT, 3077 .clkr = { 3078 .enable_reg = 0x39018, 3079 .enable_mask = BIT(0), 3080 .hw.init = &(const struct clk_init_data) { 3081 .name = "gcc_usb30_prim_master_clk", 3082 .parent_hws = (const struct clk_hw*[]) { 3083 &gcc_usb30_prim_master_clk_src.clkr.hw, 3084 }, 3085 .num_parents = 1, 3086 .flags = CLK_SET_RATE_PARENT, 3087 .ops = &clk_branch2_ops, 3088 }, 3089 }, 3090 }; 3091 3092 static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { 3093 .halt_reg = 0x3902c, 3094 .halt_check = BRANCH_HALT, 3095 .clkr = { 3096 .enable_reg = 0x3902c, 3097 .enable_mask = BIT(0), 3098 .hw.init = &(const struct clk_init_data) { 3099 .name = "gcc_usb30_prim_mock_utmi_clk", 3100 .parent_hws = (const struct clk_hw*[]) { 3101 &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, 3102 }, 3103 .num_parents = 1, 3104 .flags = CLK_SET_RATE_PARENT, 3105 .ops = &clk_branch2_ops, 3106 }, 3107 }, 3108 }; 3109 3110 static struct clk_branch gcc_usb30_prim_sleep_clk = { 3111 .halt_reg = 0x39028, 3112 .halt_check = BRANCH_HALT, 3113 .clkr = { 3114 .enable_reg = 0x39028, 3115 .enable_mask = BIT(0), 3116 .hw.init = &(const struct clk_init_data) { 3117 .name = "gcc_usb30_prim_sleep_clk", 3118 .ops = &clk_branch2_ops, 3119 }, 3120 }, 3121 }; 3122 3123 static struct clk_branch gcc_usb3_prim_phy_aux_clk = { 3124 .halt_reg = 0x39068, 3125 .halt_check = BRANCH_HALT, 3126 .clkr = { 3127 .enable_reg = 0x39068, 3128 .enable_mask = BIT(0), 3129 .hw.init = &(const struct clk_init_data) { 3130 .name = "gcc_usb3_prim_phy_aux_clk", 3131 .parent_hws = (const struct clk_hw*[]) { 3132 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3133 }, 3134 .num_parents = 1, 3135 .flags = CLK_SET_RATE_PARENT, 3136 .ops = &clk_branch2_ops, 3137 }, 3138 }, 3139 }; 3140 3141 static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { 3142 .halt_reg = 0x3906c, 3143 .halt_check = BRANCH_HALT, 3144 .clkr = { 3145 .enable_reg = 0x3906c, 3146 .enable_mask = BIT(0), 3147 .hw.init = &(const struct clk_init_data) { 3148 .name = "gcc_usb3_prim_phy_com_aux_clk", 3149 .parent_hws = (const struct clk_hw*[]) { 3150 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, 3151 }, 3152 .num_parents = 1, 3153 .flags = CLK_SET_RATE_PARENT, 3154 .ops = &clk_branch2_ops, 3155 }, 3156 }, 3157 }; 3158 3159 static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { 3160 .halt_reg = 0x39070, 3161 .halt_check = BRANCH_HALT_DELAY, 3162 .hwcg_reg = 0x39070, 3163 .hwcg_bit = 1, 3164 .clkr = { 3165 .enable_reg = 0x39070, 3166 .enable_mask = BIT(0), 3167 .hw.init = &(const struct clk_init_data) { 3168 .name = "gcc_usb3_prim_phy_pipe_clk", 3169 .parent_hws = (const struct clk_hw*[]) { 3170 &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw, 3171 }, 3172 .num_parents = 1, 3173 .flags = CLK_SET_RATE_PARENT, 3174 .ops = &clk_branch2_ops, 3175 }, 3176 }, 3177 }; 3178 3179 static struct clk_branch gcc_video_axi0_clk = { 3180 .halt_reg = 0x32018, 3181 .halt_check = BRANCH_HALT_SKIP, 3182 .hwcg_reg = 0x32018, 3183 .hwcg_bit = 1, 3184 .clkr = { 3185 .enable_reg = 0x32018, 3186 .enable_mask = BIT(0), 3187 .hw.init = &(const struct clk_init_data) { 3188 .name = "gcc_video_axi0_clk", 3189 .ops = &clk_branch2_ops, 3190 }, 3191 }, 3192 }; 3193 3194 static struct clk_branch gcc_video_axi0c_clk = { 3195 .halt_reg = 0x32020, 3196 .halt_check = BRANCH_HALT_SKIP, 3197 .hwcg_reg = 0x32020, 3198 .hwcg_bit = 1, 3199 .clkr = { 3200 .enable_reg = 0x32020, 3201 .enable_mask = BIT(0), 3202 .hw.init = &(const struct clk_init_data) { 3203 .name = "gcc_video_axi0c_clk", 3204 .ops = &clk_branch2_ops, 3205 }, 3206 }, 3207 }; 3208 3209 static struct gdsc gcc_pcie_0_gdsc = { 3210 .gdscr = 0x6b004, 3211 .en_rest_wait_val = 0x2, 3212 .en_few_wait_val = 0x2, 3213 .clk_dis_wait_val = 0xf, 3214 .collapse_ctrl = 0x52154, 3215 .collapse_mask = BIT(0), 3216 .pd = { 3217 .name = "gcc_pcie_0_gdsc", 3218 }, 3219 .pwrsts = PWRSTS_OFF_ON, 3220 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3221 }; 3222 3223 static struct gdsc gcc_pcie_0_phy_gdsc = { 3224 .gdscr = 0x6c000, 3225 .en_rest_wait_val = 0x2, 3226 .en_few_wait_val = 0x2, 3227 .clk_dis_wait_val = 0x2, 3228 .collapse_ctrl = 0x52154, 3229 .collapse_mask = BIT(1), 3230 .pd = { 3231 .name = "gcc_pcie_0_phy_gdsc", 3232 }, 3233 .pwrsts = PWRSTS_OFF_ON, 3234 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3235 }; 3236 3237 static struct gdsc gcc_pcie_1_gdsc = { 3238 .gdscr = 0x67004, 3239 .en_rest_wait_val = 0x2, 3240 .en_few_wait_val = 0x2, 3241 .clk_dis_wait_val = 0xf, 3242 .collapse_ctrl = 0x5214c, 3243 .collapse_mask = BIT(2), 3244 .pd = { 3245 .name = "gcc_pcie_1_gdsc", 3246 }, 3247 .pwrsts = PWRSTS_OFF_ON, 3248 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3249 }; 3250 3251 static struct gdsc gcc_pcie_1_phy_gdsc = { 3252 .gdscr = 0x68000, 3253 .en_rest_wait_val = 0x2, 3254 .en_few_wait_val = 0x2, 3255 .clk_dis_wait_val = 0x2, 3256 .collapse_ctrl = 0x5214c, 3257 .collapse_mask = BIT(3), 3258 .pd = { 3259 .name = "gcc_pcie_1_phy_gdsc", 3260 }, 3261 .pwrsts = PWRSTS_OFF_ON, 3262 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 3263 }; 3264 3265 static struct gdsc gcc_ufs_mem_phy_gdsc = { 3266 .gdscr = 0x9e000, 3267 .en_rest_wait_val = 0x2, 3268 .en_few_wait_val = 0x2, 3269 .clk_dis_wait_val = 0x2, 3270 .pd = { 3271 .name = "gcc_ufs_mem_phy_gdsc", 3272 }, 3273 .pwrsts = PWRSTS_OFF_ON, 3274 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3275 }; 3276 3277 static struct gdsc gcc_ufs_phy_gdsc = { 3278 .gdscr = 0x77004, 3279 .en_rest_wait_val = 0x2, 3280 .en_few_wait_val = 0x2, 3281 .clk_dis_wait_val = 0xf, 3282 .pd = { 3283 .name = "gcc_ufs_phy_gdsc", 3284 }, 3285 .pwrsts = PWRSTS_OFF_ON, 3286 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3287 }; 3288 3289 static struct gdsc gcc_usb30_prim_gdsc = { 3290 .gdscr = 0x39004, 3291 .en_rest_wait_val = 0x2, 3292 .en_few_wait_val = 0x2, 3293 .clk_dis_wait_val = 0xf, 3294 .pd = { 3295 .name = "gcc_usb30_prim_gdsc", 3296 }, 3297 .pwrsts = PWRSTS_OFF_ON, 3298 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3299 }; 3300 3301 static struct gdsc gcc_usb3_phy_gdsc = { 3302 .gdscr = 0x50018, 3303 .en_rest_wait_val = 0x2, 3304 .en_few_wait_val = 0x2, 3305 .clk_dis_wait_val = 0x2, 3306 .pd = { 3307 .name = "gcc_usb3_phy_gdsc", 3308 }, 3309 .pwrsts = PWRSTS_OFF_ON, 3310 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, 3311 }; 3312 3313 static struct clk_regmap *gcc_hawi_clocks[] = { 3314 [GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr, 3315 [GCC_AGGRE_STARDUSTNOC_USB3_PRIM_AXI_CLK] = &gcc_aggre_stardustnoc_usb3_prim_axi_clk.clkr, 3316 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr, 3317 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 3318 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr, 3319 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr, 3320 [GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr, 3321 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, 3322 [GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr, 3323 [GCC_EVA_AXI0_CLK] = &gcc_eva_axi0_clk.clkr, 3324 [GCC_EVA_AXI0C_CLK] = &gcc_eva_axi0c_clk.clkr, 3325 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 3326 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 3327 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 3328 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 3329 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 3330 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, 3331 [GCC_GPLL0] = &gcc_gpll0.clkr, 3332 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 3333 [GCC_GPLL4] = &gcc_gpll4.clkr, 3334 [GCC_GPLL5] = &gcc_gpll5.clkr, 3335 [GCC_GPLL7] = &gcc_gpll7.clkr, 3336 [GCC_GPLL9] = &gcc_gpll9.clkr, 3337 [GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr, 3338 [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, 3339 [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, 3340 [GCC_GPU_SMMU_VOTE_CLK] = &gcc_gpu_smmu_vote_clk.clkr, 3341 [GCC_MMU_TCU_VOTE_CLK] = &gcc_mmu_tcu_vote_clk.clkr, 3342 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr, 3343 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr, 3344 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr, 3345 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr, 3346 [GCC_PCIE_0_PHY_AUX_CLK] = &gcc_pcie_0_phy_aux_clk.clkr, 3347 [GCC_PCIE_0_PHY_AUX_CLK_SRC] = &gcc_pcie_0_phy_aux_clk_src.clkr, 3348 [GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr, 3349 [GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr, 3350 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr, 3351 [GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr, 3352 [GCC_PCIE_0_PIPE_DIV2_CLK] = &gcc_pcie_0_pipe_div2_clk.clkr, 3353 [GCC_PCIE_0_PIPE_DIV_CLK_SRC] = &gcc_pcie_0_pipe_div_clk_src.clkr, 3354 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr, 3355 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, 3356 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr, 3357 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr, 3358 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr, 3359 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr, 3360 [GCC_PCIE_1_PHY_AUX_CLK] = &gcc_pcie_1_phy_aux_clk.clkr, 3361 [GCC_PCIE_1_PHY_AUX_CLK_SRC] = &gcc_pcie_1_phy_aux_clk_src.clkr, 3362 [GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr, 3363 [GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr, 3364 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr, 3365 [GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr, 3366 [GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr, 3367 [GCC_PCIE_1_PIPE_DIV_CLK_SRC] = &gcc_pcie_1_pipe_div_clk_src.clkr, 3368 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr, 3369 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, 3370 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 3371 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 3372 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 3373 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 3374 [GCC_QUPV3_I2C_CORE_CLK] = &gcc_qupv3_i2c_core_clk.clkr, 3375 [GCC_QUPV3_I2C_S0_CLK] = &gcc_qupv3_i2c_s0_clk.clkr, 3376 [GCC_QUPV3_I2C_S0_CLK_SRC] = &gcc_qupv3_i2c_s0_clk_src.clkr, 3377 [GCC_QUPV3_I2C_S1_CLK] = &gcc_qupv3_i2c_s1_clk.clkr, 3378 [GCC_QUPV3_I2C_S1_CLK_SRC] = &gcc_qupv3_i2c_s1_clk_src.clkr, 3379 [GCC_QUPV3_I2C_S2_CLK] = &gcc_qupv3_i2c_s2_clk.clkr, 3380 [GCC_QUPV3_I2C_S2_CLK_SRC] = &gcc_qupv3_i2c_s2_clk_src.clkr, 3381 [GCC_QUPV3_I2C_S3_CLK] = &gcc_qupv3_i2c_s3_clk.clkr, 3382 [GCC_QUPV3_I2C_S3_CLK_SRC] = &gcc_qupv3_i2c_s3_clk_src.clkr, 3383 [GCC_QUPV3_I2C_S4_CLK] = &gcc_qupv3_i2c_s4_clk.clkr, 3384 [GCC_QUPV3_I2C_S4_CLK_SRC] = &gcc_qupv3_i2c_s4_clk_src.clkr, 3385 [GCC_QUPV3_I2C_S_AHB_CLK] = &gcc_qupv3_i2c_s_ahb_clk.clkr, 3386 [GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr, 3387 [GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr, 3388 [GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr, 3389 [GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr, 3390 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr, 3391 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr, 3392 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr, 3393 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr, 3394 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr, 3395 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr, 3396 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr, 3397 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr, 3398 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr, 3399 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr, 3400 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr, 3401 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr, 3402 [GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr, 3403 [GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr, 3404 [GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr, 3405 [GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr, 3406 [GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr, 3407 [GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr, 3408 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr, 3409 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr, 3410 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr, 3411 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr, 3412 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr, 3413 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr, 3414 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr, 3415 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr, 3416 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr, 3417 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr, 3418 [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, 3419 [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, 3420 [GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &gcc_qupv3_wrap3_qspi_ref_clk.clkr, 3421 [GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr, 3422 [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, 3423 [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, 3424 [GCC_QUPV3_WRAP3_S1_CLK] = &gcc_qupv3_wrap3_s1_clk.clkr, 3425 [GCC_QUPV3_WRAP3_S1_CLK_SRC] = &gcc_qupv3_wrap3_s1_clk_src.clkr, 3426 [GCC_QUPV3_WRAP3_S2_CLK] = &gcc_qupv3_wrap3_s2_clk.clkr, 3427 [GCC_QUPV3_WRAP3_S2_CLK_SRC] = &gcc_qupv3_wrap3_s2_clk_src.clkr, 3428 [GCC_QUPV3_WRAP3_S3_CLK] = &gcc_qupv3_wrap3_s3_clk.clkr, 3429 [GCC_QUPV3_WRAP3_S3_CLK_SRC] = &gcc_qupv3_wrap3_s3_clk_src.clkr, 3430 [GCC_QUPV3_WRAP3_S4_CLK] = &gcc_qupv3_wrap3_s4_clk.clkr, 3431 [GCC_QUPV3_WRAP3_S4_CLK_SRC] = &gcc_qupv3_wrap3_s4_clk_src.clkr, 3432 [GCC_QUPV3_WRAP3_S5_CLK] = &gcc_qupv3_wrap3_s5_clk.clkr, 3433 [GCC_QUPV3_WRAP3_S5_CLK_SRC] = &gcc_qupv3_wrap3_s5_clk_src.clkr, 3434 [GCC_QUPV3_WRAP4_CORE_2X_CLK] = &gcc_qupv3_wrap4_core_2x_clk.clkr, 3435 [GCC_QUPV3_WRAP4_CORE_CLK] = &gcc_qupv3_wrap4_core_clk.clkr, 3436 [GCC_QUPV3_WRAP4_S0_CLK] = &gcc_qupv3_wrap4_s0_clk.clkr, 3437 [GCC_QUPV3_WRAP4_S0_CLK_SRC] = &gcc_qupv3_wrap4_s0_clk_src.clkr, 3438 [GCC_QUPV3_WRAP4_S1_CLK] = &gcc_qupv3_wrap4_s1_clk.clkr, 3439 [GCC_QUPV3_WRAP4_S1_CLK_SRC] = &gcc_qupv3_wrap4_s1_clk_src.clkr, 3440 [GCC_QUPV3_WRAP4_S2_CLK] = &gcc_qupv3_wrap4_s2_clk.clkr, 3441 [GCC_QUPV3_WRAP4_S2_CLK_SRC] = &gcc_qupv3_wrap4_s2_clk_src.clkr, 3442 [GCC_QUPV3_WRAP4_S3_CLK] = &gcc_qupv3_wrap4_s3_clk.clkr, 3443 [GCC_QUPV3_WRAP4_S3_CLK_SRC] = &gcc_qupv3_wrap4_s3_clk_src.clkr, 3444 [GCC_QUPV3_WRAP4_S4_CLK] = &gcc_qupv3_wrap4_s4_clk.clkr, 3445 [GCC_QUPV3_WRAP4_S4_CLK_SRC] = &gcc_qupv3_wrap4_s4_clk_src.clkr, 3446 [GCC_QUPV3_WRAP_1_M_AXI_CLK] = &gcc_qupv3_wrap_1_m_axi_clk.clkr, 3447 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, 3448 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, 3449 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, 3450 [GCC_QUPV3_WRAP_3_M_AHB_CLK] = &gcc_qupv3_wrap_3_m_ahb_clk.clkr, 3451 [GCC_QUPV3_WRAP_3_S_AHB_CLK] = &gcc_qupv3_wrap_3_s_ahb_clk.clkr, 3452 [GCC_QUPV3_WRAP_4_M_AHB_CLK] = &gcc_qupv3_wrap_4_m_ahb_clk.clkr, 3453 [GCC_QUPV3_WRAP_4_S_AHB_CLK] = &gcc_qupv3_wrap_4_s_ahb_clk.clkr, 3454 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 3455 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 3456 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr, 3457 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr, 3458 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr, 3459 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr, 3460 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr, 3461 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr, 3462 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr, 3463 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr, 3464 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr, 3465 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, 3466 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, 3467 [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, 3468 [GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr, 3469 [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, 3470 [GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr, 3471 [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, 3472 [GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr, 3473 [GCC_UFS_PHY_UNIPRO_5_CORE_CLK] = &gcc_ufs_phy_unipro_5_core_clk.clkr, 3474 [GCC_UFS_PHY_UNIPRO_5_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_5_core_clk_src.clkr, 3475 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr, 3476 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr, 3477 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr, 3478 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr, 3479 [GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, 3480 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr, 3481 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, 3482 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, 3483 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, 3484 [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, 3485 [GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr, 3486 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, 3487 [GCC_VIDEO_AXI0C_CLK] = &gcc_video_axi0c_clk.clkr, 3488 }; 3489 3490 static struct gdsc *gcc_hawi_gdscs[] = { 3491 [GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc, 3492 [GCC_PCIE_0_PHY_GDSC] = &gcc_pcie_0_phy_gdsc, 3493 [GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc, 3494 [GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc, 3495 [GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc, 3496 [GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc, 3497 [GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc, 3498 [GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc, 3499 }; 3500 3501 static const struct qcom_reset_map gcc_hawi_resets[] = { 3502 [GCC_CAMERA_BCR] = { 0x26000 }, 3503 [GCC_EVA_AXI0_CLK_ARES] = { 0x9f008, 2 }, 3504 [GCC_EVA_AXI0C_CLK_ARES] = { 0x9f010, 2 }, 3505 [GCC_EVA_BCR] = { 0x9f000 }, 3506 [GCC_GPU_BCR] = { 0x71000 }, 3507 [GCC_PCIE_0_BCR] = { 0x6b000 }, 3508 [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 }, 3509 [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 }, 3510 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c }, 3511 [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 }, 3512 [GCC_PCIE_1_BCR] = { 0x67000 }, 3513 [GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 }, 3514 [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 }, 3515 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c }, 3516 [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 }, 3517 [GCC_PCIE_PHY_BCR] = { 0x6f000 }, 3518 [GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c }, 3519 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 }, 3520 [GCC_PCIE_RSCC_BCR] = { 0x11000 }, 3521 [GCC_PDM_BCR] = { 0x33000 }, 3522 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 }, 3523 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 }, 3524 [GCC_QUPV3_WRAPPER_3_BCR] = { 0xa8000 }, 3525 [GCC_QUPV3_WRAPPER_4_BCR] = { 0xa9000 }, 3526 [GCC_QUPV3_WRAPPER_I2C_BCR] = { 0x17000 }, 3527 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 }, 3528 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 }, 3529 [GCC_SDCC2_BCR] = { 0x14000 }, 3530 [GCC_SDCC4_BCR] = { 0x16000 }, 3531 [GCC_TCSR_PCIE_BCR] = { 0x6f018 }, 3532 [GCC_UFS_PHY_BCR] = { 0x77000 }, 3533 [GCC_USB30_PRIM_BCR] = { 0x39000 }, 3534 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 }, 3535 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 }, 3536 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 }, 3537 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c }, 3538 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 }, 3539 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 }, 3540 [GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 }, 3541 [GCC_VIDEO_AXI0C_CLK_ARES] = { 0x32020, 2 }, 3542 [GCC_VIDEO_BCR] = { 0x32000 }, 3543 [GCC_VIDEO_XO_CLK_ARES] = { 0x32028, 2 }, 3544 }; 3545 3546 static const u32 gcc_hawi_critical_cbcrs[] = { 3547 0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */ 3548 0x26004, /* GCC_CAMERA_AHB_CLK */ 3549 0x26028, /* GCC_CAMERA_RSC_CORE_CLK */ 3550 0x26024, /* GCC_CAMERA_XO_CLK */ 3551 0x9f004, /* GCC_EVA_AHB_CLK */ 3552 0x9f018, /* GCC_EVA_XO_CLK */ 3553 0x71004, /* GCC_GPU_CFG_AHB_CLK */ 3554 0x7101c, /* GCC_GPU_RSC_CORE_CLK */ 3555 0x67084, /* GCC_PCIE_1_RSC_CORE_CLK */ 3556 0x43014, /* GCC_PCIE_LINK_XO_CLK */ 3557 0x6b088, /* GCC_PCIE_RSC_CORE_CLK */ 3558 0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */ 3559 0x52010, /* GCC_PCIE_RSCC_XO_CLK */ 3560 0x32004, /* GCC_VIDEO_AHB_CLK */ 3561 0x32028, /* GCC_VIDEO_XO_CLK */ 3562 }; 3563 3564 static const struct clk_rcg_dfs_data gcc_hawi_dfs_clocks[] = { 3565 DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src), 3566 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src), 3567 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src), 3568 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src), 3569 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src), 3570 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src), 3571 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src), 3572 DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src), 3573 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src), 3574 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src), 3575 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src), 3576 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src), 3577 DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src), 3578 DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src), 3579 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s0_clk_src), 3580 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s2_clk_src), 3581 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s3_clk_src), 3582 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s4_clk_src), 3583 DEFINE_RCG_DFS(gcc_qupv3_wrap3_s5_clk_src), 3584 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s0_clk_src), 3585 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s1_clk_src), 3586 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s2_clk_src), 3587 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s3_clk_src), 3588 DEFINE_RCG_DFS(gcc_qupv3_wrap4_s4_clk_src), 3589 }; 3590 3591 static const struct regmap_config gcc_hawi_regmap_config = { 3592 .reg_bits = 32, 3593 .reg_stride = 4, 3594 .val_bits = 32, 3595 .max_register = 0x1f41f4, 3596 .fast_io = true, 3597 }; 3598 3599 static void clk_hawi_regs_configure(struct device *dev, struct regmap *regmap) 3600 { 3601 /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ 3602 qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); 3603 } 3604 3605 static const struct qcom_cc_driver_data gcc_hawi_driver_data = { 3606 .clk_cbcrs = gcc_hawi_critical_cbcrs, 3607 .num_clk_cbcrs = ARRAY_SIZE(gcc_hawi_critical_cbcrs), 3608 .dfs_rcgs = gcc_hawi_dfs_clocks, 3609 .num_dfs_rcgs = ARRAY_SIZE(gcc_hawi_dfs_clocks), 3610 .clk_regs_configure = clk_hawi_regs_configure, 3611 }; 3612 3613 static const struct qcom_cc_desc gcc_hawi_desc = { 3614 .config = &gcc_hawi_regmap_config, 3615 .clks = gcc_hawi_clocks, 3616 .num_clks = ARRAY_SIZE(gcc_hawi_clocks), 3617 .resets = gcc_hawi_resets, 3618 .num_resets = ARRAY_SIZE(gcc_hawi_resets), 3619 .gdscs = gcc_hawi_gdscs, 3620 .num_gdscs = ARRAY_SIZE(gcc_hawi_gdscs), 3621 .use_rpm = true, 3622 .driver_data = &gcc_hawi_driver_data, 3623 }; 3624 3625 static const struct of_device_id gcc_hawi_match_table[] = { 3626 { .compatible = "qcom,hawi-gcc" }, 3627 { } 3628 }; 3629 MODULE_DEVICE_TABLE(of, gcc_hawi_match_table); 3630 3631 static int gcc_hawi_probe(struct platform_device *pdev) 3632 { 3633 return qcom_cc_probe(pdev, &gcc_hawi_desc); 3634 } 3635 3636 static struct platform_driver gcc_hawi_driver = { 3637 .probe = gcc_hawi_probe, 3638 .driver = { 3639 .name = "gcc-hawi", 3640 .of_match_table = gcc_hawi_match_table, 3641 }, 3642 }; 3643 3644 static int __init gcc_hawi_init(void) 3645 { 3646 return platform_driver_register(&gcc_hawi_driver); 3647 } 3648 subsys_initcall(gcc_hawi_init); 3649 3650 static void __exit gcc_hawi_exit(void) 3651 { 3652 platform_driver_unregister(&gcc_hawi_driver); 3653 } 3654 module_exit(gcc_hawi_exit); 3655 3656 MODULE_DESCRIPTION("QTI GCC HAWI Driver"); 3657 MODULE_LICENSE("GPL"); 3658