Lines Matching +full:0 +full:x23000
30 { 249600000, 2000000000, 0 },
34 .l = 0x20,
35 .alpha = 0x0,
36 .config_ctl_val = 0x20485699,
37 .config_ctl_hi_val = 0x00002067,
38 .test_ctl_val = 0x40000000,
39 .test_ctl_hi_val = 0x00000000,
40 .user_ctl_val = 0x00005105,
41 .user_ctl_hi_val = 0x00004805,
46 [PLL_OFF_L_VAL] = 0x04,
47 [PLL_OFF_CAL_L_VAL] = 0x8,
48 [PLL_OFF_USER_CTL] = 0x0c,
49 [PLL_OFF_USER_CTL_U] = 0x10,
50 [PLL_OFF_USER_CTL_U1] = 0x14,
51 [PLL_OFF_CONFIG_CTL] = 0x18,
52 [PLL_OFF_CONFIG_CTL_U] = 0x1C,
53 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
54 [PLL_OFF_TEST_CTL] = 0x24,
55 [PLL_OFF_TEST_CTL_U] = 0x28,
56 [PLL_OFF_STATUS] = 0x30,
57 [PLL_OFF_OPMODE] = 0x38,
58 [PLL_OFF_FRAC] = 0x40,
63 .offset = 0x1000,
81 { 0x5, 5 },
86 .offset = 0x1000,
105 { P_BI_TCXO, 0 },
115 { P_BI_TCXO, 0 },
119 .cmd_rcgr = 0x1d000,
134 F(9600000, P_BI_TCXO, 2, 0, 0),
135 F(19200000, P_BI_TCXO, 1, 0, 0),
149 F(8192000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 15, 0, 0),
150 F(9600000, P_BI_TCXO, 2, 0, 0),
151 F(12288000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 10, 0, 0),
152 F(19200000, P_BI_TCXO, 1, 0, 0),
153 F(24576000, P_LPASS_LPAAUDIO_DIG_PLL_OUT_ODD, 5, 0, 0),
158 .cmd_rcgr = 0x20000,
173 .cmd_rcgr = 0x10000,
188 .cmd_rcgr = 0x11000,
203 .halt_reg = 0x20014,
205 .hwcg_reg = 0x20014,
208 .enable_reg = 0x20014,
209 .enable_mask = BIT(0),
223 .halt_reg = 0x10018,
225 .hwcg_reg = 0x10018,
228 .enable_reg = 0x10018,
229 .enable_mask = BIT(0),
243 .halt_reg = 0x11018,
245 .hwcg_reg = 0x11018,
248 .enable_reg = 0x11018,
249 .enable_mask = BIT(0),
263 .halt_reg = 0x23000,
265 .hwcg_reg = 0x23000,
268 .enable_reg = 0x23000,
269 .enable_mask = BIT(0),
299 .gdscr = 0x3090,
308 .gdscr = 0x9090,
316 .gdscr = 0x0,
374 if (ret < 0)
404 qcom_branch_set_clk_en(regmap, 0x24000); /* LPASS_AUDIO_CORE_SYSNOC_SWAY_CORE_CLK */
407 regmap_write(regmap, 0x1008, 0x20);
408 regmap_update_bits(regmap, 0x1014, BIT(0), BIT(0));
433 ret = qcom_cc_probe_by_index(pdev, 0, desc);
492 return 0;