1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/module.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 12 #include <dt-bindings/clock/qcom,nord-gcc.h> 13 14 #include "clk-alpha-pll.h" 15 #include "clk-branch.h" 16 #include "clk-pll.h" 17 #include "clk-rcg.h" 18 #include "clk-regmap.h" 19 #include "clk-regmap-divider.h" 20 #include "clk-regmap-mux.h" 21 #include "clk-regmap-phy-mux.h" 22 #include "common.h" 23 #include "gdsc.h" 24 #include "reset.h" 25 26 enum { 27 DT_BI_TCXO, 28 DT_SLEEP_CLK, 29 DT_PCIE_A_PIPE_CLK, 30 DT_PCIE_B_PIPE_CLK, 31 DT_PCIE_C_PIPE_CLK, 32 DT_PCIE_D_PIPE_CLK, 33 }; 34 35 enum { 36 P_BI_TCXO, 37 P_GCC_GPLL0_OUT_EVEN, 38 P_GCC_GPLL0_OUT_MAIN, 39 P_PCIE_A_PIPE_CLK, 40 P_PCIE_B_PIPE_CLK, 41 P_PCIE_C_PIPE_CLK, 42 P_PCIE_D_PIPE_CLK, 43 P_SLEEP_CLK, 44 }; 45 46 static struct clk_alpha_pll gcc_gpll0 = { 47 .offset = 0x0, 48 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 49 .clkr = { 50 .enable_reg = 0x9d020, 51 .enable_mask = BIT(0), 52 .hw.init = &(const struct clk_init_data) { 53 .name = "gcc_gpll0", 54 .parent_data = &(const struct clk_parent_data) { 55 .index = DT_BI_TCXO, 56 }, 57 .num_parents = 1, 58 .ops = &clk_alpha_pll_fixed_lucid_ole_ops, 59 }, 60 }, 61 }; 62 63 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { 64 { 0x1, 2 }, 65 { } 66 }; 67 68 static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { 69 .offset = 0x0, 70 .post_div_shift = 10, 71 .post_div_table = post_div_table_gcc_gpll0_out_even, 72 .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), 73 .width = 4, 74 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], 75 .clkr.hw.init = &(const struct clk_init_data) { 76 .name = "gcc_gpll0_out_even", 77 .parent_hws = (const struct clk_hw*[]) { 78 &gcc_gpll0.clkr.hw, 79 }, 80 .num_parents = 1, 81 .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, 82 }, 83 }; 84 85 static const struct parent_map gcc_parent_map_0[] = { 86 { P_BI_TCXO, 0 }, 87 { P_GCC_GPLL0_OUT_MAIN, 1 }, 88 { P_GCC_GPLL0_OUT_EVEN, 6 }, 89 }; 90 91 static const struct clk_parent_data gcc_parent_data_0[] = { 92 { .index = DT_BI_TCXO }, 93 { .hw = &gcc_gpll0.clkr.hw }, 94 { .hw = &gcc_gpll0_out_even.clkr.hw }, 95 }; 96 97 static const struct parent_map gcc_parent_map_1[] = { 98 { P_BI_TCXO, 0 }, 99 { P_SLEEP_CLK, 5 }, 100 }; 101 102 static const struct clk_parent_data gcc_parent_data_1[] = { 103 { .index = DT_BI_TCXO }, 104 { .index = DT_SLEEP_CLK }, 105 }; 106 107 static const struct parent_map gcc_parent_map_2[] = { 108 { P_BI_TCXO, 0 }, 109 { P_GCC_GPLL0_OUT_MAIN, 1 }, 110 { P_SLEEP_CLK, 5 }, 111 { P_GCC_GPLL0_OUT_EVEN, 6 }, 112 }; 113 114 static const struct clk_parent_data gcc_parent_data_2[] = { 115 { .index = DT_BI_TCXO }, 116 { .hw = &gcc_gpll0.clkr.hw }, 117 { .index = DT_SLEEP_CLK }, 118 { .hw = &gcc_gpll0_out_even.clkr.hw }, 119 }; 120 121 static const struct parent_map gcc_parent_map_3[] = { 122 { P_BI_TCXO, 0 }, 123 { P_GCC_GPLL0_OUT_MAIN, 1 }, 124 }; 125 126 static const struct clk_parent_data gcc_parent_data_3[] = { 127 { .index = DT_BI_TCXO }, 128 { .hw = &gcc_gpll0.clkr.hw }, 129 }; 130 131 static struct clk_regmap_phy_mux gcc_pcie_a_pipe_clk_src = { 132 .reg = 0x49094, 133 .clkr = { 134 .hw.init = &(const struct clk_init_data) { 135 .name = "gcc_pcie_a_pipe_clk_src", 136 .parent_data = &(const struct clk_parent_data){ 137 .index = DT_PCIE_A_PIPE_CLK, 138 }, 139 .num_parents = 1, 140 .ops = &clk_regmap_phy_mux_ops, 141 }, 142 }, 143 }; 144 145 static struct clk_regmap_phy_mux gcc_pcie_b_pipe_clk_src = { 146 .reg = 0x4a094, 147 .clkr = { 148 .hw.init = &(const struct clk_init_data) { 149 .name = "gcc_pcie_b_pipe_clk_src", 150 .parent_data = &(const struct clk_parent_data){ 151 .index = DT_PCIE_B_PIPE_CLK, 152 }, 153 .num_parents = 1, 154 .ops = &clk_regmap_phy_mux_ops, 155 }, 156 }, 157 }; 158 159 static struct clk_regmap_phy_mux gcc_pcie_c_pipe_clk_src = { 160 .reg = 0x4b094, 161 .clkr = { 162 .hw.init = &(const struct clk_init_data) { 163 .name = "gcc_pcie_c_pipe_clk_src", 164 .parent_data = &(const struct clk_parent_data){ 165 .index = DT_PCIE_C_PIPE_CLK, 166 }, 167 .num_parents = 1, 168 .ops = &clk_regmap_phy_mux_ops, 169 }, 170 }, 171 }; 172 173 static struct clk_regmap_phy_mux gcc_pcie_d_pipe_clk_src = { 174 .reg = 0x4c094, 175 .clkr = { 176 .hw.init = &(const struct clk_init_data) { 177 .name = "gcc_pcie_d_pipe_clk_src", 178 .parent_data = &(const struct clk_parent_data){ 179 .index = DT_PCIE_D_PIPE_CLK, 180 }, 181 .num_parents = 1, 182 .ops = &clk_regmap_phy_mux_ops, 183 }, 184 }, 185 }; 186 187 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { 188 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 189 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 190 F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), 191 { } 192 }; 193 194 static struct clk_rcg2 gcc_gp1_clk_src = { 195 .cmd_rcgr = 0x30004, 196 .mnd_width = 16, 197 .hid_width = 5, 198 .parent_map = gcc_parent_map_2, 199 .freq_tbl = ftbl_gcc_gp1_clk_src, 200 .hw_clk_ctrl = true, 201 .clkr.hw.init = &(const struct clk_init_data) { 202 .name = "gcc_gp1_clk_src", 203 .parent_data = gcc_parent_data_2, 204 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 205 .flags = CLK_SET_RATE_PARENT, 206 .ops = &clk_rcg2_shared_ops, 207 }, 208 }; 209 210 static struct clk_rcg2 gcc_gp2_clk_src = { 211 .cmd_rcgr = 0x31004, 212 .mnd_width = 16, 213 .hid_width = 5, 214 .parent_map = gcc_parent_map_2, 215 .freq_tbl = ftbl_gcc_gp1_clk_src, 216 .hw_clk_ctrl = true, 217 .clkr.hw.init = &(const struct clk_init_data) { 218 .name = "gcc_gp2_clk_src", 219 .parent_data = gcc_parent_data_2, 220 .num_parents = ARRAY_SIZE(gcc_parent_data_2), 221 .flags = CLK_SET_RATE_PARENT, 222 .ops = &clk_rcg2_shared_ops, 223 }, 224 }; 225 226 static const struct freq_tbl ftbl_gcc_pcie_a_aux_clk_src[] = { 227 F(19200000, P_BI_TCXO, 1, 0, 0), 228 { } 229 }; 230 231 static struct clk_rcg2 gcc_pcie_a_aux_clk_src = { 232 .cmd_rcgr = 0x49098, 233 .mnd_width = 16, 234 .hid_width = 5, 235 .parent_map = gcc_parent_map_1, 236 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 237 .hw_clk_ctrl = true, 238 .clkr.hw.init = &(const struct clk_init_data) { 239 .name = "gcc_pcie_a_aux_clk_src", 240 .parent_data = gcc_parent_data_1, 241 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 242 .flags = CLK_SET_RATE_PARENT, 243 .ops = &clk_rcg2_shared_ops, 244 }, 245 }; 246 247 static struct clk_rcg2 gcc_pcie_a_phy_aux_clk_src = { 248 .cmd_rcgr = 0x4d020, 249 .mnd_width = 16, 250 .hid_width = 5, 251 .parent_map = gcc_parent_map_1, 252 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 253 .hw_clk_ctrl = true, 254 .clkr.hw.init = &(const struct clk_init_data) { 255 .name = "gcc_pcie_a_phy_aux_clk_src", 256 .parent_data = gcc_parent_data_1, 257 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 258 .flags = CLK_SET_RATE_PARENT, 259 .ops = &clk_rcg2_shared_ops, 260 }, 261 }; 262 263 static const struct freq_tbl ftbl_gcc_pcie_a_phy_rchng_clk_src[] = { 264 F(66666667, P_GCC_GPLL0_OUT_MAIN, 9, 0, 0), 265 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 266 { } 267 }; 268 269 static struct clk_rcg2 gcc_pcie_a_phy_rchng_clk_src = { 270 .cmd_rcgr = 0x4907c, 271 .mnd_width = 0, 272 .hid_width = 5, 273 .parent_map = gcc_parent_map_0, 274 .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, 275 .hw_clk_ctrl = true, 276 .clkr.hw.init = &(const struct clk_init_data) { 277 .name = "gcc_pcie_a_phy_rchng_clk_src", 278 .parent_data = gcc_parent_data_0, 279 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 280 .flags = CLK_SET_RATE_PARENT, 281 .ops = &clk_rcg2_shared_ops, 282 }, 283 }; 284 285 static struct clk_rcg2 gcc_pcie_b_aux_clk_src = { 286 .cmd_rcgr = 0x4a098, 287 .mnd_width = 16, 288 .hid_width = 5, 289 .parent_map = gcc_parent_map_1, 290 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 291 .hw_clk_ctrl = true, 292 .clkr.hw.init = &(const struct clk_init_data) { 293 .name = "gcc_pcie_b_aux_clk_src", 294 .parent_data = gcc_parent_data_1, 295 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 296 .flags = CLK_SET_RATE_PARENT, 297 .ops = &clk_rcg2_shared_ops, 298 }, 299 }; 300 301 static struct clk_rcg2 gcc_pcie_b_phy_aux_clk_src = { 302 .cmd_rcgr = 0x4e020, 303 .mnd_width = 16, 304 .hid_width = 5, 305 .parent_map = gcc_parent_map_1, 306 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 307 .hw_clk_ctrl = true, 308 .clkr.hw.init = &(const struct clk_init_data) { 309 .name = "gcc_pcie_b_phy_aux_clk_src", 310 .parent_data = gcc_parent_data_1, 311 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 312 .flags = CLK_SET_RATE_PARENT, 313 .ops = &clk_rcg2_shared_ops, 314 }, 315 }; 316 317 static struct clk_rcg2 gcc_pcie_b_phy_rchng_clk_src = { 318 .cmd_rcgr = 0x4a07c, 319 .mnd_width = 0, 320 .hid_width = 5, 321 .parent_map = gcc_parent_map_0, 322 .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, 323 .hw_clk_ctrl = true, 324 .clkr.hw.init = &(const struct clk_init_data) { 325 .name = "gcc_pcie_b_phy_rchng_clk_src", 326 .parent_data = gcc_parent_data_0, 327 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 328 .flags = CLK_SET_RATE_PARENT, 329 .ops = &clk_rcg2_shared_ops, 330 }, 331 }; 332 333 static struct clk_rcg2 gcc_pcie_c_aux_clk_src = { 334 .cmd_rcgr = 0x4b098, 335 .mnd_width = 16, 336 .hid_width = 5, 337 .parent_map = gcc_parent_map_1, 338 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 339 .hw_clk_ctrl = true, 340 .clkr.hw.init = &(const struct clk_init_data) { 341 .name = "gcc_pcie_c_aux_clk_src", 342 .parent_data = gcc_parent_data_1, 343 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 344 .flags = CLK_SET_RATE_PARENT, 345 .ops = &clk_rcg2_shared_ops, 346 }, 347 }; 348 349 static struct clk_rcg2 gcc_pcie_c_phy_aux_clk_src = { 350 .cmd_rcgr = 0x4f020, 351 .mnd_width = 16, 352 .hid_width = 5, 353 .parent_map = gcc_parent_map_1, 354 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 355 .hw_clk_ctrl = true, 356 .clkr.hw.init = &(const struct clk_init_data) { 357 .name = "gcc_pcie_c_phy_aux_clk_src", 358 .parent_data = gcc_parent_data_1, 359 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 360 .flags = CLK_SET_RATE_PARENT, 361 .ops = &clk_rcg2_shared_ops, 362 }, 363 }; 364 365 static struct clk_rcg2 gcc_pcie_c_phy_rchng_clk_src = { 366 .cmd_rcgr = 0x4b07c, 367 .mnd_width = 0, 368 .hid_width = 5, 369 .parent_map = gcc_parent_map_3, 370 .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, 371 .hw_clk_ctrl = true, 372 .clkr.hw.init = &(const struct clk_init_data) { 373 .name = "gcc_pcie_c_phy_rchng_clk_src", 374 .parent_data = gcc_parent_data_3, 375 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 376 .flags = CLK_SET_RATE_PARENT, 377 .ops = &clk_rcg2_shared_ops, 378 }, 379 }; 380 381 static struct clk_rcg2 gcc_pcie_d_aux_clk_src = { 382 .cmd_rcgr = 0x4c098, 383 .mnd_width = 16, 384 .hid_width = 5, 385 .parent_map = gcc_parent_map_1, 386 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 387 .hw_clk_ctrl = true, 388 .clkr.hw.init = &(const struct clk_init_data) { 389 .name = "gcc_pcie_d_aux_clk_src", 390 .parent_data = gcc_parent_data_1, 391 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 392 .flags = CLK_SET_RATE_PARENT, 393 .ops = &clk_rcg2_shared_ops, 394 }, 395 }; 396 397 static struct clk_rcg2 gcc_pcie_d_phy_aux_clk_src = { 398 .cmd_rcgr = 0x50020, 399 .mnd_width = 16, 400 .hid_width = 5, 401 .parent_map = gcc_parent_map_1, 402 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 403 .hw_clk_ctrl = true, 404 .clkr.hw.init = &(const struct clk_init_data) { 405 .name = "gcc_pcie_d_phy_aux_clk_src", 406 .parent_data = gcc_parent_data_1, 407 .num_parents = ARRAY_SIZE(gcc_parent_data_1), 408 .flags = CLK_SET_RATE_PARENT, 409 .ops = &clk_rcg2_shared_ops, 410 }, 411 }; 412 413 static struct clk_rcg2 gcc_pcie_d_phy_rchng_clk_src = { 414 .cmd_rcgr = 0x4c07c, 415 .mnd_width = 0, 416 .hid_width = 5, 417 .parent_map = gcc_parent_map_3, 418 .freq_tbl = ftbl_gcc_pcie_a_phy_rchng_clk_src, 419 .hw_clk_ctrl = true, 420 .clkr.hw.init = &(const struct clk_init_data) { 421 .name = "gcc_pcie_d_phy_rchng_clk_src", 422 .parent_data = gcc_parent_data_3, 423 .num_parents = ARRAY_SIZE(gcc_parent_data_3), 424 .flags = CLK_SET_RATE_PARENT, 425 .ops = &clk_rcg2_shared_ops, 426 }, 427 }; 428 429 static struct clk_rcg2 gcc_pcie_noc_refgen_clk_src = { 430 .cmd_rcgr = 0x52094, 431 .mnd_width = 0, 432 .hid_width = 5, 433 .parent_map = gcc_parent_map_0, 434 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 435 .hw_clk_ctrl = true, 436 .clkr.hw.init = &(const struct clk_init_data) { 437 .name = "gcc_pcie_noc_refgen_clk_src", 438 .parent_data = gcc_parent_data_0, 439 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 440 .flags = CLK_SET_RATE_PARENT, 441 .ops = &clk_rcg2_shared_ops, 442 }, 443 }; 444 445 static struct clk_rcg2 gcc_pcie_noc_safety_clk_src = { 446 .cmd_rcgr = 0x520ac, 447 .mnd_width = 0, 448 .hid_width = 5, 449 .parent_map = gcc_parent_map_0, 450 .freq_tbl = ftbl_gcc_pcie_a_aux_clk_src, 451 .hw_clk_ctrl = true, 452 .clkr.hw.init = &(const struct clk_init_data) { 453 .name = "gcc_pcie_noc_safety_clk_src", 454 .parent_data = gcc_parent_data_0, 455 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 456 .flags = CLK_SET_RATE_PARENT, 457 .ops = &clk_rcg2_shared_ops, 458 }, 459 }; 460 461 static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { 462 F(40000000, P_GCC_GPLL0_OUT_MAIN, 15, 0, 0), 463 F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), 464 { } 465 }; 466 467 static struct clk_rcg2 gcc_pdm2_clk_src = { 468 .cmd_rcgr = 0x1a010, 469 .mnd_width = 0, 470 .hid_width = 5, 471 .parent_map = gcc_parent_map_0, 472 .freq_tbl = ftbl_gcc_pdm2_clk_src, 473 .hw_clk_ctrl = true, 474 .clkr.hw.init = &(const struct clk_init_data) { 475 .name = "gcc_pdm2_clk_src", 476 .parent_data = gcc_parent_data_0, 477 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 478 .flags = CLK_SET_RATE_PARENT, 479 .ops = &clk_rcg2_shared_ops, 480 }, 481 }; 482 483 static const struct freq_tbl ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src[] = { 484 F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), 485 F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), 486 F(19200000, P_BI_TCXO, 1, 0, 0), 487 F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), 488 F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), 489 F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), 490 F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375), 491 F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), 492 F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), 493 F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), 494 F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), 495 F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), 496 F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375), 497 F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75), 498 F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625), 499 F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), 500 F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), 501 F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), 502 { } 503 }; 504 505 static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = { 506 .name = "gcc_qupv3_wrap3_qspi_ref_clk_src", 507 .parent_data = gcc_parent_data_0, 508 .num_parents = ARRAY_SIZE(gcc_parent_data_0), 509 .flags = CLK_SET_RATE_PARENT, 510 .ops = &clk_rcg2_shared_no_init_park_ops, 511 }; 512 513 static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = { 514 .cmd_rcgr = 0x23174, 515 .mnd_width = 16, 516 .hid_width = 5, 517 .parent_map = gcc_parent_map_0, 518 .freq_tbl = ftbl_gcc_qupv3_wrap3_qspi_ref_clk_src, 519 .hw_clk_ctrl = true, 520 .clkr.hw.init = &gcc_qupv3_wrap3_qspi_ref_clk_src_init, 521 }; 522 523 static struct clk_regmap_div gcc_qupv3_wrap3_s0_clk_src = { 524 .reg = 0x2316c, 525 .shift = 0, 526 .width = 4, 527 .clkr.hw.init = &(const struct clk_init_data) { 528 .name = "gcc_qupv3_wrap3_s0_clk_src", 529 .parent_hws = (const struct clk_hw*[]) { 530 &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, 531 }, 532 .num_parents = 1, 533 .flags = CLK_SET_RATE_PARENT, 534 .ops = &clk_regmap_div_ro_ops, 535 }, 536 }; 537 538 static struct clk_branch gcc_boot_rom_ahb_clk = { 539 .halt_reg = 0x1f004, 540 .halt_check = BRANCH_HALT, 541 .clkr = { 542 .enable_reg = 0x1f004, 543 .enable_mask = BIT(0), 544 .hw.init = &(const struct clk_init_data) { 545 .name = "gcc_boot_rom_ahb_clk", 546 .ops = &clk_branch2_ops, 547 }, 548 }, 549 }; 550 551 static struct clk_branch gcc_gp1_clk = { 552 .halt_reg = 0x30000, 553 .halt_check = BRANCH_HALT, 554 .clkr = { 555 .enable_reg = 0x30000, 556 .enable_mask = BIT(0), 557 .hw.init = &(const struct clk_init_data) { 558 .name = "gcc_gp1_clk", 559 .parent_hws = (const struct clk_hw*[]) { 560 &gcc_gp1_clk_src.clkr.hw, 561 }, 562 .num_parents = 1, 563 .flags = CLK_SET_RATE_PARENT, 564 .ops = &clk_branch2_ops, 565 }, 566 }, 567 }; 568 569 static struct clk_branch gcc_gp2_clk = { 570 .halt_reg = 0x31000, 571 .halt_check = BRANCH_HALT, 572 .clkr = { 573 .enable_reg = 0x31000, 574 .enable_mask = BIT(0), 575 .hw.init = &(const struct clk_init_data) { 576 .name = "gcc_gp2_clk", 577 .parent_hws = (const struct clk_hw*[]) { 578 &gcc_gp2_clk_src.clkr.hw, 579 }, 580 .num_parents = 1, 581 .flags = CLK_SET_RATE_PARENT, 582 .ops = &clk_branch2_ops, 583 }, 584 }, 585 }; 586 587 static struct clk_branch gcc_mmu_0_tcu_vote_clk = { 588 .halt_reg = 0x7d094, 589 .halt_check = BRANCH_HALT_VOTED, 590 .clkr = { 591 .enable_reg = 0x7d094, 592 .enable_mask = BIT(0), 593 .hw.init = &(const struct clk_init_data) { 594 .name = "gcc_mmu_0_tcu_vote_clk", 595 .ops = &clk_branch2_ops, 596 }, 597 }, 598 }; 599 600 static struct clk_branch gcc_pcie_a_aux_clk = { 601 .halt_reg = 0x49058, 602 .halt_check = BRANCH_HALT_VOTED, 603 .hwcg_reg = 0x49058, 604 .hwcg_bit = 1, 605 .clkr = { 606 .enable_reg = 0x9d008, 607 .enable_mask = BIT(14), 608 .hw.init = &(const struct clk_init_data) { 609 .name = "gcc_pcie_a_aux_clk", 610 .parent_hws = (const struct clk_hw*[]) { 611 &gcc_pcie_a_aux_clk_src.clkr.hw, 612 }, 613 .num_parents = 1, 614 .flags = CLK_SET_RATE_PARENT, 615 .ops = &clk_branch2_ops, 616 }, 617 }, 618 }; 619 620 static struct clk_branch gcc_pcie_a_cfg_ahb_clk = { 621 .halt_reg = 0x49054, 622 .halt_check = BRANCH_HALT_VOTED, 623 .hwcg_reg = 0x49054, 624 .hwcg_bit = 1, 625 .clkr = { 626 .enable_reg = 0x9d008, 627 .enable_mask = BIT(13), 628 .hw.init = &(const struct clk_init_data) { 629 .name = "gcc_pcie_a_cfg_ahb_clk", 630 .ops = &clk_branch2_ops, 631 }, 632 }, 633 }; 634 635 static struct clk_branch gcc_pcie_a_dti_qtc_clk = { 636 .halt_reg = 0x49018, 637 .halt_check = BRANCH_HALT_SKIP, 638 .hwcg_reg = 0x49018, 639 .hwcg_bit = 1, 640 .clkr = { 641 .enable_reg = 0x9d008, 642 .enable_mask = BIT(8), 643 .hw.init = &(const struct clk_init_data) { 644 .name = "gcc_pcie_a_dti_qtc_clk", 645 .ops = &clk_branch2_ops, 646 }, 647 }, 648 }; 649 650 static struct clk_branch gcc_pcie_a_mstr_axi_clk = { 651 .halt_reg = 0x49040, 652 .halt_check = BRANCH_HALT_SKIP, 653 .hwcg_reg = 0x49040, 654 .hwcg_bit = 1, 655 .clkr = { 656 .enable_reg = 0x9d008, 657 .enable_mask = BIT(12), 658 .hw.init = &(const struct clk_init_data) { 659 .name = "gcc_pcie_a_mstr_axi_clk", 660 .ops = &clk_branch2_ops, 661 }, 662 }, 663 }; 664 665 static struct clk_branch gcc_pcie_a_phy_aux_clk = { 666 .halt_reg = 0x4d01c, 667 .halt_check = BRANCH_HALT_VOTED, 668 .clkr = { 669 .enable_reg = 0x9d010, 670 .enable_mask = BIT(12), 671 .hw.init = &(const struct clk_init_data) { 672 .name = "gcc_pcie_a_phy_aux_clk", 673 .parent_hws = (const struct clk_hw*[]) { 674 &gcc_pcie_a_phy_aux_clk_src.clkr.hw, 675 }, 676 .num_parents = 1, 677 .flags = CLK_SET_RATE_PARENT, 678 .ops = &clk_branch2_ops, 679 }, 680 }, 681 }; 682 683 static struct clk_branch gcc_pcie_a_phy_rchng_clk = { 684 .halt_reg = 0x49078, 685 .halt_check = BRANCH_HALT_VOTED, 686 .hwcg_reg = 0x49078, 687 .hwcg_bit = 1, 688 .clkr = { 689 .enable_reg = 0x9d008, 690 .enable_mask = BIT(16), 691 .hw.init = &(const struct clk_init_data) { 692 .name = "gcc_pcie_a_phy_rchng_clk", 693 .parent_hws = (const struct clk_hw*[]) { 694 &gcc_pcie_a_phy_rchng_clk_src.clkr.hw, 695 }, 696 .num_parents = 1, 697 .flags = CLK_SET_RATE_PARENT, 698 .ops = &clk_branch2_ops, 699 }, 700 }, 701 }; 702 703 static struct clk_branch gcc_pcie_a_pipe_clk = { 704 .halt_reg = 0x49068, 705 .halt_check = BRANCH_HALT_VOTED, 706 .hwcg_reg = 0x49068, 707 .hwcg_bit = 1, 708 .clkr = { 709 .enable_reg = 0x9d008, 710 .enable_mask = BIT(15), 711 .hw.init = &(const struct clk_init_data) { 712 .name = "gcc_pcie_a_pipe_clk", 713 .parent_hws = (const struct clk_hw*[]) { 714 &gcc_pcie_a_pipe_clk_src.clkr.hw, 715 }, 716 .num_parents = 1, 717 .flags = CLK_SET_RATE_PARENT, 718 .ops = &clk_branch2_ops, 719 }, 720 }, 721 }; 722 723 static struct clk_branch gcc_pcie_a_slv_axi_clk = { 724 .halt_reg = 0x4902c, 725 .halt_check = BRANCH_HALT_VOTED, 726 .hwcg_reg = 0x4902c, 727 .hwcg_bit = 1, 728 .clkr = { 729 .enable_reg = 0x9d008, 730 .enable_mask = BIT(11), 731 .hw.init = &(const struct clk_init_data) { 732 .name = "gcc_pcie_a_slv_axi_clk", 733 .ops = &clk_branch2_ops, 734 }, 735 }, 736 }; 737 738 static struct clk_branch gcc_pcie_a_slv_q2a_axi_clk = { 739 .halt_reg = 0x49024, 740 .halt_check = BRANCH_HALT_VOTED, 741 .hwcg_reg = 0x49024, 742 .hwcg_bit = 1, 743 .clkr = { 744 .enable_reg = 0x9d008, 745 .enable_mask = BIT(10), 746 .hw.init = &(const struct clk_init_data) { 747 .name = "gcc_pcie_a_slv_q2a_axi_clk", 748 .ops = &clk_branch2_ops, 749 }, 750 }, 751 }; 752 753 static struct clk_branch gcc_pcie_b_aux_clk = { 754 .halt_reg = 0x4a058, 755 .halt_check = BRANCH_HALT_VOTED, 756 .clkr = { 757 .enable_reg = 0x9d008, 758 .enable_mask = BIT(23), 759 .hw.init = &(const struct clk_init_data) { 760 .name = "gcc_pcie_b_aux_clk", 761 .parent_hws = (const struct clk_hw*[]) { 762 &gcc_pcie_b_aux_clk_src.clkr.hw, 763 }, 764 .num_parents = 1, 765 .flags = CLK_SET_RATE_PARENT, 766 .ops = &clk_branch2_ops, 767 }, 768 }, 769 }; 770 771 static struct clk_branch gcc_pcie_b_cfg_ahb_clk = { 772 .halt_reg = 0x4a054, 773 .halt_check = BRANCH_HALT_VOTED, 774 .hwcg_reg = 0x4a054, 775 .hwcg_bit = 1, 776 .clkr = { 777 .enable_reg = 0x9d008, 778 .enable_mask = BIT(22), 779 .hw.init = &(const struct clk_init_data) { 780 .name = "gcc_pcie_b_cfg_ahb_clk", 781 .ops = &clk_branch2_ops, 782 }, 783 }, 784 }; 785 786 static struct clk_branch gcc_pcie_b_dti_qtc_clk = { 787 .halt_reg = 0x4a018, 788 .halt_check = BRANCH_HALT_SKIP, 789 .hwcg_reg = 0x4a018, 790 .hwcg_bit = 1, 791 .clkr = { 792 .enable_reg = 0x9d008, 793 .enable_mask = BIT(17), 794 .hw.init = &(const struct clk_init_data) { 795 .name = "gcc_pcie_b_dti_qtc_clk", 796 .ops = &clk_branch2_ops, 797 }, 798 }, 799 }; 800 801 static struct clk_branch gcc_pcie_b_mstr_axi_clk = { 802 .halt_reg = 0x4a040, 803 .halt_check = BRANCH_HALT_SKIP, 804 .hwcg_reg = 0x4a040, 805 .hwcg_bit = 1, 806 .clkr = { 807 .enable_reg = 0x9d008, 808 .enable_mask = BIT(21), 809 .hw.init = &(const struct clk_init_data) { 810 .name = "gcc_pcie_b_mstr_axi_clk", 811 .ops = &clk_branch2_ops, 812 }, 813 }, 814 }; 815 816 static struct clk_branch gcc_pcie_b_phy_aux_clk = { 817 .halt_reg = 0x4e01c, 818 .halt_check = BRANCH_HALT_VOTED, 819 .clkr = { 820 .enable_reg = 0x9d010, 821 .enable_mask = BIT(13), 822 .hw.init = &(const struct clk_init_data) { 823 .name = "gcc_pcie_b_phy_aux_clk", 824 .parent_hws = (const struct clk_hw*[]) { 825 &gcc_pcie_b_phy_aux_clk_src.clkr.hw, 826 }, 827 .num_parents = 1, 828 .flags = CLK_SET_RATE_PARENT, 829 .ops = &clk_branch2_ops, 830 }, 831 }, 832 }; 833 834 static struct clk_branch gcc_pcie_b_phy_rchng_clk = { 835 .halt_reg = 0x4a078, 836 .halt_check = BRANCH_HALT_VOTED, 837 .clkr = { 838 .enable_reg = 0x9d008, 839 .enable_mask = BIT(25), 840 .hw.init = &(const struct clk_init_data) { 841 .name = "gcc_pcie_b_phy_rchng_clk", 842 .parent_hws = (const struct clk_hw*[]) { 843 &gcc_pcie_b_phy_rchng_clk_src.clkr.hw, 844 }, 845 .num_parents = 1, 846 .flags = CLK_SET_RATE_PARENT, 847 .ops = &clk_branch2_ops, 848 }, 849 }, 850 }; 851 852 static struct clk_branch gcc_pcie_b_pipe_clk = { 853 .halt_reg = 0x4a068, 854 .halt_check = BRANCH_HALT_VOTED, 855 .clkr = { 856 .enable_reg = 0x9d008, 857 .enable_mask = BIT(24), 858 .hw.init = &(const struct clk_init_data) { 859 .name = "gcc_pcie_b_pipe_clk", 860 .parent_hws = (const struct clk_hw*[]) { 861 &gcc_pcie_b_pipe_clk_src.clkr.hw, 862 }, 863 .num_parents = 1, 864 .flags = CLK_SET_RATE_PARENT, 865 .ops = &clk_branch2_ops, 866 }, 867 }, 868 }; 869 870 static struct clk_branch gcc_pcie_b_slv_axi_clk = { 871 .halt_reg = 0x4a02c, 872 .halt_check = BRANCH_HALT_VOTED, 873 .hwcg_reg = 0x4a02c, 874 .hwcg_bit = 1, 875 .clkr = { 876 .enable_reg = 0x9d008, 877 .enable_mask = BIT(20), 878 .hw.init = &(const struct clk_init_data) { 879 .name = "gcc_pcie_b_slv_axi_clk", 880 .ops = &clk_branch2_ops, 881 }, 882 }, 883 }; 884 885 static struct clk_branch gcc_pcie_b_slv_q2a_axi_clk = { 886 .halt_reg = 0x4a024, 887 .halt_check = BRANCH_HALT_VOTED, 888 .clkr = { 889 .enable_reg = 0x9d008, 890 .enable_mask = BIT(19), 891 .hw.init = &(const struct clk_init_data) { 892 .name = "gcc_pcie_b_slv_q2a_axi_clk", 893 .ops = &clk_branch2_ops, 894 }, 895 }, 896 }; 897 898 static struct clk_branch gcc_pcie_c_aux_clk = { 899 .halt_reg = 0x4b058, 900 .halt_check = BRANCH_HALT_VOTED, 901 .clkr = { 902 .enable_reg = 0x9d010, 903 .enable_mask = BIT(0), 904 .hw.init = &(const struct clk_init_data) { 905 .name = "gcc_pcie_c_aux_clk", 906 .parent_hws = (const struct clk_hw*[]) { 907 &gcc_pcie_c_aux_clk_src.clkr.hw, 908 }, 909 .num_parents = 1, 910 .flags = CLK_SET_RATE_PARENT, 911 .ops = &clk_branch2_ops, 912 }, 913 }, 914 }; 915 916 static struct clk_branch gcc_pcie_c_cfg_ahb_clk = { 917 .halt_reg = 0x4b054, 918 .halt_check = BRANCH_HALT_VOTED, 919 .hwcg_reg = 0x4b054, 920 .hwcg_bit = 1, 921 .clkr = { 922 .enable_reg = 0x9d008, 923 .enable_mask = BIT(31), 924 .hw.init = &(const struct clk_init_data) { 925 .name = "gcc_pcie_c_cfg_ahb_clk", 926 .ops = &clk_branch2_ops, 927 }, 928 }, 929 }; 930 931 static struct clk_branch gcc_pcie_c_dti_qtc_clk = { 932 .halt_reg = 0x4b018, 933 .halt_check = BRANCH_HALT_SKIP, 934 .hwcg_reg = 0x4b018, 935 .hwcg_bit = 1, 936 .clkr = { 937 .enable_reg = 0x9d008, 938 .enable_mask = BIT(26), 939 .hw.init = &(const struct clk_init_data) { 940 .name = "gcc_pcie_c_dti_qtc_clk", 941 .ops = &clk_branch2_ops, 942 }, 943 }, 944 }; 945 946 static struct clk_branch gcc_pcie_c_mstr_axi_clk = { 947 .halt_reg = 0x4b040, 948 .halt_check = BRANCH_HALT_SKIP, 949 .hwcg_reg = 0x4b040, 950 .hwcg_bit = 1, 951 .clkr = { 952 .enable_reg = 0x9d008, 953 .enable_mask = BIT(30), 954 .hw.init = &(const struct clk_init_data) { 955 .name = "gcc_pcie_c_mstr_axi_clk", 956 .ops = &clk_branch2_ops, 957 }, 958 }, 959 }; 960 961 static struct clk_branch gcc_pcie_c_phy_aux_clk = { 962 .halt_reg = 0x4f01c, 963 .halt_check = BRANCH_HALT_VOTED, 964 .clkr = { 965 .enable_reg = 0x9d010, 966 .enable_mask = BIT(14), 967 .hw.init = &(const struct clk_init_data) { 968 .name = "gcc_pcie_c_phy_aux_clk", 969 .parent_hws = (const struct clk_hw*[]) { 970 &gcc_pcie_c_phy_aux_clk_src.clkr.hw, 971 }, 972 .num_parents = 1, 973 .flags = CLK_SET_RATE_PARENT, 974 .ops = &clk_branch2_ops, 975 }, 976 }, 977 }; 978 979 static struct clk_branch gcc_pcie_c_phy_rchng_clk = { 980 .halt_reg = 0x4b078, 981 .halt_check = BRANCH_HALT_VOTED, 982 .clkr = { 983 .enable_reg = 0x9d010, 984 .enable_mask = BIT(2), 985 .hw.init = &(const struct clk_init_data) { 986 .name = "gcc_pcie_c_phy_rchng_clk", 987 .parent_hws = (const struct clk_hw*[]) { 988 &gcc_pcie_c_phy_rchng_clk_src.clkr.hw, 989 }, 990 .num_parents = 1, 991 .flags = CLK_SET_RATE_PARENT, 992 .ops = &clk_branch2_ops, 993 }, 994 }, 995 }; 996 997 static struct clk_branch gcc_pcie_c_pipe_clk = { 998 .halt_reg = 0x4b068, 999 .halt_check = BRANCH_HALT_VOTED, 1000 .clkr = { 1001 .enable_reg = 0x9d010, 1002 .enable_mask = BIT(1), 1003 .hw.init = &(const struct clk_init_data) { 1004 .name = "gcc_pcie_c_pipe_clk", 1005 .parent_hws = (const struct clk_hw*[]) { 1006 &gcc_pcie_c_pipe_clk_src.clkr.hw, 1007 }, 1008 .num_parents = 1, 1009 .flags = CLK_SET_RATE_PARENT, 1010 .ops = &clk_branch2_ops, 1011 }, 1012 }, 1013 }; 1014 1015 static struct clk_branch gcc_pcie_c_slv_axi_clk = { 1016 .halt_reg = 0x4b02c, 1017 .halt_check = BRANCH_HALT_VOTED, 1018 .hwcg_reg = 0x4b02c, 1019 .hwcg_bit = 1, 1020 .clkr = { 1021 .enable_reg = 0x9d008, 1022 .enable_mask = BIT(29), 1023 .hw.init = &(const struct clk_init_data) { 1024 .name = "gcc_pcie_c_slv_axi_clk", 1025 .ops = &clk_branch2_ops, 1026 }, 1027 }, 1028 }; 1029 1030 static struct clk_branch gcc_pcie_c_slv_q2a_axi_clk = { 1031 .halt_reg = 0x4b024, 1032 .halt_check = BRANCH_HALT_VOTED, 1033 .clkr = { 1034 .enable_reg = 0x9d008, 1035 .enable_mask = BIT(28), 1036 .hw.init = &(const struct clk_init_data) { 1037 .name = "gcc_pcie_c_slv_q2a_axi_clk", 1038 .ops = &clk_branch2_ops, 1039 }, 1040 }, 1041 }; 1042 1043 static struct clk_branch gcc_pcie_d_aux_clk = { 1044 .halt_reg = 0x4c058, 1045 .halt_check = BRANCH_HALT_VOTED, 1046 .clkr = { 1047 .enable_reg = 0x9d010, 1048 .enable_mask = BIT(9), 1049 .hw.init = &(const struct clk_init_data) { 1050 .name = "gcc_pcie_d_aux_clk", 1051 .parent_hws = (const struct clk_hw*[]) { 1052 &gcc_pcie_d_aux_clk_src.clkr.hw, 1053 }, 1054 .num_parents = 1, 1055 .flags = CLK_SET_RATE_PARENT, 1056 .ops = &clk_branch2_ops, 1057 }, 1058 }, 1059 }; 1060 1061 static struct clk_branch gcc_pcie_d_cfg_ahb_clk = { 1062 .halt_reg = 0x4c054, 1063 .halt_check = BRANCH_HALT_VOTED, 1064 .hwcg_reg = 0x4c054, 1065 .hwcg_bit = 1, 1066 .clkr = { 1067 .enable_reg = 0x9d010, 1068 .enable_mask = BIT(8), 1069 .hw.init = &(const struct clk_init_data) { 1070 .name = "gcc_pcie_d_cfg_ahb_clk", 1071 .ops = &clk_branch2_ops, 1072 }, 1073 }, 1074 }; 1075 1076 static struct clk_branch gcc_pcie_d_dti_qtc_clk = { 1077 .halt_reg = 0x4c018, 1078 .halt_check = BRANCH_HALT_SKIP, 1079 .hwcg_reg = 0x4c018, 1080 .hwcg_bit = 1, 1081 .clkr = { 1082 .enable_reg = 0x9d010, 1083 .enable_mask = BIT(3), 1084 .hw.init = &(const struct clk_init_data) { 1085 .name = "gcc_pcie_d_dti_qtc_clk", 1086 .ops = &clk_branch2_ops, 1087 }, 1088 }, 1089 }; 1090 1091 static struct clk_branch gcc_pcie_d_mstr_axi_clk = { 1092 .halt_reg = 0x4c040, 1093 .halt_check = BRANCH_HALT_SKIP, 1094 .hwcg_reg = 0x4c040, 1095 .hwcg_bit = 1, 1096 .clkr = { 1097 .enable_reg = 0x9d010, 1098 .enable_mask = BIT(7), 1099 .hw.init = &(const struct clk_init_data) { 1100 .name = "gcc_pcie_d_mstr_axi_clk", 1101 .ops = &clk_branch2_ops, 1102 }, 1103 }, 1104 }; 1105 1106 static struct clk_branch gcc_pcie_d_phy_aux_clk = { 1107 .halt_reg = 0x5001c, 1108 .halt_check = BRANCH_HALT_VOTED, 1109 .clkr = { 1110 .enable_reg = 0x9d010, 1111 .enable_mask = BIT(16), 1112 .hw.init = &(const struct clk_init_data) { 1113 .name = "gcc_pcie_d_phy_aux_clk", 1114 .parent_hws = (const struct clk_hw*[]) { 1115 &gcc_pcie_d_phy_aux_clk_src.clkr.hw, 1116 }, 1117 .num_parents = 1, 1118 .flags = CLK_SET_RATE_PARENT, 1119 .ops = &clk_branch2_ops, 1120 }, 1121 }, 1122 }; 1123 1124 static struct clk_branch gcc_pcie_d_phy_rchng_clk = { 1125 .halt_reg = 0x4c078, 1126 .halt_check = BRANCH_HALT_VOTED, 1127 .clkr = { 1128 .enable_reg = 0x9d010, 1129 .enable_mask = BIT(11), 1130 .hw.init = &(const struct clk_init_data) { 1131 .name = "gcc_pcie_d_phy_rchng_clk", 1132 .parent_hws = (const struct clk_hw*[]) { 1133 &gcc_pcie_d_phy_rchng_clk_src.clkr.hw, 1134 }, 1135 .num_parents = 1, 1136 .flags = CLK_SET_RATE_PARENT, 1137 .ops = &clk_branch2_ops, 1138 }, 1139 }, 1140 }; 1141 1142 static struct clk_branch gcc_pcie_d_pipe_clk = { 1143 .halt_reg = 0x4c068, 1144 .halt_check = BRANCH_HALT_VOTED, 1145 .clkr = { 1146 .enable_reg = 0x9d010, 1147 .enable_mask = BIT(10), 1148 .hw.init = &(const struct clk_init_data) { 1149 .name = "gcc_pcie_d_pipe_clk", 1150 .parent_hws = (const struct clk_hw*[]) { 1151 &gcc_pcie_d_pipe_clk_src.clkr.hw, 1152 }, 1153 .num_parents = 1, 1154 .flags = CLK_SET_RATE_PARENT, 1155 .ops = &clk_branch2_ops, 1156 }, 1157 }, 1158 }; 1159 1160 static struct clk_branch gcc_pcie_d_slv_axi_clk = { 1161 .halt_reg = 0x4c02c, 1162 .halt_check = BRANCH_HALT_VOTED, 1163 .hwcg_reg = 0x4c02c, 1164 .hwcg_bit = 1, 1165 .clkr = { 1166 .enable_reg = 0x9d010, 1167 .enable_mask = BIT(6), 1168 .hw.init = &(const struct clk_init_data) { 1169 .name = "gcc_pcie_d_slv_axi_clk", 1170 .ops = &clk_branch2_ops, 1171 }, 1172 }, 1173 }; 1174 1175 static struct clk_branch gcc_pcie_d_slv_q2a_axi_clk = { 1176 .halt_reg = 0x4c024, 1177 .halt_check = BRANCH_HALT_VOTED, 1178 .clkr = { 1179 .enable_reg = 0x9d010, 1180 .enable_mask = BIT(5), 1181 .hw.init = &(const struct clk_init_data) { 1182 .name = "gcc_pcie_d_slv_q2a_axi_clk", 1183 .ops = &clk_branch2_ops, 1184 }, 1185 }, 1186 }; 1187 1188 static struct clk_branch gcc_pcie_link_ahb_clk = { 1189 .halt_reg = 0x52464, 1190 .halt_check = BRANCH_HALT, 1191 .clkr = { 1192 .enable_reg = 0x52464, 1193 .enable_mask = BIT(0), 1194 .hw.init = &(const struct clk_init_data) { 1195 .name = "gcc_pcie_link_ahb_clk", 1196 .ops = &clk_branch2_ops, 1197 }, 1198 }, 1199 }; 1200 1201 static struct clk_branch gcc_pcie_link_xo_clk = { 1202 .halt_reg = 0x52468, 1203 .halt_check = BRANCH_HALT_VOTED, 1204 .hwcg_reg = 0x52468, 1205 .hwcg_bit = 1, 1206 .clkr = { 1207 .enable_reg = 0x52468, 1208 .enable_mask = BIT(0), 1209 .hw.init = &(const struct clk_init_data) { 1210 .name = "gcc_pcie_link_xo_clk", 1211 .ops = &clk_branch2_ops, 1212 }, 1213 }, 1214 }; 1215 1216 static struct clk_branch gcc_pcie_noc_async_bridge_clk = { 1217 .halt_reg = 0x52048, 1218 .halt_check = BRANCH_HALT_SKIP, 1219 .hwcg_reg = 0x52048, 1220 .hwcg_bit = 1, 1221 .clkr = { 1222 .enable_reg = 0x9d018, 1223 .enable_mask = BIT(18), 1224 .hw.init = &(const struct clk_init_data) { 1225 .name = "gcc_pcie_noc_async_bridge_clk", 1226 .ops = &clk_branch2_ops, 1227 }, 1228 }, 1229 }; 1230 1231 static struct clk_branch gcc_pcie_noc_cnoc_sf_qx_clk = { 1232 .halt_reg = 0x52040, 1233 .halt_check = BRANCH_HALT_VOTED, 1234 .hwcg_reg = 0x52040, 1235 .hwcg_bit = 1, 1236 .clkr = { 1237 .enable_reg = 0x9d010, 1238 .enable_mask = BIT(24), 1239 .hw.init = &(const struct clk_init_data) { 1240 .name = "gcc_pcie_noc_cnoc_sf_qx_clk", 1241 .ops = &clk_branch2_ops, 1242 }, 1243 }, 1244 }; 1245 1246 static struct clk_branch gcc_pcie_noc_m_cfg_clk = { 1247 .halt_reg = 0x52060, 1248 .halt_check = BRANCH_HALT_VOTED, 1249 .hwcg_reg = 0x52060, 1250 .hwcg_bit = 1, 1251 .clkr = { 1252 .enable_reg = 0x9d018, 1253 .enable_mask = BIT(4), 1254 .hw.init = &(const struct clk_init_data) { 1255 .name = "gcc_pcie_noc_m_cfg_clk", 1256 .ops = &clk_branch2_ops, 1257 }, 1258 }, 1259 }; 1260 1261 static struct clk_branch gcc_pcie_noc_m_pdb_clk = { 1262 .halt_reg = 0x52084, 1263 .halt_check = BRANCH_HALT_VOTED, 1264 .hwcg_reg = 0x52084, 1265 .hwcg_bit = 1, 1266 .clkr = { 1267 .enable_reg = 0x9d018, 1268 .enable_mask = BIT(8), 1269 .hw.init = &(const struct clk_init_data) { 1270 .name = "gcc_pcie_noc_m_pdb_clk", 1271 .ops = &clk_branch2_ops, 1272 }, 1273 }, 1274 }; 1275 1276 static struct clk_branch gcc_pcie_noc_mstr_axi_clk = { 1277 .halt_reg = 0x52050, 1278 .halt_check = BRANCH_HALT_SKIP, 1279 .hwcg_reg = 0x52050, 1280 .hwcg_bit = 1, 1281 .clkr = { 1282 .enable_reg = 0x9d010, 1283 .enable_mask = BIT(25), 1284 .hw.init = &(const struct clk_init_data) { 1285 .name = "gcc_pcie_noc_mstr_axi_clk", 1286 .ops = &clk_branch2_ops, 1287 }, 1288 }, 1289 }; 1290 1291 static struct clk_branch gcc_pcie_noc_pwrctl_clk = { 1292 .halt_reg = 0x52080, 1293 .halt_check = BRANCH_HALT_VOTED, 1294 .clkr = { 1295 .enable_reg = 0x9d018, 1296 .enable_mask = BIT(7), 1297 .hw.init = &(const struct clk_init_data) { 1298 .name = "gcc_pcie_noc_pwrctl_clk", 1299 .ops = &clk_branch2_ops, 1300 }, 1301 }, 1302 }; 1303 1304 static struct clk_branch gcc_pcie_noc_qosgen_extref_clk = { 1305 .halt_reg = 0x52074, 1306 .halt_check = BRANCH_HALT_VOTED, 1307 .clkr = { 1308 .enable_reg = 0x9d010, 1309 .enable_mask = BIT(19), 1310 .hw.init = &(const struct clk_init_data) { 1311 .name = "gcc_pcie_noc_qosgen_extref_clk", 1312 .ops = &clk_branch2_ops, 1313 }, 1314 }, 1315 }; 1316 1317 static struct clk_branch gcc_pcie_noc_refgen_clk = { 1318 .halt_reg = 0x52078, 1319 .halt_check = BRANCH_HALT, 1320 .clkr = { 1321 .enable_reg = 0x52078, 1322 .enable_mask = BIT(0), 1323 .hw.init = &(const struct clk_init_data) { 1324 .name = "gcc_pcie_noc_refgen_clk", 1325 .parent_hws = (const struct clk_hw*[]) { 1326 &gcc_pcie_noc_refgen_clk_src.clkr.hw, 1327 }, 1328 .num_parents = 1, 1329 .flags = CLK_SET_RATE_PARENT, 1330 .ops = &clk_branch2_ops, 1331 }, 1332 }, 1333 }; 1334 1335 static struct clk_branch gcc_pcie_noc_s_cfg_clk = { 1336 .halt_reg = 0x52064, 1337 .halt_check = BRANCH_HALT_VOTED, 1338 .clkr = { 1339 .enable_reg = 0x9d018, 1340 .enable_mask = BIT(5), 1341 .hw.init = &(const struct clk_init_data) { 1342 .name = "gcc_pcie_noc_s_cfg_clk", 1343 .ops = &clk_branch2_ops, 1344 }, 1345 }, 1346 }; 1347 1348 static struct clk_branch gcc_pcie_noc_s_pdb_clk = { 1349 .halt_reg = 0x5208c, 1350 .halt_check = BRANCH_HALT_VOTED, 1351 .hwcg_reg = 0x5208c, 1352 .hwcg_bit = 1, 1353 .clkr = { 1354 .enable_reg = 0x9d018, 1355 .enable_mask = BIT(9), 1356 .hw.init = &(const struct clk_init_data) { 1357 .name = "gcc_pcie_noc_s_pdb_clk", 1358 .ops = &clk_branch2_ops, 1359 }, 1360 }, 1361 }; 1362 1363 static struct clk_branch gcc_pcie_noc_safety_clk = { 1364 .halt_reg = 0x5207c, 1365 .halt_check = BRANCH_HALT, 1366 .clkr = { 1367 .enable_reg = 0x5207c, 1368 .enable_mask = BIT(0), 1369 .hw.init = &(const struct clk_init_data) { 1370 .name = "gcc_pcie_noc_safety_clk", 1371 .parent_hws = (const struct clk_hw*[]) { 1372 &gcc_pcie_noc_safety_clk_src.clkr.hw, 1373 }, 1374 .num_parents = 1, 1375 .flags = CLK_SET_RATE_PARENT, 1376 .ops = &clk_branch2_ops, 1377 }, 1378 }, 1379 }; 1380 1381 static struct clk_branch gcc_pcie_noc_slave_axi_clk = { 1382 .halt_reg = 0x52058, 1383 .halt_check = BRANCH_HALT_VOTED, 1384 .hwcg_reg = 0x52058, 1385 .hwcg_bit = 1, 1386 .clkr = { 1387 .enable_reg = 0x9d010, 1388 .enable_mask = BIT(26), 1389 .hw.init = &(const struct clk_init_data) { 1390 .name = "gcc_pcie_noc_slave_axi_clk", 1391 .ops = &clk_branch2_ops, 1392 }, 1393 }, 1394 }; 1395 1396 static struct clk_branch gcc_pcie_noc_tsctr_clk = { 1397 .halt_reg = 0x52070, 1398 .halt_check = BRANCH_HALT_VOTED, 1399 .clkr = { 1400 .enable_reg = 0x9d010, 1401 .enable_mask = BIT(18), 1402 .hw.init = &(const struct clk_init_data) { 1403 .name = "gcc_pcie_noc_tsctr_clk", 1404 .ops = &clk_branch2_ops, 1405 }, 1406 }, 1407 }; 1408 1409 static struct clk_branch gcc_pcie_noc_xo_clk = { 1410 .halt_reg = 0x52068, 1411 .halt_check = BRANCH_HALT_VOTED, 1412 .clkr = { 1413 .enable_reg = 0x9d018, 1414 .enable_mask = BIT(6), 1415 .hw.init = &(const struct clk_init_data) { 1416 .name = "gcc_pcie_noc_xo_clk", 1417 .ops = &clk_branch2_ops, 1418 }, 1419 }, 1420 }; 1421 1422 static struct clk_branch gcc_pdm2_clk = { 1423 .halt_reg = 0x1a00c, 1424 .halt_check = BRANCH_HALT, 1425 .clkr = { 1426 .enable_reg = 0x1a00c, 1427 .enable_mask = BIT(0), 1428 .hw.init = &(const struct clk_init_data) { 1429 .name = "gcc_pdm2_clk", 1430 .parent_hws = (const struct clk_hw*[]) { 1431 &gcc_pdm2_clk_src.clkr.hw, 1432 }, 1433 .num_parents = 1, 1434 .flags = CLK_SET_RATE_PARENT, 1435 .ops = &clk_branch2_ops, 1436 }, 1437 }, 1438 }; 1439 1440 static struct clk_branch gcc_pdm_ahb_clk = { 1441 .halt_reg = 0x1a004, 1442 .halt_check = BRANCH_HALT_VOTED, 1443 .hwcg_reg = 0x1a004, 1444 .hwcg_bit = 1, 1445 .clkr = { 1446 .enable_reg = 0x1a004, 1447 .enable_mask = BIT(0), 1448 .hw.init = &(const struct clk_init_data) { 1449 .name = "gcc_pdm_ahb_clk", 1450 .ops = &clk_branch2_ops, 1451 }, 1452 }, 1453 }; 1454 1455 static struct clk_branch gcc_pdm_xo4_clk = { 1456 .halt_reg = 0x1a008, 1457 .halt_check = BRANCH_HALT, 1458 .clkr = { 1459 .enable_reg = 0x1a008, 1460 .enable_mask = BIT(0), 1461 .hw.init = &(const struct clk_init_data) { 1462 .name = "gcc_pdm_xo4_clk", 1463 .ops = &clk_branch2_ops, 1464 }, 1465 }, 1466 }; 1467 1468 static struct clk_branch gcc_qupv3_wrap3_core_2x_clk = { 1469 .halt_reg = 0x23020, 1470 .halt_check = BRANCH_HALT_VOTED, 1471 .clkr = { 1472 .enable_reg = 0x9d000, 1473 .enable_mask = BIT(24), 1474 .hw.init = &(const struct clk_init_data) { 1475 .name = "gcc_qupv3_wrap3_core_2x_clk", 1476 .ops = &clk_branch2_ops, 1477 }, 1478 }, 1479 }; 1480 1481 static struct clk_branch gcc_qupv3_wrap3_core_clk = { 1482 .halt_reg = 0x2300c, 1483 .halt_check = BRANCH_HALT_VOTED, 1484 .clkr = { 1485 .enable_reg = 0x9d000, 1486 .enable_mask = BIT(23), 1487 .hw.init = &(const struct clk_init_data) { 1488 .name = "gcc_qupv3_wrap3_core_clk", 1489 .ops = &clk_branch2_ops, 1490 }, 1491 }, 1492 }; 1493 1494 static struct clk_branch gcc_qupv3_wrap3_m_clk = { 1495 .halt_reg = 0x23004, 1496 .halt_check = BRANCH_HALT_VOTED, 1497 .hwcg_reg = 0x23004, 1498 .hwcg_bit = 1, 1499 .clkr = { 1500 .enable_reg = 0x9d000, 1501 .enable_mask = BIT(22), 1502 .hw.init = &(const struct clk_init_data) { 1503 .name = "gcc_qupv3_wrap3_m_clk", 1504 .ops = &clk_branch2_ops, 1505 }, 1506 }, 1507 }; 1508 1509 static struct clk_branch gcc_qupv3_wrap3_qspi_ref_clk = { 1510 .halt_reg = 0x23170, 1511 .halt_check = BRANCH_HALT_VOTED, 1512 .clkr = { 1513 .enable_reg = 0x9d000, 1514 .enable_mask = BIT(26), 1515 .hw.init = &(const struct clk_init_data) { 1516 .name = "gcc_qupv3_wrap3_qspi_ref_clk", 1517 .parent_hws = (const struct clk_hw*[]) { 1518 &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr.hw, 1519 }, 1520 .num_parents = 1, 1521 .flags = CLK_SET_RATE_PARENT, 1522 .ops = &clk_branch2_ops, 1523 }, 1524 }, 1525 }; 1526 1527 static struct clk_branch gcc_qupv3_wrap3_s0_clk = { 1528 .halt_reg = 0x2315c, 1529 .halt_check = BRANCH_HALT_VOTED, 1530 .clkr = { 1531 .enable_reg = 0x9d000, 1532 .enable_mask = BIT(25), 1533 .hw.init = &(const struct clk_init_data) { 1534 .name = "gcc_qupv3_wrap3_s0_clk", 1535 .parent_hws = (const struct clk_hw*[]) { 1536 &gcc_qupv3_wrap3_s0_clk_src.clkr.hw, 1537 }, 1538 .num_parents = 1, 1539 .flags = CLK_SET_RATE_PARENT, 1540 .ops = &clk_branch2_ops, 1541 }, 1542 }, 1543 }; 1544 1545 static struct clk_branch gcc_qupv3_wrap3_s_ahb_clk = { 1546 .halt_reg = 0x23008, 1547 .halt_check = BRANCH_HALT_VOTED, 1548 .hwcg_reg = 0x23008, 1549 .hwcg_bit = 1, 1550 .clkr = { 1551 .enable_reg = 0x9d010, 1552 .enable_mask = BIT(15), 1553 .hw.init = &(const struct clk_init_data) { 1554 .name = "gcc_qupv3_wrap3_s_ahb_clk", 1555 .ops = &clk_branch2_ops, 1556 }, 1557 }, 1558 }; 1559 1560 static struct clk_branch gcc_smmu_pcie_qtc_vote_clk = { 1561 .halt_reg = 0x7d0b8, 1562 .halt_check = BRANCH_HALT_VOTED, 1563 .clkr = { 1564 .enable_reg = 0x7d0b8, 1565 .enable_mask = BIT(0), 1566 .hw.init = &(const struct clk_init_data) { 1567 .name = "gcc_smmu_pcie_qtc_vote_clk", 1568 .ops = &clk_branch2_ops, 1569 }, 1570 }, 1571 }; 1572 1573 static struct gdsc gcc_pcie_a_gdsc = { 1574 .gdscr = 0x49004, 1575 .en_rest_wait_val = 0x2, 1576 .en_few_wait_val = 0x2, 1577 .clk_dis_wait_val = 0xf, 1578 .collapse_ctrl = 0x8d02c, 1579 .collapse_mask = BIT(1), 1580 .pd = { 1581 .name = "gcc_pcie_a_gdsc", 1582 }, 1583 .pwrsts = PWRSTS_OFF_ON, 1584 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1585 }; 1586 1587 static struct gdsc gcc_pcie_a_phy_gdsc = { 1588 .gdscr = 0x4d004, 1589 .en_rest_wait_val = 0x2, 1590 .en_few_wait_val = 0x2, 1591 .clk_dis_wait_val = 0x2, 1592 .collapse_ctrl = 0x8d02c, 1593 .collapse_mask = BIT(5), 1594 .pd = { 1595 .name = "gcc_pcie_a_phy_gdsc", 1596 }, 1597 .pwrsts = PWRSTS_OFF_ON, 1598 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1599 }; 1600 1601 static struct gdsc gcc_pcie_b_gdsc = { 1602 .gdscr = 0x4a004, 1603 .en_rest_wait_val = 0x2, 1604 .en_few_wait_val = 0x2, 1605 .clk_dis_wait_val = 0xf, 1606 .collapse_ctrl = 0x8d02c, 1607 .collapse_mask = BIT(2), 1608 .pd = { 1609 .name = "gcc_pcie_b_gdsc", 1610 }, 1611 .pwrsts = PWRSTS_OFF_ON, 1612 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1613 }; 1614 1615 static struct gdsc gcc_pcie_b_phy_gdsc = { 1616 .gdscr = 0x4e004, 1617 .en_rest_wait_val = 0x2, 1618 .en_few_wait_val = 0x2, 1619 .clk_dis_wait_val = 0x2, 1620 .collapse_ctrl = 0x8d02c, 1621 .collapse_mask = BIT(6), 1622 .pd = { 1623 .name = "gcc_pcie_b_phy_gdsc", 1624 }, 1625 .pwrsts = PWRSTS_OFF_ON, 1626 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1627 }; 1628 1629 static struct gdsc gcc_pcie_c_gdsc = { 1630 .gdscr = 0x4b004, 1631 .en_rest_wait_val = 0x2, 1632 .en_few_wait_val = 0x2, 1633 .clk_dis_wait_val = 0xf, 1634 .collapse_ctrl = 0x8d02c, 1635 .collapse_mask = BIT(3), 1636 .pd = { 1637 .name = "gcc_pcie_c_gdsc", 1638 }, 1639 .pwrsts = PWRSTS_OFF_ON, 1640 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1641 }; 1642 1643 static struct gdsc gcc_pcie_c_phy_gdsc = { 1644 .gdscr = 0x4f004, 1645 .en_rest_wait_val = 0x2, 1646 .en_few_wait_val = 0x2, 1647 .clk_dis_wait_val = 0x2, 1648 .collapse_ctrl = 0x8d02c, 1649 .collapse_mask = BIT(7), 1650 .pd = { 1651 .name = "gcc_pcie_c_phy_gdsc", 1652 }, 1653 .pwrsts = PWRSTS_OFF_ON, 1654 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1655 }; 1656 1657 static struct gdsc gcc_pcie_d_gdsc = { 1658 .gdscr = 0x4c004, 1659 .en_rest_wait_val = 0x2, 1660 .en_few_wait_val = 0x2, 1661 .clk_dis_wait_val = 0xf, 1662 .collapse_ctrl = 0x8d02c, 1663 .collapse_mask = BIT(4), 1664 .pd = { 1665 .name = "gcc_pcie_d_gdsc", 1666 }, 1667 .pwrsts = PWRSTS_OFF_ON, 1668 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1669 }; 1670 1671 static struct gdsc gcc_pcie_d_phy_gdsc = { 1672 .gdscr = 0x50004, 1673 .en_rest_wait_val = 0x2, 1674 .en_few_wait_val = 0x2, 1675 .clk_dis_wait_val = 0x2, 1676 .collapse_ctrl = 0x8d02c, 1677 .collapse_mask = BIT(8), 1678 .pd = { 1679 .name = "gcc_pcie_d_phy_gdsc", 1680 }, 1681 .pwrsts = PWRSTS_OFF_ON, 1682 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1683 }; 1684 1685 static struct gdsc gcc_pcie_noc_gdsc = { 1686 .gdscr = 0x52004, 1687 .gds_hw_ctrl = 0x52018, 1688 .en_rest_wait_val = 0x2, 1689 .en_few_wait_val = 0x2, 1690 .clk_dis_wait_val = 0xf, 1691 .collapse_ctrl = 0x8d02c, 1692 .collapse_mask = BIT(0), 1693 .pd = { 1694 .name = "gcc_pcie_noc_gdsc", 1695 }, 1696 .pwrsts = PWRSTS_OFF_ON, 1697 .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE, 1698 }; 1699 1700 static struct clk_regmap *gcc_nord_clocks[] = { 1701 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 1702 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 1703 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, 1704 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 1705 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, 1706 [GCC_GPLL0] = &gcc_gpll0.clkr, 1707 [GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr, 1708 [GCC_MMU_0_TCU_VOTE_CLK] = &gcc_mmu_0_tcu_vote_clk.clkr, 1709 [GCC_PCIE_A_AUX_CLK] = &gcc_pcie_a_aux_clk.clkr, 1710 [GCC_PCIE_A_AUX_CLK_SRC] = &gcc_pcie_a_aux_clk_src.clkr, 1711 [GCC_PCIE_A_CFG_AHB_CLK] = &gcc_pcie_a_cfg_ahb_clk.clkr, 1712 [GCC_PCIE_A_DTI_QTC_CLK] = &gcc_pcie_a_dti_qtc_clk.clkr, 1713 [GCC_PCIE_A_MSTR_AXI_CLK] = &gcc_pcie_a_mstr_axi_clk.clkr, 1714 [GCC_PCIE_A_PHY_AUX_CLK] = &gcc_pcie_a_phy_aux_clk.clkr, 1715 [GCC_PCIE_A_PHY_AUX_CLK_SRC] = &gcc_pcie_a_phy_aux_clk_src.clkr, 1716 [GCC_PCIE_A_PHY_RCHNG_CLK] = &gcc_pcie_a_phy_rchng_clk.clkr, 1717 [GCC_PCIE_A_PHY_RCHNG_CLK_SRC] = &gcc_pcie_a_phy_rchng_clk_src.clkr, 1718 [GCC_PCIE_A_PIPE_CLK] = &gcc_pcie_a_pipe_clk.clkr, 1719 [GCC_PCIE_A_PIPE_CLK_SRC] = &gcc_pcie_a_pipe_clk_src.clkr, 1720 [GCC_PCIE_A_SLV_AXI_CLK] = &gcc_pcie_a_slv_axi_clk.clkr, 1721 [GCC_PCIE_A_SLV_Q2A_AXI_CLK] = &gcc_pcie_a_slv_q2a_axi_clk.clkr, 1722 [GCC_PCIE_B_AUX_CLK] = &gcc_pcie_b_aux_clk.clkr, 1723 [GCC_PCIE_B_AUX_CLK_SRC] = &gcc_pcie_b_aux_clk_src.clkr, 1724 [GCC_PCIE_B_CFG_AHB_CLK] = &gcc_pcie_b_cfg_ahb_clk.clkr, 1725 [GCC_PCIE_B_DTI_QTC_CLK] = &gcc_pcie_b_dti_qtc_clk.clkr, 1726 [GCC_PCIE_B_MSTR_AXI_CLK] = &gcc_pcie_b_mstr_axi_clk.clkr, 1727 [GCC_PCIE_B_PHY_AUX_CLK] = &gcc_pcie_b_phy_aux_clk.clkr, 1728 [GCC_PCIE_B_PHY_AUX_CLK_SRC] = &gcc_pcie_b_phy_aux_clk_src.clkr, 1729 [GCC_PCIE_B_PHY_RCHNG_CLK] = &gcc_pcie_b_phy_rchng_clk.clkr, 1730 [GCC_PCIE_B_PHY_RCHNG_CLK_SRC] = &gcc_pcie_b_phy_rchng_clk_src.clkr, 1731 [GCC_PCIE_B_PIPE_CLK] = &gcc_pcie_b_pipe_clk.clkr, 1732 [GCC_PCIE_B_PIPE_CLK_SRC] = &gcc_pcie_b_pipe_clk_src.clkr, 1733 [GCC_PCIE_B_SLV_AXI_CLK] = &gcc_pcie_b_slv_axi_clk.clkr, 1734 [GCC_PCIE_B_SLV_Q2A_AXI_CLK] = &gcc_pcie_b_slv_q2a_axi_clk.clkr, 1735 [GCC_PCIE_C_AUX_CLK] = &gcc_pcie_c_aux_clk.clkr, 1736 [GCC_PCIE_C_AUX_CLK_SRC] = &gcc_pcie_c_aux_clk_src.clkr, 1737 [GCC_PCIE_C_CFG_AHB_CLK] = &gcc_pcie_c_cfg_ahb_clk.clkr, 1738 [GCC_PCIE_C_DTI_QTC_CLK] = &gcc_pcie_c_dti_qtc_clk.clkr, 1739 [GCC_PCIE_C_MSTR_AXI_CLK] = &gcc_pcie_c_mstr_axi_clk.clkr, 1740 [GCC_PCIE_C_PHY_AUX_CLK] = &gcc_pcie_c_phy_aux_clk.clkr, 1741 [GCC_PCIE_C_PHY_AUX_CLK_SRC] = &gcc_pcie_c_phy_aux_clk_src.clkr, 1742 [GCC_PCIE_C_PHY_RCHNG_CLK] = &gcc_pcie_c_phy_rchng_clk.clkr, 1743 [GCC_PCIE_C_PHY_RCHNG_CLK_SRC] = &gcc_pcie_c_phy_rchng_clk_src.clkr, 1744 [GCC_PCIE_C_PIPE_CLK] = &gcc_pcie_c_pipe_clk.clkr, 1745 [GCC_PCIE_C_PIPE_CLK_SRC] = &gcc_pcie_c_pipe_clk_src.clkr, 1746 [GCC_PCIE_C_SLV_AXI_CLK] = &gcc_pcie_c_slv_axi_clk.clkr, 1747 [GCC_PCIE_C_SLV_Q2A_AXI_CLK] = &gcc_pcie_c_slv_q2a_axi_clk.clkr, 1748 [GCC_PCIE_D_AUX_CLK] = &gcc_pcie_d_aux_clk.clkr, 1749 [GCC_PCIE_D_AUX_CLK_SRC] = &gcc_pcie_d_aux_clk_src.clkr, 1750 [GCC_PCIE_D_CFG_AHB_CLK] = &gcc_pcie_d_cfg_ahb_clk.clkr, 1751 [GCC_PCIE_D_DTI_QTC_CLK] = &gcc_pcie_d_dti_qtc_clk.clkr, 1752 [GCC_PCIE_D_MSTR_AXI_CLK] = &gcc_pcie_d_mstr_axi_clk.clkr, 1753 [GCC_PCIE_D_PHY_AUX_CLK] = &gcc_pcie_d_phy_aux_clk.clkr, 1754 [GCC_PCIE_D_PHY_AUX_CLK_SRC] = &gcc_pcie_d_phy_aux_clk_src.clkr, 1755 [GCC_PCIE_D_PHY_RCHNG_CLK] = &gcc_pcie_d_phy_rchng_clk.clkr, 1756 [GCC_PCIE_D_PHY_RCHNG_CLK_SRC] = &gcc_pcie_d_phy_rchng_clk_src.clkr, 1757 [GCC_PCIE_D_PIPE_CLK] = &gcc_pcie_d_pipe_clk.clkr, 1758 [GCC_PCIE_D_PIPE_CLK_SRC] = &gcc_pcie_d_pipe_clk_src.clkr, 1759 [GCC_PCIE_D_SLV_AXI_CLK] = &gcc_pcie_d_slv_axi_clk.clkr, 1760 [GCC_PCIE_D_SLV_Q2A_AXI_CLK] = &gcc_pcie_d_slv_q2a_axi_clk.clkr, 1761 [GCC_PCIE_LINK_AHB_CLK] = &gcc_pcie_link_ahb_clk.clkr, 1762 [GCC_PCIE_LINK_XO_CLK] = &gcc_pcie_link_xo_clk.clkr, 1763 [GCC_PCIE_NOC_ASYNC_BRIDGE_CLK] = &gcc_pcie_noc_async_bridge_clk.clkr, 1764 [GCC_PCIE_NOC_CNOC_SF_QX_CLK] = &gcc_pcie_noc_cnoc_sf_qx_clk.clkr, 1765 [GCC_PCIE_NOC_M_CFG_CLK] = &gcc_pcie_noc_m_cfg_clk.clkr, 1766 [GCC_PCIE_NOC_M_PDB_CLK] = &gcc_pcie_noc_m_pdb_clk.clkr, 1767 [GCC_PCIE_NOC_MSTR_AXI_CLK] = &gcc_pcie_noc_mstr_axi_clk.clkr, 1768 [GCC_PCIE_NOC_PWRCTL_CLK] = &gcc_pcie_noc_pwrctl_clk.clkr, 1769 [GCC_PCIE_NOC_QOSGEN_EXTREF_CLK] = &gcc_pcie_noc_qosgen_extref_clk.clkr, 1770 [GCC_PCIE_NOC_REFGEN_CLK] = &gcc_pcie_noc_refgen_clk.clkr, 1771 [GCC_PCIE_NOC_REFGEN_CLK_SRC] = &gcc_pcie_noc_refgen_clk_src.clkr, 1772 [GCC_PCIE_NOC_S_CFG_CLK] = &gcc_pcie_noc_s_cfg_clk.clkr, 1773 [GCC_PCIE_NOC_S_PDB_CLK] = &gcc_pcie_noc_s_pdb_clk.clkr, 1774 [GCC_PCIE_NOC_SAFETY_CLK] = &gcc_pcie_noc_safety_clk.clkr, 1775 [GCC_PCIE_NOC_SAFETY_CLK_SRC] = &gcc_pcie_noc_safety_clk_src.clkr, 1776 [GCC_PCIE_NOC_SLAVE_AXI_CLK] = &gcc_pcie_noc_slave_axi_clk.clkr, 1777 [GCC_PCIE_NOC_TSCTR_CLK] = &gcc_pcie_noc_tsctr_clk.clkr, 1778 [GCC_PCIE_NOC_XO_CLK] = &gcc_pcie_noc_xo_clk.clkr, 1779 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 1780 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, 1781 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 1782 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, 1783 [GCC_QUPV3_WRAP3_CORE_2X_CLK] = &gcc_qupv3_wrap3_core_2x_clk.clkr, 1784 [GCC_QUPV3_WRAP3_CORE_CLK] = &gcc_qupv3_wrap3_core_clk.clkr, 1785 [GCC_QUPV3_WRAP3_M_CLK] = &gcc_qupv3_wrap3_m_clk.clkr, 1786 [GCC_QUPV3_WRAP3_QSPI_REF_CLK] = &gcc_qupv3_wrap3_qspi_ref_clk.clkr, 1787 [GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap3_qspi_ref_clk_src.clkr, 1788 [GCC_QUPV3_WRAP3_S0_CLK] = &gcc_qupv3_wrap3_s0_clk.clkr, 1789 [GCC_QUPV3_WRAP3_S0_CLK_SRC] = &gcc_qupv3_wrap3_s0_clk_src.clkr, 1790 [GCC_QUPV3_WRAP3_S_AHB_CLK] = &gcc_qupv3_wrap3_s_ahb_clk.clkr, 1791 [GCC_SMMU_PCIE_QTC_VOTE_CLK] = &gcc_smmu_pcie_qtc_vote_clk.clkr, 1792 }; 1793 1794 static struct gdsc *gcc_nord_gdscs[] = { 1795 [GCC_PCIE_A_GDSC] = &gcc_pcie_a_gdsc, 1796 [GCC_PCIE_A_PHY_GDSC] = &gcc_pcie_a_phy_gdsc, 1797 [GCC_PCIE_B_GDSC] = &gcc_pcie_b_gdsc, 1798 [GCC_PCIE_B_PHY_GDSC] = &gcc_pcie_b_phy_gdsc, 1799 [GCC_PCIE_C_GDSC] = &gcc_pcie_c_gdsc, 1800 [GCC_PCIE_C_PHY_GDSC] = &gcc_pcie_c_phy_gdsc, 1801 [GCC_PCIE_D_GDSC] = &gcc_pcie_d_gdsc, 1802 [GCC_PCIE_D_PHY_GDSC] = &gcc_pcie_d_phy_gdsc, 1803 [GCC_PCIE_NOC_GDSC] = &gcc_pcie_noc_gdsc, 1804 }; 1805 1806 static const struct qcom_reset_map gcc_nord_resets[] = { 1807 [GCC_PCIE_A_BCR] = { 0x49000 }, 1808 [GCC_PCIE_A_LINK_DOWN_BCR] = { 0xb9000 }, 1809 [GCC_PCIE_A_NOCSR_COM_PHY_BCR] = { 0xb900c }, 1810 [GCC_PCIE_A_PHY_BCR] = { 0x4d000 }, 1811 [GCC_PCIE_A_PHY_CFG_AHB_BCR] = { 0xb9014 }, 1812 [GCC_PCIE_A_PHY_COM_BCR] = { 0xb9018 }, 1813 [GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR] = { 0xb9010 }, 1814 [GCC_PCIE_B_BCR] = { 0x4a000 }, 1815 [GCC_PCIE_B_LINK_DOWN_BCR] = { 0xba000 }, 1816 [GCC_PCIE_B_NOCSR_COM_PHY_BCR] = { 0xba008 }, 1817 [GCC_PCIE_B_PHY_BCR] = { 0x4e000 }, 1818 [GCC_PCIE_B_PHY_CFG_AHB_BCR] = { 0xba010 }, 1819 [GCC_PCIE_B_PHY_COM_BCR] = { 0xba014 }, 1820 [GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR] = { 0xba00c }, 1821 [GCC_PCIE_C_BCR] = { 0x4b000 }, 1822 [GCC_PCIE_C_LINK_DOWN_BCR] = { 0xbb07c }, 1823 [GCC_PCIE_C_NOCSR_COM_PHY_BCR] = { 0xbb084 }, 1824 [GCC_PCIE_C_PHY_BCR] = { 0x4f000 }, 1825 [GCC_PCIE_C_PHY_CFG_AHB_BCR] = { 0xbb08c }, 1826 [GCC_PCIE_C_PHY_COM_BCR] = { 0xbb090 }, 1827 [GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR] = { 0xbb088 }, 1828 [GCC_PCIE_D_BCR] = { 0x4c000 }, 1829 [GCC_PCIE_D_LINK_DOWN_BCR] = { 0xbc000 }, 1830 [GCC_PCIE_D_NOCSR_COM_PHY_BCR] = { 0xbc008 }, 1831 [GCC_PCIE_D_PHY_BCR] = { 0x50000 }, 1832 [GCC_PCIE_D_PHY_CFG_AHB_BCR] = { 0xbc010 }, 1833 [GCC_PCIE_D_PHY_COM_BCR] = { 0xbc014 }, 1834 [GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR] = { 0xbc00c }, 1835 [GCC_PCIE_NOC_BCR] = { 0x52000 }, 1836 [GCC_PDM_BCR] = { 0x1a000 }, 1837 [GCC_QUPV3_WRAPPER_3_BCR] = { 0x23000 }, 1838 [GCC_TCSR_PCIE_BCR] = { 0xb901c }, 1839 }; 1840 1841 static const struct clk_rcg_dfs_data gcc_nord_dfs_clocks[] = { 1842 DEFINE_RCG_DFS(gcc_qupv3_wrap3_qspi_ref_clk_src), 1843 }; 1844 1845 static const struct regmap_config gcc_nord_regmap_config = { 1846 .reg_bits = 32, 1847 .reg_stride = 4, 1848 .val_bits = 32, 1849 .max_register = 0x1f41f0, 1850 .fast_io = true, 1851 }; 1852 1853 static struct qcom_cc_driver_data gcc_nord_driver_data = { 1854 .dfs_rcgs = gcc_nord_dfs_clocks, 1855 .num_dfs_rcgs = ARRAY_SIZE(gcc_nord_dfs_clocks), 1856 }; 1857 1858 static const struct qcom_cc_desc gcc_nord_desc = { 1859 .config = &gcc_nord_regmap_config, 1860 .clks = gcc_nord_clocks, 1861 .num_clks = ARRAY_SIZE(gcc_nord_clocks), 1862 .resets = gcc_nord_resets, 1863 .num_resets = ARRAY_SIZE(gcc_nord_resets), 1864 .gdscs = gcc_nord_gdscs, 1865 .num_gdscs = ARRAY_SIZE(gcc_nord_gdscs), 1866 .use_rpm = true, 1867 .driver_data = &gcc_nord_driver_data, 1868 }; 1869 1870 static const struct of_device_id gcc_nord_match_table[] = { 1871 { .compatible = "qcom,nord-gcc" }, 1872 { } 1873 }; 1874 MODULE_DEVICE_TABLE(of, gcc_nord_match_table); 1875 1876 static int gcc_nord_probe(struct platform_device *pdev) 1877 { 1878 return qcom_cc_probe(pdev, &gcc_nord_desc); 1879 } 1880 1881 static struct platform_driver gcc_nord_driver = { 1882 .probe = gcc_nord_probe, 1883 .driver = { 1884 .name = "gcc-nord", 1885 .of_match_table = gcc_nord_match_table, 1886 }, 1887 }; 1888 1889 static int __init gcc_nord_init(void) 1890 { 1891 return platform_driver_register(&gcc_nord_driver); 1892 } 1893 subsys_initcall(gcc_nord_init); 1894 1895 static void __exit gcc_nord_exit(void) 1896 { 1897 platform_driver_unregister(&gcc_nord_driver); 1898 } 1899 module_exit(gcc_nord_exit); 1900 1901 MODULE_DESCRIPTION("QTI GCC NORD Driver"); 1902 MODULE_LICENSE("GPL"); 1903