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/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sc7280-venus.yaml103 reg = <0x0aa00000 0xd0600>;
119 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
120 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
123 iommus = <&apps_smmu 0x2180 0x20>,
124 <&apps_smmu 0x2184 0x20>;
137 iommus = <&apps_smmu 0x21a2 0x0>;
/linux/arch/arm/boot/dts/ti/omap/
H A Dlogicpd-torpedo-37xx-devkit.dts19 gpio = <&gpio5 29 0>; /* gpio157 */
34 interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
35 pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>;
42 #size-cells = <0>;
70 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat4.sdmmc3_dat0 */
71 OMAP3_CORE1_IOPAD(0x2166, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat5.sdmmc3_dat1 */
72 OMAP3_CORE1_IOPAD(0x2168, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat2 */
73 OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc2_dat6.sdmmc3_dat3 */
74 OMAP3_CORE1_IOPAD(0x2184, PIN_INPUT_PULLUP | MUX_MODE4) /* mcbsp4_clkx.gpio_152 */
75 OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr.gpio_157 */
[all …]
H A Domap3-cm-t3517.dts25 pinctrl-0 = <
48 OMAP3_WKUP_IOPAD(0x2a0e, PIN_OUTPUT | MUX_MODE4) /* sys_boot2.gpio_4 */
49 OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE4) /* sys_boot4.gpio_6 */
58 OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE4) /* uart2_tx.gpio_146 */
64 OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */
70 OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */
76 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */
77 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */
78 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */
79 OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */
[all …]
H A Domap3-n950-n9.dtsi12 cpu@0 {
19 reg = <0x80000000 0x40000000>; /* 1 GB */
47 pinctrl-0 = <&debug_leds>;
54 #clock-cells = <0>;
62 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */
63 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */
69 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */
75 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
76 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
77 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
[all …]
H A Dlogicpd-som-lv-baseboard.dtsi7 pinctrl-0 = <&gpio_key_pins>;
26 pinctrl-0 = <&led_pins &led_pins_wkup>;
55 pinctrl-0 = <&mcbsp2_pins>;
64 ranges = <0 0 0x30000000 0x1000000 /* CS0: 16MB for NAND */
65 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */
66 2 0 0x10000000 0x2000000>; /* CS2: 32MB for NOR */
70 pinctrl-0 = <&lan9221_pins>;
73 reg = <1 0 0xff>;
86 pinctrl-0 = <&dss_dpi_pins1>;
111 pinctrl-0 = <&lcd_enable_pin>;
[all …]
H A Domap3-n900.dts46 cpu@0 {
58 pinctrl-0 = <&debug_leds>;
64 reg = <0x80000000 0x10000000>; /* 256 MB */
117 gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; /* 160 */
156 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
164 ti,clock-source = <0x00>; /* timer_sys_ck */
169 pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
181 #clock-cells = <0>;
190 pinctrl-0 = <&camera_pins>;
200 data-lanes = <0>;
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr600_reg.h31 #define R600_PCIE_PORT_INDEX 0x0038
32 #define R600_PCIE_PORT_DATA 0x003c
34 #define R600_RCU_INDEX 0x0100
35 #define R600_RCU_DATA 0x0104
37 #define R600_UVD_CTX_INDEX 0xf4a0
38 #define R600_UVD_CTX_DATA 0xf4a4
40 #define R600_MC_VM_FB_LOCATION 0x2180
41 #define R600_MC_FB_BASE_MASK 0x0000FFFF
42 #define R600_MC_FB_BASE_SHIFT 0
43 #define R600_MC_FB_TOP_MASK 0xFFFF0000
[all …]
H A Dr300_reg.h35 #define R300_MC_INIT_MISC_LAT_TIMER 0x180
36 # define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0
45 #define R300_MC_INIT_GFX_LAT_TIMER 0x154
46 # define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0
63 #define R300_SE_VPORT_XSCALE 0x1D98
64 #define R300_SE_VPORT_XOFFSET 0x1D9C
65 #define R300_SE_VPORT_YSCALE 0x1DA0
66 #define R300_SE_VPORT_YOFFSET 0x1DA4
67 #define R300_SE_VPORT_ZSCALE 0x1DA8
68 #define R300_SE_VPORT_ZOFFSET 0x1DAC
[all …]
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr3001 r300 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Drs6001 rs600 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr4201 r420 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/drivers/media/i2c/
H A Dtda1997x_regs.h6 /* Page 0x00 - General Control */
7 #define REG_VERSION 0x0000
8 #define REG_INPUT_SEL 0x0001
9 #define REG_SVC_MODE 0x0002
10 #define REG_HPD_MAN_CTRL 0x0003
11 #define REG_RT_MAN_CTRL 0x0004
12 #define REG_STANDBY_SOFT_RST 0x000A
13 #define REG_HDMI_SOFT_RST 0x000B
14 #define REG_HDMI_INFO_RST 0x000C
15 #define REG_INT_FLG_CLR_TOP 0x000E
[all …]
H A Dhi846.c22 #define HI846_REG_FLL 0x0006
23 #define HI846_FLL_MAX 0xffff
26 #define HI846_REG_LLP 0x0008
29 #define HI846_REG_BINNING_MODE 0x000c
31 #define HI846_REG_IMAGE_ORIENTATION 0x000e
33 #define HI846_REG_UNKNOWN_0022 0x0022
35 #define HI846_REG_Y_ADDR_START_VACT_H 0x0026
36 #define HI846_REG_Y_ADDR_START_VACT_L 0x0027
37 #define HI846_REG_UNKNOWN_0028 0x0028
39 #define HI846_REG_Y_ADDR_END_VACT_H 0x002c
[all …]
/linux/drivers/clk/qcom/
H A Ddispcc-sdm845.c36 .offset = 0x0,
51 { P_BI_TCXO, 0 },
63 { P_BI_TCXO, 0 },
75 { P_BI_TCXO, 0 },
83 { P_BI_TCXO, 0 },
97 { P_BI_TCXO, 0 },
110 .cmd_rcgr = 0x20d0,
111 .mnd_width = 0,
125 .cmd_rcgr = 0x20ec,
126 .mnd_width = 0,
[all …]
/linux/drivers/usb/serial/
H A Dch341.c35 /* first irq byte normally 0x08 */
36 /* second irq byte base 0x7d + below */
37 /* third irq byte base 0x94 + below */
38 /* fourth irq byte normally 0xee */
41 #define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */
45 #define CH341_BIT_CTS 0x01
46 #define CH341_BIT_DSR 0x02
47 #define CH341_BIT_RI 0x04
48 #define CH341_BIT_DCD 0x08
49 #define CH341_BITS_MODEM_STAT 0x0f /* all bits */
[all …]
H A Dcp210x.c54 { USB_DEVICE(0x0404, 0x034C) }, /* NCR Retail IO Box */
55 { USB_DEVICE(0x045B, 0x0053) }, /* Renesas RX610 RX-Stick */
56 { USB_DEVICE(0x0471, 0x066A) }, /* AKTAKOM ACE-1001 cable */
57 { USB_DEVICE(0x0489, 0xE000) }, /* Pirelli Broadband S.p.A, DP-L10 SIP/GSM Mobile */
58 { USB_DEVICE(0x0489, 0xE003) }, /* Pirelli Broadband S.p.A, DP-L10 SIP/GSM Mobile */
59 { USB_DEVICE(0x04BF, 0x1301) }, /* TDK Corporation NC0110013M - Network Controller */
60 { USB_DEVICE(0x04BF, 0x1303) }, /* TDK Corporation MM0110113M - i3 Micro Module */
61 { USB_DEVICE(0x0745, 0x1000) }, /* CipherLab USB CCD Barcode Scanner 1000 */
62 …{ USB_DEVICE(0x0846, 0x1100) }, /* NetGear Managed Switch M4100 series, M5300 series, M7100 series…
63 { USB_DEVICE(0x08e6, 0x5501) }, /* Gemalto Prox-PU/CU contactless smartcard reader */
[all …]
/linux/drivers/usb/class/
H A Dcdc-acm.c93 minor = idr_alloc(&acm_minors, acm, 0, ACM_TTY_MINORS, GFP_KERNEL); in acm_alloc_minor()
120 retval = usb_control_msg(acm->dev, usb_sndctrlpipe(acm->dev, 0), in acm_ctrl_msg()
122 acm->control->altsetting[0].desc.bInterfaceNumber, in acm_ctrl_msg()
126 "%s - rq 0x%02x, val %#x, len %#x, result %d\n", in acm_ctrl_msg()
131 return retval < 0 ? retval : 0; in acm_ctrl_msg()
143 control, NULL, 0); in acm_set_control()
147 acm_ctrl_msg(acm, USB_CDC_REQ_SET_LINE_CODING, 0, line, sizeof *(line))
149 acm_ctrl_msg(acm, USB_CDC_REQ_SEND_BREAK, ms, NULL, 0)
156 for (i = 0; i < ACM_NW; i++) in acm_poison_urbs()
158 for (i = 0; i < acm->rx_buflimit; i++) in acm_poison_urbs()
[all …]
/linux/include/linux/mfd/mt6357/
H A Dregisters.h10 #define MT6357_TOP0_ID 0x0
11 #define MT6357_TOP0_REV0 0x2
12 #define MT6357_TOP0_DSN_DBI 0x4
13 #define MT6357_TOP0_DSN_DXI 0x6
14 #define MT6357_HWCID 0x8
15 #define MT6357_SWCID 0xa
16 #define MT6357_PONSTS 0xc
17 #define MT6357_POFFSTS 0xe
18 #define MT6357_PSTSCTL 0x10
19 #define MT6357_PG_DEB_STS0 0x12
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h26 #define ixCLIPPER_DEBUG_REG00 0x0000
27 #define ixCLIPPER_DEBUG_REG01 0x0001
28 #define ixCLIPPER_DEBUG_REG02 0x0002
29 #define ixCLIPPER_DEBUG_REG03 0x0003
30 #define ixCLIPPER_DEBUG_REG04 0x0004
31 #define ixCLIPPER_DEBUG_REG05 0x0005
32 #define ixCLIPPER_DEBUG_REG06 0x0006
33 #define ixCLIPPER_DEBUG_REG07 0x0007
34 #define ixCLIPPER_DEBUG_REG08 0x0008
35 #define ixCLIPPER_DEBUG_REG09 0x0009
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgv100.c41 const u32 hoff = 0x800 * head; in gv100_sor_hda_device_entry()
43 nvkm_mask(device, 0x616528 + hoff, 0x00000070, head << 4); in gv100_sor_hda_device_entry()
57 const u32 hoff = head * 0x800; in gv100_sor_dp_watermark()
59 nvkm_mask(device, 0x616550 + hoff, 0x0c00003f, 0x08000000 | watermark); in gv100_sor_dp_watermark()
66 const u32 hoff = head * 0x800; in gv100_sor_dp_audio_sym()
68 nvkm_mask(device, 0x616568 + hoff, 0x0000ffff, h); in gv100_sor_dp_audio_sym()
69 nvkm_mask(device, 0x61656c + hoff, 0x00ffffff, v); in gv100_sor_dp_audio_sym()
76 const u32 hoff = 0x800 * head; in gv100_sor_dp_audio()
77 const u32 data = 0x80000000 | (0x00000001 * enable); in gv100_sor_dp_audio()
78 const u32 mask = 0x8000000d; in gv100_sor_dp_audio()
[all …]
/linux/sound/soc/codecs/
H A Drt5645.c47 #define RT5645_DEVICE_ID 0x6308
48 #define RT5650_DEVICE_ID 0x6419
50 #define RT5645_PR_RANGE_BASE (0xff + 1)
51 #define RT5645_PR_SPACING 0x100
53 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
63 .range_max = RT5645_PR_BASE + 0xf8,
65 .selector_mask = 0xff,
66 .selector_shift = 0x0,
68 .window_len = 0x1,
73 {RT5645_PR_BASE + 0x3
[all...]
H A Drt5677.c37 #define RT5677_DEVICE_ID 0x6327
40 #define RT5677_DSP_BOOT_VECTOR 0x1801f090
41 #define RT5677_MODEL_ADDR 0x5FFC9800
43 #define RT5677_PR_RANGE_BASE (0xff + 1)
44 #define RT5677_PR_SPACING 0x100
46 #define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
52 .range_max = RT5677_PR_BASE + 0xfd,
54 .selector_mask = 0xff,
55 .selector_shift = 0x0,
57 .window_len = 0x1,
[all …]
/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da5xx.xml10 <value value="0x02" name="RB5_A8_UNORM"/>
11 <value value="0x03" name="RB5_R8_UNORM"/>
12 <value value="0x04" name="RB5_R8_SNORM"/>
13 <value value="0x05" name="RB5_R8_UINT"/>
14 <value value="0x06" name="RB5_R8_SINT"/>
15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
18 <value value="0x0f" name="RB5_R8G8_UNORM"/>
19 <value value="0x10" name="RB5_R8G8_SNORM"/>
[all …]
H A Da2xx.xml11 <value name="DITHER_PIXEL" value="0"/>
16 <value name="COLORX_4_4_4_4" value="0"/>
34 <value name="FMT_1_REVERSE" value="0"/>
91 <value name="POSITION_1_VECTOR" value="0"/>
102 <value name="CENTROIDS_ONLY" value="0"/>
108 <value name="DXCLIP_OPENGL" value="0"/>
113 <value name="POLY_DISABLED" value="0"/>
118 <value name="EDRAM_NOP" value="0"/>
125 <value name="LITTLE" value="0"/>
130 <value name="NEVER" value="0"/>
[all …]

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