Lines Matching +full:0 +full:x2184
10 <value value="0x02" name="RB5_A8_UNORM"/>
11 <value value="0x03" name="RB5_R8_UNORM"/>
12 <value value="0x04" name="RB5_R8_SNORM"/>
13 <value value="0x05" name="RB5_R8_UINT"/>
14 <value value="0x06" name="RB5_R8_SINT"/>
15 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
16 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
17 <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
18 <value value="0x0f" name="RB5_R8G8_UNORM"/>
19 <value value="0x10" name="RB5_R8G8_SNORM"/>
20 <value value="0x11" name="RB5_R8G8_UINT"/>
21 <value value="0x12" name="RB5_R8G8_SINT"/>
22 <value value="0x15" name="RB5_R16_UNORM"/>
23 <value value="0x16" name="RB5_R16_SNORM"/>
24 <value value="0x17" name="RB5_R16_FLOAT"/>
25 <value value="0x18" name="RB5_R16_UINT"/>
26 <value value="0x19" name="RB5_R16_SINT"/>
27 <value value="0x30" name="RB5_R8G8B8A8_UNORM"/>
28 <value value="0x31" name="RB5_R8G8B8_UNORM"/>
29 <value value="0x32" name="RB5_R8G8B8A8_SNORM"/>
30 <value value="0x33" name="RB5_R8G8B8A8_UINT"/>
31 <value value="0x34" name="RB5_R8G8B8A8_SINT"/>
32 <value value="0x37" name="RB5_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 -->
33 <value value="0x3a" name="RB5_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI -->
34 <value value="0x42" name="RB5_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F -->
35 <value value="0x43" name="RB5_R16G16_UNORM"/>
36 <value value="0x44" name="RB5_R16G16_SNORM"/>
37 <value value="0x45" name="RB5_R16G16_FLOAT"/>
38 <value value="0x46" name="RB5_R16G16_UINT"/>
39 <value value="0x47" name="RB5_R16G16_SINT"/>
40 <value value="0x4a" name="RB5_R32_FLOAT"/>
41 <value value="0x4b" name="RB5_R32_UINT"/>
42 <value value="0x4c" name="RB5_R32_SINT"/>
43 <value value="0x60" name="RB5_R16G16B16A16_UNORM"/>
44 <value value="0x61" name="RB5_R16G16B16A16_SNORM"/>
45 <value value="0x62" name="RB5_R16G16B16A16_FLOAT"/>
46 <value value="0x63" name="RB5_R16G16B16A16_UINT"/>
47 <value value="0x64" name="RB5_R16G16B16A16_SINT"/>
48 <value value="0x67" name="RB5_R32G32_FLOAT"/>
49 <value value="0x68" name="RB5_R32G32_UINT"/>
50 <value value="0x69" name="RB5_R32G32_SINT"/>
51 <value value="0x82" name="RB5_R32G32B32A32_FLOAT"/>
52 <value value="0x83" name="RB5_R32G32B32A32_UINT"/>
53 <value value="0x84" name="RB5_R32G32B32A32_SINT"/>
55 <value value="0xff" name="RB5_NONE"/>
59 <value name="TILE5_LINEAR" value="0"/>
65 <value value="0x03" name="VFMT5_8_UNORM"/>
66 <value value="0x04" name="VFMT5_8_SNORM"/>
67 <value value="0x05" name="VFMT5_8_UINT"/>
68 <value value="0x06" name="VFMT5_8_SINT"/>
70 <value value="0x0f" name="VFMT5_8_8_UNORM"/>
71 <value value="0x10" name="VFMT5_8_8_SNORM"/>
72 <value value="0x11" name="VFMT5_8_8_UINT"/>
73 <value value="0x12" name="VFMT5_8_8_SINT"/>
75 <value value="0x15" name="VFMT5_16_UNORM"/>
76 <value value="0x16" name="VFMT5_16_SNORM"/>
77 <value value="0x17" name="VFMT5_16_FLOAT"/>
78 <value value="0x18" name="VFMT5_16_UINT"/>
79 <value value="0x19" name="VFMT5_16_SINT"/>
81 <value value="0x21" name="VFMT5_8_8_8_UNORM"/>
82 <value value="0x22" name="VFMT5_8_8_8_SNORM"/>
83 <value value="0x23" name="VFMT5_8_8_8_UINT"/>
84 <value value="0x24" name="VFMT5_8_8_8_SINT"/>
86 <value value="0x30" name="VFMT5_8_8_8_8_UNORM"/>
87 <value value="0x32" name="VFMT5_8_8_8_8_SNORM"/>
88 <value value="0x33" name="VFMT5_8_8_8_8_UINT"/>
89 <value value="0x34" name="VFMT5_8_8_8_8_SINT"/>
91 <value value="0x36" name="VFMT5_10_10_10_2_UNORM"/>
92 <value value="0x39" name="VFMT5_10_10_10_2_SNORM"/>
93 <value value="0x3a" name="VFMT5_10_10_10_2_UINT"/>
94 <value value="0x3b" name="VFMT5_10_10_10_2_SINT"/>
96 <value value="0x42" name="VFMT5_11_11_10_FLOAT"/>
98 <value value="0x43" name="VFMT5_16_16_UNORM"/>
99 <value value="0x44" name="VFMT5_16_16_SNORM"/>
100 <value value="0x45" name="VFMT5_16_16_FLOAT"/>
101 <value value="0x46" name="VFMT5_16_16_UINT"/>
102 <value value="0x47" name="VFMT5_16_16_SINT"/>
104 <value value="0x48" name="VFMT5_32_UNORM"/>
105 <value value="0x49" name="VFMT5_32_SNORM"/>
106 <value value="0x4a" name="VFMT5_32_FLOAT"/>
107 <value value="0x4b" name="VFMT5_32_UINT"/>
108 <value value="0x4c" name="VFMT5_32_SINT"/>
109 <value value="0x4d" name="VFMT5_32_FIXED"/>
111 <value value="0x58" name="VFMT5_16_16_16_UNORM"/>
112 <value value="0x59" name="VFMT5_16_16_16_SNORM"/>
113 <value value="0x5a" name="VFMT5_16_16_16_FLOAT"/>
114 <value value="0x5b" name="VFMT5_16_16_16_UINT"/>
115 <value value="0x5c" name="VFMT5_16_16_16_SINT"/>
117 <value value="0x60" name="VFMT5_16_16_16_16_UNORM"/>
118 <value value="0x61" name="VFMT5_16_16_16_16_SNORM"/>
119 <value value="0x62" name="VFMT5_16_16_16_16_FLOAT"/>
120 <value value="0x63" name="VFMT5_16_16_16_16_UINT"/>
121 <value value="0x64" name="VFMT5_16_16_16_16_SINT"/>
123 <value value="0x65" name="VFMT5_32_32_UNORM"/>
124 <value value="0x66" name="VFMT5_32_32_SNORM"/>
125 <value value="0x67" name="VFMT5_32_32_FLOAT"/>
126 <value value="0x68" name="VFMT5_32_32_UINT"/>
127 <value value="0x69" name="VFMT5_32_32_SINT"/>
128 <value value="0x6a" name="VFMT5_32_32_FIXED"/>
130 <value value="0x70" name="VFMT5_32_32_32_UNORM"/>
131 <value value="0x71" name="VFMT5_32_32_32_SNORM"/>
132 <value value="0x72" name="VFMT5_32_32_32_UINT"/>
133 <value value="0x73" name="VFMT5_32_32_32_SINT"/>
134 <value value="0x74" name="VFMT5_32_32_32_FLOAT"/>
135 <value value="0x75" name="VFMT5_32_32_32_FIXED"/>
137 <value value="0x80" name="VFMT5_32_32_32_32_UNORM"/>
138 <value value="0x81" name="VFMT5_32_32_32_32_SNORM"/>
139 <value value="0x82" name="VFMT5_32_32_32_32_FLOAT"/>
140 <value value="0x83" name="VFMT5_32_32_32_32_UINT"/>
141 <value value="0x84" name="VFMT5_32_32_32_32_SINT"/>
142 <value value="0x85" name="VFMT5_32_32_32_32_FIXED"/>
144 <value value="0xff" name="VFMT5_NONE"/>
148 <value value="0x02" name="TFMT5_A8_UNORM"/>
149 <value value="0x03" name="TFMT5_8_UNORM"/>
150 <value value="0x04" name="TFMT5_8_SNORM"/>
151 <value value="0x05" name="TFMT5_8_UINT"/>
152 <value value="0x06" name="TFMT5_8_SINT"/>
153 <value value="0x08" name="TFMT5_4_4_4_4_UNORM"/>
154 <value value="0x0a" name="TFMT5_5_5_5_1_UNORM"/>
155 <value value="0x0e" name="TFMT5_5_6_5_UNORM"/>
156 <value value="0x0f" name="TFMT5_8_8_UNORM"/>
157 <value value="0x10" name="TFMT5_8_8_SNORM"/>
158 <value value="0x11" name="TFMT5_8_8_UINT"/>
159 <value value="0x12" name="TFMT5_8_8_SINT"/>
160 <value value="0x13" name="TFMT5_L8_A8_UNORM"/>
161 <value value="0x15" name="TFMT5_16_UNORM"/>
162 <value value="0x16" name="TFMT5_16_SNORM"/>
163 <value value="0x17" name="TFMT5_16_FLOAT"/>
164 <value value="0x18" name="TFMT5_16_UINT"/>
165 <value value="0x19" name="TFMT5_16_SINT"/>
166 <value value="0x30" name="TFMT5_8_8_8_8_UNORM"/>
167 <value value="0x31" name="TFMT5_8_8_8_UNORM"/>
168 <value value="0x32" name="TFMT5_8_8_8_8_SNORM"/>
169 <value value="0x33" name="TFMT5_8_8_8_8_UINT"/>
170 <value value="0x34" name="TFMT5_8_8_8_8_SINT"/>
171 <value value="0x35" name="TFMT5_9_9_9_E5_FLOAT"/>
172 <value value="0x36" name="TFMT5_10_10_10_2_UNORM"/>
173 <value value="0x3a" name="TFMT5_10_10_10_2_UINT"/>
174 <value value="0x42" name="TFMT5_11_11_10_FLOAT"/>
175 <value value="0x43" name="TFMT5_16_16_UNORM"/>
176 <value value="0x44" name="TFMT5_16_16_SNORM"/>
177 <value value="0x45" name="TFMT5_16_16_FLOAT"/>
178 <value value="0x46" name="TFMT5_16_16_UINT"/>
179 <value value="0x47" name="TFMT5_16_16_SINT"/>
180 <value value="0x4a" name="TFMT5_32_FLOAT"/>
181 <value value="0x4b" name="TFMT5_32_UINT"/>
182 <value value="0x4c" name="TFMT5_32_SINT"/>
183 <value value="0x60" name="TFMT5_16_16_16_16_UNORM"/>
184 <value value="0x61" name="TFMT5_16_16_16_16_SNORM"/>
185 <value value="0x62" name="TFMT5_16_16_16_16_FLOAT"/>
186 <value value="0x63" name="TFMT5_16_16_16_16_UINT"/>
187 <value value="0x64" name="TFMT5_16_16_16_16_SINT"/>
188 <value value="0x67" name="TFMT5_32_32_FLOAT"/>
189 <value value="0x68" name="TFMT5_32_32_UINT"/>
190 <value value="0x69" name="TFMT5_32_32_SINT"/>
191 <value value="0x72" name="TFMT5_32_32_32_UINT"/>
192 <value value="0x73" name="TFMT5_32_32_32_SINT"/>
193 <value value="0x74" name="TFMT5_32_32_32_FLOAT"/>
194 <value value="0x82" name="TFMT5_32_32_32_32_FLOAT"/>
195 <value value="0x83" name="TFMT5_32_32_32_32_UINT"/>
196 <value value="0x84" name="TFMT5_32_32_32_32_SINT"/>
197 <value value="0xa0" name="TFMT5_X8Z24_UNORM"/>
199 <value value="0xab" name="TFMT5_ETC2_RG11_UNORM"/>
200 <value value="0xac" name="TFMT5_ETC2_RG11_SNORM"/>
201 <value value="0xad" name="TFMT5_ETC2_R11_UNORM"/>
202 <value value="0xae" name="TFMT5_ETC2_R11_SNORM"/>
203 <value value="0xaf" name="TFMT5_ETC1"/>
204 <value value="0xb0" name="TFMT5_ETC2_RGB8"/>
205 <value value="0xb1" name="TFMT5_ETC2_RGBA8"/>
206 <value value="0xb2" name="TFMT5_ETC2_RGB8A1"/>
207 <value value="0xb3" name="TFMT5_DXT1"/>
208 <value value="0xb4" name="TFMT5_DXT3"/>
209 <value value="0xb5" name="TFMT5_DXT5"/>
210 <value value="0xb7" name="TFMT5_RGTC1_UNORM"/>
211 <value value="0xb8" name="TFMT5_RGTC1_SNORM"/>
212 <value value="0xbb" name="TFMT5_RGTC2_UNORM"/>
213 <value value="0xbc" name="TFMT5_RGTC2_SNORM"/>
214 <value value="0xbe" name="TFMT5_BPTC_UFLOAT"/>
215 <value value="0xbf" name="TFMT5_BPTC_FLOAT"/>
216 <value value="0xc0" name="TFMT5_BPTC"/>
217 <value value="0xc1" name="TFMT5_ASTC_4x4"/>
218 <value value="0xc2" name="TFMT5_ASTC_5x4"/>
219 <value value="0xc3" name="TFMT5_ASTC_5x5"/>
220 <value value="0xc4" name="TFMT5_ASTC_6x5"/>
221 <value value="0xc5" name="TFMT5_ASTC_6x6"/>
222 <value value="0xc6" name="TFMT5_ASTC_8x5"/>
223 <value value="0xc7" name="TFMT5_ASTC_8x6"/>
224 <value value="0xc8" name="TFMT5_ASTC_8x8"/>
225 <value value="0xc9" name="TFMT5_ASTC_10x5"/>
226 <value value="0xca" name="TFMT5_ASTC_10x6"/>
227 <value value="0xcb" name="TFMT5_ASTC_10x8"/>
228 <value value="0xcc" name="TFMT5_ASTC_10x10"/>
229 <value value="0xcd" name="TFMT5_ASTC_12x10"/>
230 <value value="0xce" name="TFMT5_ASTC_12x12"/>
232 <value value="0xff" name="TFMT5_NONE"/>
236 <value name="DEPTH5_NONE" value="0"/>
243 <value value="0" name="BLIT_MRT0"/>
257 <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
291 <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
308 <value value="0" name="PERF_PC_BUSY_CYCLES"/>
348 <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
382 <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
400 <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
420 <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
442 <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
455 <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
477 <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
511 <value value="0" name="PERF_TP_BUSY_CYCLES"/>
556 <value value="0" name="PERF_SP_BUSY_CYCLES"/>
624 <value value="0" name="PERF_RB_BUSY_CYCLES"/>
657 <value value="0" name="TOTAL_SAMPLES"/>
664 <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
671 <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
700 <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_VBIF"/>
727 <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
817 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
853 <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
862 <reg32 offset="0x0800" name="CP_RB_BASE"/>
863 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
864 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
865 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
866 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
867 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
868 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
869 <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
870 <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
871 <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
872 <reg32 offset="0x080c" name="CP_DRAW_STATE_DATA"/>
873 <reg32 offset="0x080d" name="CP_ME_NRT_ADDR_LO"/>
874 <reg32 offset="0x080e" name="CP_ME_NRT_ADDR_HI"/>
875 <reg32 offset="0x0810" name="CP_ME_NRT_DATA"/>
876 <reg32 offset="0x0817" name="CP_CRASH_SCRIPT_BASE_LO"/>
877 <reg32 offset="0x0818" name="CP_CRASH_SCRIPT_BASE_HI"/>
878 <reg32 offset="0x0819" name="CP_CRASH_DUMP_CNTL"/>
879 <reg32 offset="0x081a" name="CP_ME_STAT_ADDR"/>
880 <reg32 offset="0x081f" name="CP_ROQ_THRESHOLDS_1"/>
881 <reg32 offset="0x0820" name="CP_ROQ_THRESHOLDS_2"/>
882 <reg32 offset="0x0821" name="CP_ROQ_DBG_ADDR"/>
883 <reg32 offset="0x0822" name="CP_ROQ_DBG_DATA"/>
884 <reg32 offset="0x0823" name="CP_MEQ_DBG_ADDR"/>
885 <reg32 offset="0x0824" name="CP_MEQ_DBG_DATA"/>
886 <reg32 offset="0x0825" name="CP_MEQ_THRESHOLDS"/>
887 <reg32 offset="0x0826" name="CP_MERCIU_SIZE"/>
888 <reg32 offset="0x0827" name="CP_MERCIU_DBG_ADDR"/>
889 <reg32 offset="0x0828" name="CP_MERCIU_DBG_DATA_1"/>
890 <reg32 offset="0x0829" name="CP_MERCIU_DBG_DATA_2"/>
891 <reg32 offset="0x082a" name="CP_PFP_UCODE_DBG_ADDR"/>
892 <reg32 offset="0x082b" name="CP_PFP_UCODE_DBG_DATA"/>
893 <reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/>
894 <reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/>
895 <reg32 offset="0x0831" name="CP_CNTL"/>
896 <reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/>
897 <reg32 offset="0x0833" name="CP_CHICKEN_DBG"/>
898 <reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/>
899 <reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/>
900 <reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/>
901 <reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/>
902 <reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/>
903 <reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/>
904 <reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/>
905 <reg32 offset="0x083e" name="CP_CONTEXT_SWITCH_SAVE_ADDR_LO"/>
906 <reg32 offset="0x083f" name="CP_CONTEXT_SWITCH_SAVE_ADDR_HI"/>
907 <reg32 offset="0x0840" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
908 <reg32 offset="0x0841" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
909 <reg32 offset="0x0860" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
910 <reg32 offset="0x0b14" name="CP_ME_STAT_DATA"/>
911 <reg32 offset="0x0b15" name="CP_WFI_PEND_CTR"/>
912 <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"/>
913 <reg32 offset="0x0b1a" name="CP_HW_FAULT"/>
914 <reg32 offset="0x0b1c" name="CP_PROTECT_STATUS"/>
915 <reg32 offset="0x0b1f" name="CP_IB1_BASE"/>
916 <reg32 offset="0x0b20" name="CP_IB1_BASE_HI"/>
917 <reg32 offset="0x0b21" name="CP_IB1_BUFSZ"/>
918 <reg32 offset="0x0b22" name="CP_IB2_BASE"/>
919 <reg32 offset="0x0b23" name="CP_IB2_BASE_HI"/>
920 <reg32 offset="0x0b24" name="CP_IB2_BUFSZ"/>
921 <array offset="0x0b78" name="CP_SCRATCH" stride="1" length="8">
922 <reg32 offset="0x0" name="REG" type="uint"/>
924 <array offset="0x0880" name="CP_PROTECT" stride="1" length="32">
925 <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
927 <reg32 offset="0x08a0" name="CP_PROTECT_CNTL"/>
928 <reg32 offset="0x0b1b" name="CP_AHB_FAULT"/>
929 <reg32 offset="0x0bb0" name="CP_PERFCTR_CP_SEL_0" type="a5xx_cp_perfcounter_select"/>
930 <reg32 offset="0x0bb1" name="CP_PERFCTR_CP_SEL_1" type="a5xx_cp_perfcounter_select"/>
931 <reg32 offset="0x0bb2" name="CP_PERFCTR_CP_SEL_2" type="a5xx_cp_perfcounter_select"/>
932 <reg32 offset="0x0bb3" name="CP_PERFCTR_CP_SEL_3" type="a5xx_cp_perfcounter_select"/>
933 <reg32 offset="0x0bb4" name="CP_PERFCTR_CP_SEL_4" type="a5xx_cp_perfcounter_select"/>
934 <reg32 offset="0x0bb5" name="CP_PERFCTR_CP_SEL_5" type="a5xx_cp_perfcounter_select"/>
935 <reg32 offset="0x0bb6" name="CP_PERFCTR_CP_SEL_6" type="a5xx_cp_perfcounter_select"/>
936 <reg32 offset="0x0bb7" name="CP_PERFCTR_CP_SEL_7" type="a5xx_cp_perfcounter_select"/>
937 <reg32 offset="0x0bc1" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
938 <reg32 offset="0x0bba" name="CP_POWERCTR_CP_SEL_0"/>
939 <reg32 offset="0x0bbb" name="CP_POWERCTR_CP_SEL_1"/>
940 <reg32 offset="0x0bbc" name="CP_POWERCTR_CP_SEL_2"/>
941 <reg32 offset="0x0bbd" name="CP_POWERCTR_CP_SEL_3"/>
944 <reg32 offset="0x0004" name="RBBM_CFG_DBGBUS_SEL_A"/>
945 <reg32 offset="0x0005" name="RBBM_CFG_DBGBUS_SEL_B"/>
946 <reg32 offset="0x0006" name="RBBM_CFG_DBGBUS_SEL_C"/>
947 <reg32 offset="0x0007" name="RBBM_CFG_DBGBUS_SEL_D"/>
949 #define A5XX_RBBM_CFG_DBGBUS_SEL_PING_INDEX_SHIFT 0x0
950 #define A5XX_RBBM_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT 0x8
951 #define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_INDEX_SHIFT 0x10
952 #define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_BLK_SEL_SHIFT 0x18
954 <reg32 offset="0x0008" name="RBBM_CFG_DBGBUS_CNTLT"/>
955 <reg32 offset="0x0009" name="RBBM_CFG_DBGBUS_CNTLM"/>
956 <reg32 offset="0x0018" name="RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT"/>
957 <reg32 offset="0x000a" name="RBBM_CFG_DBGBUS_OPL"/>
958 <reg32 offset="0x000b" name="RBBM_CFG_DBGBUS_OPE"/>
959 <reg32 offset="0x000c" name="RBBM_CFG_DBGBUS_IVTL_0"/>
960 <reg32 offset="0x000d" name="RBBM_CFG_DBGBUS_IVTL_1"/>
961 <reg32 offset="0x000e" name="RBBM_CFG_DBGBUS_IVTL_2"/>
962 <reg32 offset="0x000f" name="RBBM_CFG_DBGBUS_IVTL_3"/>
963 <reg32 offset="0x0010" name="RBBM_CFG_DBGBUS_MASKL_0"/>
964 <reg32 offset="0x0011" name="RBBM_CFG_DBGBUS_MASKL_1"/>
965 <reg32 offset="0x0012" name="RBBM_CFG_DBGBUS_MASKL_2"/>
966 <reg32 offset="0x0013" name="RBBM_CFG_DBGBUS_MASKL_3"/>
967 <reg32 offset="0x0014" name="RBBM_CFG_DBGBUS_BYTEL_0"/>
968 <reg32 offset="0x0015" name="RBBM_CFG_DBGBUS_BYTEL_1"/>
969 <reg32 offset="0x0016" name="RBBM_CFG_DBGBUS_IVTE_0"/>
970 <reg32 offset="0x0017" name="RBBM_CFG_DBGBUS_IVTE_1"/>
971 <reg32 offset="0x0018" name="RBBM_CFG_DBGBUS_IVTE_2"/>
972 <reg32 offset="0x0019" name="RBBM_CFG_DBGBUS_IVTE_3"/>
973 <reg32 offset="0x001a" name="RBBM_CFG_DBGBUS_MASKE_0"/>
974 <reg32 offset="0x001b" name="RBBM_CFG_DBGBUS_MASKE_1"/>
975 <reg32 offset="0x001c" name="RBBM_CFG_DBGBUS_MASKE_2"/>
976 <reg32 offset="0x001d" name="RBBM_CFG_DBGBUS_MASKE_3"/>
977 <reg32 offset="0x001e" name="RBBM_CFG_DBGBUS_NIBBLEE"/>
978 <reg32 offset="0x001f" name="RBBM_CFG_DBGBUS_PTRC0"/>
979 <reg32 offset="0x0020" name="RBBM_CFG_DBGBUS_PTRC1"/>
980 <reg32 offset="0x0021" name="RBBM_CFG_DBGBUS_LOADREG"/>
981 <reg32 offset="0x0022" name="RBBM_CFG_DBGBUS_IDX"/>
982 <reg32 offset="0x0023" name="RBBM_CFG_DBGBUS_CLRC"/>
983 <reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/>
984 <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
985 <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/>
986 <reg32 offset="0x0038" name="RBBM_INT_0_MASK">
987 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
1017 <reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/>
1018 <reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/>
1019 <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/>
1020 <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1021 <reg32 offset="0x0046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1022 <reg32 offset="0x0048" name="RBBM_DBG_LO_HI_GPIO"/>
1023 <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CNTL"/>
1024 <reg32 offset="0x004a" name="RBBM_CLOCK_CNTL_TP0"/>
1025 <reg32 offset="0x004b" name="RBBM_CLOCK_CNTL_TP1"/>
1026 <reg32 offset="0x004c" name="RBBM_CLOCK_CNTL_TP2"/>
1027 <reg32 offset="0x004d" name="RBBM_CLOCK_CNTL_TP3"/>
1028 <reg32 offset="0x004e" name="RBBM_CLOCK_CNTL2_TP0"/>
1029 <reg32 offset="0x004f" name="RBBM_CLOCK_CNTL2_TP1"/>
1030 <reg32 offset="0x0050" name="RBBM_CLOCK_CNTL2_TP2"/>
1031 <reg32 offset="0x0051" name="RBBM_CLOCK_CNTL2_TP3"/>
1032 <reg32 offset="0x0052" name="RBBM_CLOCK_CNTL3_TP0"/>
1033 <reg32 offset="0x0053" name="RBBM_CLOCK_CNTL3_TP1"/>
1034 <reg32 offset="0x0054" name="RBBM_CLOCK_CNTL3_TP2"/>
1035 <reg32 offset="0x0055" name="RBBM_CLOCK_CNTL3_TP3"/>
1036 <reg32 offset="0x0059" name="RBBM_READ_AHB_THROUGH_DBG"/>
1037 <reg32 offset="0x005a" name="RBBM_CLOCK_CNTL_UCHE"/>
1038 <reg32 offset="0x005b" name="RBBM_CLOCK_CNTL2_UCHE"/>
1039 <reg32 offset="0x005c" name="RBBM_CLOCK_CNTL3_UCHE"/>
1040 <reg32 offset="0x005d" name="RBBM_CLOCK_CNTL4_UCHE"/>
1041 <reg32 offset="0x005e" name="RBBM_CLOCK_HYST_UCHE"/>
1042 <reg32 offset="0x005f" name="RBBM_CLOCK_DELAY_UCHE"/>
1043 <reg32 offset="0x0060" name="RBBM_CLOCK_MODE_GPC"/>
1044 <reg32 offset="0x0061" name="RBBM_CLOCK_DELAY_GPC"/>
1045 <reg32 offset="0x0062" name="RBBM_CLOCK_HYST_GPC"/>
1046 <reg32 offset="0x0063" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1047 <reg32 offset="0x0064" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1048 <reg32 offset="0x0065" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1049 <reg32 offset="0x0066" name="RBBM_CLOCK_DELAY_HLSQ"/>
1050 <reg32 offset="0x0067" name="RBBM_CLOCK_CNTL"/>
1051 <reg32 offset="0x0068" name="RBBM_CLOCK_CNTL_SP0"/>
1052 <reg32 offset="0x0069" name="RBBM_CLOCK_CNTL_SP1"/>
1053 <reg32 offset="0x006a" name="RBBM_CLOCK_CNTL_SP2"/>
1054 <reg32 offset="0x006b" name="RBBM_CLOCK_CNTL_SP3"/>
1055 <reg32 offset="0x006c" name="RBBM_CLOCK_CNTL2_SP0"/>
1056 <reg32 offset="0x006d" name="RBBM_CLOCK_CNTL2_SP1"/>
1057 <reg32 offset="0x006e" name="RBBM_CLOCK_CNTL2_SP2"/>
1058 <reg32 offset="0x006f" name="RBBM_CLOCK_CNTL2_SP3"/>
1059 <reg32 offset="0x0070" name="RBBM_CLOCK_HYST_SP0"/>
1060 <reg32 offset="0x0071" name="RBBM_CLOCK_HYST_SP1"/>
1061 <reg32 offset="0x0072" name="RBBM_CLOCK_HYST_SP2"/>
1062 <reg32 offset="0x0073" name="RBBM_CLOCK_HYST_SP3"/>
1063 <reg32 offset="0x0074" name="RBBM_CLOCK_DELAY_SP0"/>
1064 <reg32 offset="0x0075" name="RBBM_CLOCK_DELAY_SP1"/>
1065 <reg32 offset="0x0076" name="RBBM_CLOCK_DELAY_SP2"/>
1066 <reg32 offset="0x0077" name="RBBM_CLOCK_DELAY_SP3"/>
1067 <reg32 offset="0x0078" name="RBBM_CLOCK_CNTL_RB0"/>
1068 <reg32 offset="0x0079" name="RBBM_CLOCK_CNTL_RB1"/>
1069 <reg32 offset="0x007a" name="RBBM_CLOCK_CNTL_RB2"/>
1070 <reg32 offset="0x007b" name="RBBM_CLOCK_CNTL_RB3"/>
1071 <reg32 offset="0x007c" name="RBBM_CLOCK_CNTL2_RB0"/>
1072 <reg32 offset="0x007d" name="RBBM_CLOCK_CNTL2_RB1"/>
1073 <reg32 offset="0x007e" name="RBBM_CLOCK_CNTL2_RB2"/>
1074 <reg32 offset="0x007f" name="RBBM_CLOCK_CNTL2_RB3"/>
1075 <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_RAC"/>
1076 <reg32 offset="0x0081" name="RBBM_CLOCK_DELAY_RAC"/>
1077 <reg32 offset="0x0082" name="RBBM_CLOCK_CNTL_CCU0"/>
1078 <reg32 offset="0x0083" name="RBBM_CLOCK_CNTL_CCU1"/>
1079 <reg32 offset="0x0084" name="RBBM_CLOCK_CNTL_CCU2"/>
1080 <reg32 offset="0x0085" name="RBBM_CLOCK_CNTL_CCU3"/>
1081 <reg32 offset="0x0086" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1082 <reg32 offset="0x0087" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1083 <reg32 offset="0x0088" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1084 <reg32 offset="0x0089" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1085 <reg32 offset="0x008a" name="RBBM_CLOCK_CNTL_RAC"/>
1086 <reg32 offset="0x008b" name="RBBM_CLOCK_CNTL2_RAC"/>
1087 <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_RB_CCU_L1_0"/>
1088 <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_RB_CCU_L1_1"/>
1089 <reg32 offset="0x008e" name="RBBM_CLOCK_DELAY_RB_CCU_L1_2"/>
1090 <reg32 offset="0x008f" name="RBBM_CLOCK_DELAY_RB_CCU_L1_3"/>
1091 <reg32 offset="0x0090" name="RBBM_CLOCK_HYST_VFD"/>
1092 <reg32 offset="0x0091" name="RBBM_CLOCK_MODE_VFD"/>
1093 <reg32 offset="0x0092" name="RBBM_CLOCK_DELAY_VFD"/>
1094 <reg32 offset="0x0093" name="RBBM_AHB_CNTL0"/>
1095 <reg32 offset="0x0094" name="RBBM_AHB_CNTL1"/>
1096 <reg32 offset="0x0095" name="RBBM_AHB_CNTL2"/>
1097 <reg32 offset="0x0096" name="RBBM_AHB_CMD"/>
1098 <reg32 offset="0x009c" name="RBBM_INTERFACE_HANG_MASK_CNTL11"/>
1099 <reg32 offset="0x009d" name="RBBM_INTERFACE_HANG_MASK_CNTL12"/>
1100 <reg32 offset="0x009e" name="RBBM_INTERFACE_HANG_MASK_CNTL13"/>
1101 <reg32 offset="0x009f" name="RBBM_INTERFACE_HANG_MASK_CNTL14"/>
1102 <reg32 offset="0x00a0" name="RBBM_INTERFACE_HANG_MASK_CNTL15"/>
1103 <reg32 offset="0x00a1" name="RBBM_INTERFACE_HANG_MASK_CNTL16"/>
1104 <reg32 offset="0x00a2" name="RBBM_INTERFACE_HANG_MASK_CNTL17"/>
1105 <reg32 offset="0x00a3" name="RBBM_INTERFACE_HANG_MASK_CNTL18"/>
1106 <reg32 offset="0x00a4" name="RBBM_CLOCK_DELAY_TP0"/>
1107 <reg32 offset="0x00a5" name="RBBM_CLOCK_DELAY_TP1"/>
1108 <reg32 offset="0x00a6" name="RBBM_CLOCK_DELAY_TP2"/>
1109 <reg32 offset="0x00a7" name="RBBM_CLOCK_DELAY_TP3"/>
1110 <reg32 offset="0x00a8" name="RBBM_CLOCK_DELAY2_TP0"/>
1111 <reg32 offset="0x00a9" name="RBBM_CLOCK_DELAY2_TP1"/>
1112 <reg32 offset="0x00aa" name="RBBM_CLOCK_DELAY2_TP2"/>
1113 <reg32 offset="0x00ab" name="RBBM_CLOCK_DELAY2_TP3"/>
1114 <reg32 offset="0x00ac" name="RBBM_CLOCK_DELAY3_TP0"/>
1115 <reg32 offset="0x00ad" name="RBBM_CLOCK_DELAY3_TP1"/>
1116 <reg32 offset="0x00ae" name="RBBM_CLOCK_DELAY3_TP2"/>
1117 <reg32 offset="0x00af" name="RBBM_CLOCK_DELAY3_TP3"/>
1118 <reg32 offset="0x00b0" name="RBBM_CLOCK_HYST_TP0"/>
1119 <reg32 offset="0x00b1" name="RBBM_CLOCK_HYST_TP1"/>
1120 <reg32 offset="0x00b2" name="RBBM_CLOCK_HYST_TP2"/>
1121 <reg32 offset="0x00b3" name="RBBM_CLOCK_HYST_TP3"/>
1122 <reg32 offset="0x00b4" name="RBBM_CLOCK_HYST2_TP0"/>
1123 <reg32 offset="0x00b5" name="RBBM_CLOCK_HYST2_TP1"/>
1124 <reg32 offset="0x00b6" name="RBBM_CLOCK_HYST2_TP2"/>
1125 <reg32 offset="0x00b7" name="RBBM_CLOCK_HYST2_TP3"/>
1126 <reg32 offset="0x00b8" name="RBBM_CLOCK_HYST3_TP0"/>
1127 <reg32 offset="0x00b9" name="RBBM_CLOCK_HYST3_TP1"/>
1128 <reg32 offset="0x00ba" name="RBBM_CLOCK_HYST3_TP2"/>
1129 <reg32 offset="0x00bb" name="RBBM_CLOCK_HYST3_TP3"/>
1130 <reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL_GPMU"/>
1131 <reg32 offset="0x00c9" name="RBBM_CLOCK_DELAY_GPMU"/>
1132 <reg32 offset="0x00ca" name="RBBM_CLOCK_HYST_GPMU"/>
1133 <reg32 offset="0x03a0" name="RBBM_PERFCTR_CP_0_LO"/>
1134 <reg32 offset="0x03a1" name="RBBM_PERFCTR_CP_0_HI"/>
1135 <reg32 offset="0x03a2" name="RBBM_PERFCTR_CP_1_LO"/>
1136 <reg32 offset="0x03a3" name="RBBM_PERFCTR_CP_1_HI"/>
1137 <reg32 offset="0x03a4" name="RBBM_PERFCTR_CP_2_LO"/>
1138 <reg32 offset="0x03a5" name="RBBM_PERFCTR_CP_2_HI"/>
1139 <reg32 offset="0x03a6" name="RBBM_PERFCTR_CP_3_LO"/>
1140 <reg32 offset="0x03a7" name="RBBM_PERFCTR_CP_3_HI"/>
1141 <reg32 offset="0x03a8" name="RBBM_PERFCTR_CP_4_LO"/>
1142 <reg32 offset="0x03a9" name="RBBM_PERFCTR_CP_4_HI"/>
1143 <reg32 offset="0x03aa" name="RBBM_PERFCTR_CP_5_LO"/>
1144 <reg32 offset="0x03ab" name="RBBM_PERFCTR_CP_5_HI"/>
1145 <reg32 offset="0x03ac" name="RBBM_PERFCTR_CP_6_LO"/>
1146 <reg32 offset="0x03ad" name="RBBM_PERFCTR_CP_6_HI"/>
1147 <reg32 offset="0x03ae" name="RBBM_PERFCTR_CP_7_LO"/>
1148 <reg32 offset="0x03af" name="RBBM_PERFCTR_CP_7_HI"/>
1149 <reg32 offset="0x03b0" name="RBBM_PERFCTR_RBBM_0_LO"/>
1150 <reg32 offset="0x03b1" name="RBBM_PERFCTR_RBBM_0_HI"/>
1151 <reg32 offset="0x03b2" name="RBBM_PERFCTR_RBBM_1_LO"/>
1152 <reg32 offset="0x03b3" name="RBBM_PERFCTR_RBBM_1_HI"/>
1153 <reg32 offset="0x03b4" name="RBBM_PERFCTR_RBBM_2_LO"/>
1154 <reg32 offset="0x03b5" name="RBBM_PERFCTR_RBBM_2_HI"/>
1155 <reg32 offset="0x03b6" name="RBBM_PERFCTR_RBBM_3_LO"/>
1156 <reg32 offset="0x03b7" name="RBBM_PERFCTR_RBBM_3_HI"/>
1157 <reg32 offset="0x03b8" name="RBBM_PERFCTR_PC_0_LO"/>
1158 <reg32 offset="0x03b9" name="RBBM_PERFCTR_PC_0_HI"/>
1159 <reg32 offset="0x03ba" name="RBBM_PERFCTR_PC_1_LO"/>
1160 <reg32 offset="0x03bb" name="RBBM_PERFCTR_PC_1_HI"/>
1161 <reg32 offset="0x03bc" name="RBBM_PERFCTR_PC_2_LO"/>
1162 <reg32 offset="0x03bd" name="RBBM_PERFCTR_PC_2_HI"/>
1163 <reg32 offset="0x03be" name="RBBM_PERFCTR_PC_3_LO"/>
1164 <reg32 offset="0x03bf" name="RBBM_PERFCTR_PC_3_HI"/>
1165 <reg32 offset="0x03c0" name="RBBM_PERFCTR_PC_4_LO"/>
1166 <reg32 offset="0x03c1" name="RBBM_PERFCTR_PC_4_HI"/>
1167 <reg32 offset="0x03c2" name="RBBM_PERFCTR_PC_5_LO"/>
1168 <reg32 offset="0x03c3" name="RBBM_PERFCTR_PC_5_HI"/>
1169 <reg32 offset="0x03c4" name="RBBM_PERFCTR_PC_6_LO"/>
1170 <reg32 offset="0x03c5" name="RBBM_PERFCTR_PC_6_HI"/>
1171 <reg32 offset="0x03c6" name="RBBM_PERFCTR_PC_7_LO"/>
1172 <reg32 offset="0x03c7" name="RBBM_PERFCTR_PC_7_HI"/>
1173 <reg32 offset="0x03c8" name="RBBM_PERFCTR_VFD_0_LO"/>
1174 <reg32 offset="0x03c9" name="RBBM_PERFCTR_VFD_0_HI"/>
1175 <reg32 offset="0x03ca" name="RBBM_PERFCTR_VFD_1_LO"/>
1176 <reg32 offset="0x03cb" name="RBBM_PERFCTR_VFD_1_HI"/>
1177 <reg32 offset="0x03cc" name="RBBM_PERFCTR_VFD_2_LO"/>
1178 <reg32 offset="0x03cd" name="RBBM_PERFCTR_VFD_2_HI"/>
1179 <reg32 offset="0x03ce" name="RBBM_PERFCTR_VFD_3_LO"/>
1180 <reg32 offset="0x03cf" name="RBBM_PERFCTR_VFD_3_HI"/>
1181 <reg32 offset="0x03d0" name="RBBM_PERFCTR_VFD_4_LO"/>
1182 <reg32 offset="0x03d1" name="RBBM_PERFCTR_VFD_4_HI"/>
1183 <reg32 offset="0x03d2" name="RBBM_PERFCTR_VFD_5_LO"/>
1184 <reg32 offset="0x03d3" name="RBBM_PERFCTR_VFD_5_HI"/>
1185 <reg32 offset="0x03d4" name="RBBM_PERFCTR_VFD_6_LO"/>
1186 <reg32 offset="0x03d5" name="RBBM_PERFCTR_VFD_6_HI"/>
1187 <reg32 offset="0x03d6" name="RBBM_PERFCTR_VFD_7_LO"/>
1188 <reg32 offset="0x03d7" name="RBBM_PERFCTR_VFD_7_HI"/>
1189 <reg32 offset="0x03d8" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1190 <reg32 offset="0x03d9" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1191 <reg32 offset="0x03da" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1192 <reg32 offset="0x03db" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1193 <reg32 offset="0x03dc" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1194 <reg32 offset="0x03dd" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1195 <reg32 offset="0x03de" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1196 <reg32 offset="0x03df" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1197 <reg32 offset="0x03e0" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1198 <reg32 offset="0x03e1" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1199 <reg32 offset="0x03e2" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1200 <reg32 offset="0x03e3" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1201 <reg32 offset="0x03e4" name="RBBM_PERFCTR_HLSQ_6_LO"/>
1202 <reg32 offset="0x03e5" name="RBBM_PERFCTR_HLSQ_6_HI"/>
1203 <reg32 offset="0x03e6" name="RBBM_PERFCTR_HLSQ_7_LO"/>
1204 <reg32 offset="0x03e7" name="RBBM_PERFCTR_HLSQ_7_HI"/>
1205 <reg32 offset="0x03e8" name="RBBM_PERFCTR_VPC_0_LO"/>
1206 <reg32 offset="0x03e9" name="RBBM_PERFCTR_VPC_0_HI"/>
1207 <reg32 offset="0x03ea" name="RBBM_PERFCTR_VPC_1_LO"/>
1208 <reg32 offset="0x03eb" name="RBBM_PERFCTR_VPC_1_HI"/>
1209 <reg32 offset="0x03ec" name="RBBM_PERFCTR_VPC_2_LO"/>
1210 <reg32 offset="0x03ed" name="RBBM_PERFCTR_VPC_2_HI"/>
1211 <reg32 offset="0x03ee" name="RBBM_PERFCTR_VPC_3_LO"/>
1212 <reg32 offset="0x03ef" name="RBBM_PERFCTR_VPC_3_HI"/>
1213 <reg32 offset="0x03f0" name="RBBM_PERFCTR_CCU_0_LO"/>
1214 <reg32 offset="0x03f1" name="RBBM_PERFCTR_CCU_0_HI"/>
1215 <reg32 offset="0x03f2" name="RBBM_PERFCTR_CCU_1_LO"/>
1216 <reg32 offset="0x03f3" name="RBBM_PERFCTR_CCU_1_HI"/>
1217 <reg32 offset="0x03f4" name="RBBM_PERFCTR_CCU_2_LO"/>
1218 <reg32 offset="0x03f5" name="RBBM_PERFCTR_CCU_2_HI"/>
1219 <reg32 offset="0x03f6" name="RBBM_PERFCTR_CCU_3_LO"/>
1220 <reg32 offset="0x03f7" name="RBBM_PERFCTR_CCU_3_HI"/>
1221 <reg32 offset="0x03f8" name="RBBM_PERFCTR_TSE_0_LO"/>
1222 <reg32 offset="0x03f9" name="RBBM_PERFCTR_TSE_0_HI"/>
1223 <reg32 offset="0x03fa" name="RBBM_PERFCTR_TSE_1_LO"/>
1224 <reg32 offset="0x03fb" name="RBBM_PERFCTR_TSE_1_HI"/>
1225 <reg32 offset="0x03fc" name="RBBM_PERFCTR_TSE_2_LO"/>
1226 <reg32 offset="0x03fd" name="RBBM_PERFCTR_TSE_2_HI"/>
1227 <reg32 offset="0x03fe" name="RBBM_PERFCTR_TSE_3_LO"/>
1228 <reg32 offset="0x03ff" name="RBBM_PERFCTR_TSE_3_HI"/>
1229 <reg32 offset="0x0400" name="RBBM_PERFCTR_RAS_0_LO"/>
1230 <reg32 offset="0x0401" name="RBBM_PERFCTR_RAS_0_HI"/>
1231 <reg32 offset="0x0402" name="RBBM_PERFCTR_RAS_1_LO"/>
1232 <reg32 offset="0x0403" name="RBBM_PERFCTR_RAS_1_HI"/>
1233 <reg32 offset="0x0404" name="RBBM_PERFCTR_RAS_2_LO"/>
1234 <reg32 offset="0x0405" name="RBBM_PERFCTR_RAS_2_HI"/>
1235 <reg32 offset="0x0406" name="RBBM_PERFCTR_RAS_3_LO"/>
1236 <reg32 offset="0x0407" name="RBBM_PERFCTR_RAS_3_HI"/>
1237 <reg32 offset="0x0408" name="RBBM_PERFCTR_UCHE_0_LO"/>
1238 <reg32 offset="0x0409" name="RBBM_PERFCTR_UCHE_0_HI"/>
1239 <reg32 offset="0x040a" name="RBBM_PERFCTR_UCHE_1_LO"/>
1240 <reg32 offset="0x040b" name="RBBM_PERFCTR_UCHE_1_HI"/>
1241 <reg32 offset="0x040c" name="RBBM_PERFCTR_UCHE_2_LO"/>
1242 <reg32 offset="0x040d" name="RBBM_PERFCTR_UCHE_2_HI"/>
1243 <reg32 offset="0x040e" name="RBBM_PERFCTR_UCHE_3_LO"/>
1244 <reg32 offset="0x040f" name="RBBM_PERFCTR_UCHE_3_HI"/>
1245 <reg32 offset="0x0410" name="RBBM_PERFCTR_UCHE_4_LO"/>
1246 <reg32 offset="0x0411" name="RBBM_PERFCTR_UCHE_4_HI"/>
1247 <reg32 offset="0x0412" name="RBBM_PERFCTR_UCHE_5_LO"/>
1248 <reg32 offset="0x0413" name="RBBM_PERFCTR_UCHE_5_HI"/>
1249 <reg32 offset="0x0414" name="RBBM_PERFCTR_UCHE_6_LO"/>
1250 <reg32 offset="0x0415" name="RBBM_PERFCTR_UCHE_6_HI"/>
1251 <reg32 offset="0x0416" name="RBBM_PERFCTR_UCHE_7_LO"/>
1252 <reg32 offset="0x0417" name="RBBM_PERFCTR_UCHE_7_HI"/>
1253 <reg32 offset="0x0418" name="RBBM_PERFCTR_TP_0_LO"/>
1254 <reg32 offset="0x0419" name="RBBM_PERFCTR_TP_0_HI"/>
1255 <reg32 offset="0x041a" name="RBBM_PERFCTR_TP_1_LO"/>
1256 <reg32 offset="0x041b" name="RBBM_PERFCTR_TP_1_HI"/>
1257 <reg32 offset="0x041c" name="RBBM_PERFCTR_TP_2_LO"/>
1258 <reg32 offset="0x041d" name="RBBM_PERFCTR_TP_2_HI"/>
1259 <reg32 offset="0x041e" name="RBBM_PERFCTR_TP_3_LO"/>
1260 <reg32 offset="0x041f" name="RBBM_PERFCTR_TP_3_HI"/>
1261 <reg32 offset="0x0420" name="RBBM_PERFCTR_TP_4_LO"/>
1262 <reg32 offset="0x0421" name="RBBM_PERFCTR_TP_4_HI"/>
1263 <reg32 offset="0x0422" name="RBBM_PERFCTR_TP_5_LO"/>
1264 <reg32 offset="0x0423" name="RBBM_PERFCTR_TP_5_HI"/>
1265 <reg32 offset="0x0424" name="RBBM_PERFCTR_TP_6_LO"/>
1266 <reg32 offset="0x0425" name="RBBM_PERFCTR_TP_6_HI"/>
1267 <reg32 offset="0x0426" name="RBBM_PERFCTR_TP_7_LO"/>
1268 <reg32 offset="0x0427" name="RBBM_PERFCTR_TP_7_HI"/>
1269 <reg32 offset="0x0428" name="RBBM_PERFCTR_SP_0_LO"/>
1270 <reg32 offset="0x0429" name="RBBM_PERFCTR_SP_0_HI"/>
1271 <reg32 offset="0x042a" name="RBBM_PERFCTR_SP_1_LO"/>
1272 <reg32 offset="0x042b" name="RBBM_PERFCTR_SP_1_HI"/>
1273 <reg32 offset="0x042c" name="RBBM_PERFCTR_SP_2_LO"/>
1274 <reg32 offset="0x042d" name="RBBM_PERFCTR_SP_2_HI"/>
1275 <reg32 offset="0x042e" name="RBBM_PERFCTR_SP_3_LO"/>
1276 <reg32 offset="0x042f" name="RBBM_PERFCTR_SP_3_HI"/>
1277 <reg32 offset="0x0430" name="RBBM_PERFCTR_SP_4_LO"/>
1278 <reg32 offset="0x0431" name="RBBM_PERFCTR_SP_4_HI"/>
1279 <reg32 offset="0x0432" name="RBBM_PERFCTR_SP_5_LO"/>
1280 <reg32 offset="0x0433" name="RBBM_PERFCTR_SP_5_HI"/>
1281 <reg32 offset="0x0434" name="RBBM_PERFCTR_SP_6_LO"/>
1282 <reg32 offset="0x0435" name="RBBM_PERFCTR_SP_6_HI"/>
1283 <reg32 offset="0x0436" name="RBBM_PERFCTR_SP_7_LO"/>
1284 <reg32 offset="0x0437" name="RBBM_PERFCTR_SP_7_HI"/>
1285 <reg32 offset="0x0438" name="RBBM_PERFCTR_SP_8_LO"/>
1286 <reg32 offset="0x0439" name="RBBM_PERFCTR_SP_8_HI"/>
1287 <reg32 offset="0x043a" name="RBBM_PERFCTR_SP_9_LO"/>
1288 <reg32 offset="0x043b" name="RBBM_PERFCTR_SP_9_HI"/>
1289 <reg32 offset="0x043c" name="RBBM_PERFCTR_SP_10_LO"/>
1290 <reg32 offset="0x043d" name="RBBM_PERFCTR_SP_10_HI"/>
1291 <reg32 offset="0x043e" name="RBBM_PERFCTR_SP_11_LO"/>
1292 <reg32 offset="0x043f" name="RBBM_PERFCTR_SP_11_HI"/>
1293 <reg32 offset="0x0440" name="RBBM_PERFCTR_RB_0_LO"/>
1294 <reg32 offset="0x0441" name="RBBM_PERFCTR_RB_0_HI"/>
1295 <reg32 offset="0x0442" name="RBBM_PERFCTR_RB_1_LO"/>
1296 <reg32 offset="0x0443" name="RBBM_PERFCTR_RB_1_HI"/>
1297 <reg32 offset="0x0444" name="RBBM_PERFCTR_RB_2_LO"/>
1298 <reg32 offset="0x0445" name="RBBM_PERFCTR_RB_2_HI"/>
1299 <reg32 offset="0x0446" name="RBBM_PERFCTR_RB_3_LO"/>
1300 <reg32 offset="0x0447" name="RBBM_PERFCTR_RB_3_HI"/>
1301 <reg32 offset="0x0448" name="RBBM_PERFCTR_RB_4_LO"/>
1302 <reg32 offset="0x0449" name="RBBM_PERFCTR_RB_4_HI"/>
1303 <reg32 offset="0x044a" name="RBBM_PERFCTR_RB_5_LO"/>
1304 <reg32 offset="0x044b" name="RBBM_PERFCTR_RB_5_HI"/>
1305 <reg32 offset="0x044c" name="RBBM_PERFCTR_RB_6_LO"/>
1306 <reg32 offset="0x044d" name="RBBM_PERFCTR_RB_6_HI"/>
1307 <reg32 offset="0x044e" name="RBBM_PERFCTR_RB_7_LO"/>
1308 <reg32 offset="0x044f" name="RBBM_PERFCTR_RB_7_HI"/>
1309 <reg32 offset="0x0450" name="RBBM_PERFCTR_VSC_0_LO"/>
1310 <reg32 offset="0x0451" name="RBBM_PERFCTR_VSC_0_HI"/>
1311 <reg32 offset="0x0452" name="RBBM_PERFCTR_VSC_1_LO"/>
1312 <reg32 offset="0x0453" name="RBBM_PERFCTR_VSC_1_HI"/>
1313 <reg32 offset="0x0454" name="RBBM_PERFCTR_LRZ_0_LO"/>
1314 <reg32 offset="0x0455" name="RBBM_PERFCTR_LRZ_0_HI"/>
1315 <reg32 offset="0x0456" name="RBBM_PERFCTR_LRZ_1_LO"/>
1316 <reg32 offset="0x0457" name="RBBM_PERFCTR_LRZ_1_HI"/>
1317 <reg32 offset="0x0458" name="RBBM_PERFCTR_LRZ_2_LO"/>
1318 <reg32 offset="0x0459" name="RBBM_PERFCTR_LRZ_2_HI"/>
1319 <reg32 offset="0x045a" name="RBBM_PERFCTR_LRZ_3_LO"/>
1320 <reg32 offset="0x045b" name="RBBM_PERFCTR_LRZ_3_HI"/>
1321 <reg32 offset="0x045c" name="RBBM_PERFCTR_CMP_0_LO"/>
1322 <reg32 offset="0x045d" name="RBBM_PERFCTR_CMP_0_HI"/>
1323 <reg32 offset="0x045e" name="RBBM_PERFCTR_CMP_1_LO"/>
1324 <reg32 offset="0x045f" name="RBBM_PERFCTR_CMP_1_HI"/>
1325 <reg32 offset="0x0460" name="RBBM_PERFCTR_CMP_2_LO"/>
1326 <reg32 offset="0x0461" name="RBBM_PERFCTR_CMP_2_HI"/>
1327 <reg32 offset="0x0462" name="RBBM_PERFCTR_CMP_3_LO"/>
1328 <reg32 offset="0x0463" name="RBBM_PERFCTR_CMP_3_HI"/>
1329 <reg32 offset="0x046b" name="RBBM_PERFCTR_RBBM_SEL_0" type="a5xx_rbbm_perfcounter_select"/>
1330 <reg32 offset="0x046c" name="RBBM_PERFCTR_RBBM_SEL_1" type="a5xx_rbbm_perfcounter_select"/>
1331 <reg32 offset="0x046d" name="RBBM_PERFCTR_RBBM_SEL_2" type="a5xx_rbbm_perfcounter_select"/>
1332 <reg32 offset="0x046e" name="RBBM_PERFCTR_RBBM_SEL_3" type="a5xx_rbbm_perfcounter_select"/>
1333 <reg32 offset="0x04d2" name="RBBM_ALWAYSON_COUNTER_LO"/>
1334 <reg32 offset="0x04d3" name="RBBM_ALWAYSON_COUNTER_HI"/>
1335 <reg32 offset="0x04f5" name="RBBM_STATUS">
1367 <bitfield high="0" low="0" name="HI_BUSY" />
1369 <reg32 offset="0x0530" name="RBBM_STATUS3">
1372 <reg32 offset="0x04e1" name="RBBM_INT_0_STATUS"/>
1373 <reg32 offset="0x04f0" name="RBBM_AHB_ME_SPLIT_STATUS"/>
1374 <reg32 offset="0x04f1" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
1375 <reg32 offset="0x04f3" name="RBBM_AHB_ETS_SPLIT_STATUS"/>
1376 <reg32 offset="0x04f4" name="RBBM_AHB_ERROR_STATUS"/>
1377 <reg32 offset="0x0464" name="RBBM_PERFCTR_CNTL"/>
1378 <reg32 offset="0x0465" name="RBBM_PERFCTR_LOAD_CMD0"/>
1379 <reg32 offset="0x0466" name="RBBM_PERFCTR_LOAD_CMD1"/>
1380 <reg32 offset="0x0467" name="RBBM_PERFCTR_LOAD_CMD2"/>
1381 <reg32 offset="0x0468" name="RBBM_PERFCTR_LOAD_CMD3"/>
1382 <reg32 offset="0x0469" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1383 <reg32 offset="0x046a" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1384 <reg32 offset="0x046f" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1385 <reg32 offset="0x04ed" name="RBBM_AHB_ERROR"/>
1386 <reg32 offset="0x0504" name="RBBM_CFG_DBGBUS_EVENT_LOGIC"/>
1387 <reg32 offset="0x0505" name="RBBM_CFG_DBGBUS_OVER"/>
1388 <reg32 offset="0x0506" name="RBBM_CFG_DBGBUS_COUNT0"/>
1389 <reg32 offset="0x0507" name="RBBM_CFG_DBGBUS_COUNT1"/>
1390 <reg32 offset="0x0508" name="RBBM_CFG_DBGBUS_COUNT2"/>
1391 <reg32 offset="0x0509" name="RBBM_CFG_DBGBUS_COUNT3"/>
1392 <reg32 offset="0x050a" name="RBBM_CFG_DBGBUS_COUNT4"/>
1393 <reg32 offset="0x050b" name="RBBM_CFG_DBGBUS_COUNT5"/>
1394 <reg32 offset="0x050c" name="RBBM_CFG_DBGBUS_TRACE_ADDR"/>
1395 <reg32 offset="0x050d" name="RBBM_CFG_DBGBUS_TRACE_BUF0"/>
1396 <reg32 offset="0x050e" name="RBBM_CFG_DBGBUS_TRACE_BUF1"/>
1397 <reg32 offset="0x050f" name="RBBM_CFG_DBGBUS_TRACE_BUF2"/>
1398 <reg32 offset="0x0510" name="RBBM_CFG_DBGBUS_TRACE_BUF3"/>
1399 <reg32 offset="0x0511" name="RBBM_CFG_DBGBUS_TRACE_BUF4"/>
1400 <reg32 offset="0x0512" name="RBBM_CFG_DBGBUS_MISR0"/>
1401 <reg32 offset="0x0513" name="RBBM_CFG_DBGBUS_MISR1"/>
1402 <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1403 <reg32 offset="0xf000" name="RBBM_SECVID_TRUST_CONFIG"/>
1404 <reg32 offset="0xf400" name="RBBM_SECVID_TRUST_CNTL"/>
1405 <reg32 offset="0xf800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1406 <reg32 offset="0xf801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1407 <reg32 offset="0xf802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1408 <reg32 offset="0xf803" name="RBBM_SECVID_TSB_CNTL"/>
1409 <reg32 offset="0xf804" name="RBBM_SECVID_TSB_COMP_STATUS_LO"/>
1410 <reg32 offset="0xf805" name="RBBM_SECVID_TSB_COMP_STATUS_HI"/>
1411 <reg32 offset="0xf806" name="RBBM_SECVID_TSB_UCHE_STATUS_LO"/>
1412 <reg32 offset="0xf807" name="RBBM_SECVID_TSB_UCHE_STATUS_HI"/>
1413 <reg32 offset="0xf810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1416 <reg32 offset="0x0bc2" name="VSC_BIN_SIZE">
1417 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1421 <reg32 offset="0x0bc3" name="VSC_SIZE_ADDRESS_LO"/>
1422 <reg32 offset="0x0bc4" name="VSC_SIZE_ADDRESS_HI"/>
1423 <reg32 offset="0x0bc5" name="UNKNOWN_0BC5"/> <!-- always 00000000? -->
1424 <reg32 offset="0x0bc6" name="UNKNOWN_0BC6"/> <!-- always 00000000? -->
1425 <array offset="0x0bd0" name="VSC_PIPE_CONFIG" stride="1" length="16">
1426 <reg32 offset="0x0" name="REG">
1430 direction (0,0 is upper left, 0,1 is leftmost bin
1435 <bitfield name="X" low="0" high="9" type="uint"/>
1441 <array offset="0x0be0" name="VSC_PIPE_DATA_ADDRESS" stride="2" length="16">
1442 <reg32 offset="0x0" name="LO"/>
1443 <reg32 offset="0x1" name="HI"/>
1445 <array offset="0x0c00" name="VSC_PIPE_DATA_LENGTH" stride="1" length="16">
1446 <reg32 offset="0x0" name="REG"/>
1448 <reg32 offset="0x0c60" name="VSC_PERFCTR_VSC_SEL_0" type="a5xx_vsc_perfcounter_select"/>
1449 <reg32 offset="0x0c61" name="VSC_PERFCTR_VSC_SEL_1" type="a5xx_vsc_perfcounter_select"/>
1452 <reg32 offset="0x0cdd" name="VSC_RESOLVE_CNTL" type="adreno_reg_xy"/>
1455 <reg32 offset="0x0c81" name="GRAS_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1456 <reg32 offset="0x0c90" name="GRAS_PERFCTR_TSE_SEL_0" type="a5xx_tse_perfcounter_select"/>
1457 <reg32 offset="0x0c91" name="GRAS_PERFCTR_TSE_SEL_1" type="a5xx_tse_perfcounter_select"/>
1458 <reg32 offset="0x0c92" name="GRAS_PERFCTR_TSE_SEL_2" type="a5xx_tse_perfcounter_select"/>
1459 <reg32 offset="0x0c93" name="GRAS_PERFCTR_TSE_SEL_3" type="a5xx_tse_perfcounter_select"/>
1460 <reg32 offset="0x0c94" name="GRAS_PERFCTR_RAS_SEL_0" type="a5xx_ras_perfcounter_select"/>
1461 <reg32 offset="0x0c95" name="GRAS_PERFCTR_RAS_SEL_1" type="a5xx_ras_perfcounter_select"/>
1462 <reg32 offset="0x0c96" name="GRAS_PERFCTR_RAS_SEL_2" type="a5xx_ras_perfcounter_select"/>
1463 <reg32 offset="0x0c97" name="GRAS_PERFCTR_RAS_SEL_3" type="a5xx_ras_perfcounter_select"/>
1464 <reg32 offset="0x0c98" name="GRAS_PERFCTR_LRZ_SEL_0" type="a5xx_lrz_perfcounter_select"/>
1465 <reg32 offset="0x0c99" name="GRAS_PERFCTR_LRZ_SEL_1" type="a5xx_lrz_perfcounter_select"/>
1466 <reg32 offset="0x0c9a" name="GRAS_PERFCTR_LRZ_SEL_2" type="a5xx_lrz_perfcounter_select"/>
1467 <reg32 offset="0x0c9b" name="GRAS_PERFCTR_LRZ_SEL_3" type="a5xx_lrz_perfcounter_select"/>
1469 <reg32 offset="0x0cc4" name="RB_DBG_ECO_CNTL"/> <!-- always 00100000? -->
1470 <reg32 offset="0x0cc5" name="RB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1471 <reg32 offset="0x0cc6" name="RB_MODE_CNTL"/> <!-- always 00000044? -->
1472 <reg32 offset="0x0cc7" name="RB_CCU_CNTL"/> <!-- always b0056080 or 10000000? -->
1473 <reg32 offset="0x0cd0" name="RB_PERFCTR_RB_SEL_0" type="a5xx_rb_perfcounter_select"/>
1474 <reg32 offset="0x0cd1" name="RB_PERFCTR_RB_SEL_1" type="a5xx_rb_perfcounter_select"/>
1475 <reg32 offset="0x0cd2" name="RB_PERFCTR_RB_SEL_2" type="a5xx_rb_perfcounter_select"/>
1476 <reg32 offset="0x0cd3" name="RB_PERFCTR_RB_SEL_3" type="a5xx_rb_perfcounter_select"/>
1477 <reg32 offset="0x0cd4" name="RB_PERFCTR_RB_SEL_4" type="a5xx_rb_perfcounter_select"/>
1478 <reg32 offset="0x0cd5" name="RB_PERFCTR_RB_SEL_5" type="a5xx_rb_perfcounter_select"/>
1479 <reg32 offset="0x0cd6" name="RB_PERFCTR_RB_SEL_6" type="a5xx_rb_perfcounter_select"/>
1480 <reg32 offset="0x0cd7" name="RB_PERFCTR_RB_SEL_7" type="a5xx_rb_perfcounter_select"/>
1481 <reg32 offset="0x0cd8" name="RB_PERFCTR_CCU_SEL_0" type="a5xx_ccu_perfcounter_select"/>
1482 <reg32 offset="0x0cd9" name="RB_PERFCTR_CCU_SEL_1" type="a5xx_ccu_perfcounter_select"/>
1483 <reg32 offset="0x0cda" name="RB_PERFCTR_CCU_SEL_2" type="a5xx_ccu_perfcounter_select"/>
1484 <reg32 offset="0x0cdb" name="RB_PERFCTR_CCU_SEL_3" type="a5xx_ccu_perfcounter_select"/>
1485 <reg32 offset="0x0ce0" name="RB_POWERCTR_RB_SEL_0"/>
1486 <reg32 offset="0x0ce1" name="RB_POWERCTR_RB_SEL_1"/>
1487 <reg32 offset="0x0ce2" name="RB_POWERCTR_RB_SEL_2"/>
1488 <reg32 offset="0x0ce3" name="RB_POWERCTR_RB_SEL_3"/>
1489 <reg32 offset="0x0ce4" name="RB_POWERCTR_CCU_SEL_0"/>
1490 <reg32 offset="0x0ce5" name="RB_POWERCTR_CCU_SEL_1"/>
1491 <reg32 offset="0x0cec" name="RB_PERFCTR_CMP_SEL_0" type="a5xx_cmp_perfcounter_select"/>
1492 <reg32 offset="0x0ced" name="RB_PERFCTR_CMP_SEL_1" type="a5xx_cmp_perfcounter_select"/>
1493 <reg32 offset="0x0cee" name="RB_PERFCTR_CMP_SEL_2" type="a5xx_cmp_perfcounter_select"/>
1494 <reg32 offset="0x0cef" name="RB_PERFCTR_CMP_SEL_3" type="a5xx_cmp_perfcounter_select"/>
1496 <reg32 offset="0x0d00" name="PC_DBG_ECO_CNTL">
1499 <reg32 offset="0x0d01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1500 <reg32 offset="0x0d02" name="PC_MODE_CNTL"/> <!-- always 0000001f? -->
1501 <reg32 offset="0x0d04" name="PC_INDEX_BUF_LO"/>
1502 <reg32 offset="0x0d05" name="PC_INDEX_BUF_HI"/>
1503 <reg32 offset="0x0d06" name="PC_START_INDEX"/>
1504 <reg32 offset="0x0d07" name="PC_MAX_INDEX"/>
1505 <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR_LO"/>
1506 <reg32 offset="0x0d09" name="PC_TESSFACTOR_ADDR_HI"/>
1507 <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a5xx_pc_perfcounter_select"/>
1508 <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a5xx_pc_perfcounter_select"/>
1509 <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a5xx_pc_perfcounter_select"/>
1510 <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a5xx_pc_perfcounter_select"/>
1511 <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a5xx_pc_perfcounter_select"/>
1512 <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a5xx_pc_perfcounter_select"/>
1513 <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a5xx_pc_perfcounter_select"/>
1514 <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a5xx_pc_perfcounter_select"/>
1516 <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD_0"/>
1517 <reg32 offset="0x0e01" name="HLSQ_TIMEOUT_THRESHOLD_1"/>
1518 <reg32 offset="0x0e04" name="HLSQ_DBG_ECO_CNTL"/>
1519 <reg32 offset="0x0e05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1520 <reg32 offset="0x0e06" name="HLSQ_MODE_CNTL"/> <!-- always 00000001? -->
1521 <reg32 offset="0x0e10" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a5xx_hlsq_perfcounter_select"/>
1522 <reg32 offset="0x0e11" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a5xx_hlsq_perfcounter_select"/>
1523 <reg32 offset="0x0e12" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a5xx_hlsq_perfcounter_select"/>
1524 <reg32 offset="0x0e13" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a5xx_hlsq_perfcounter_select"/>
1525 <reg32 offset="0x0e14" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a5xx_hlsq_perfcounter_select"/>
1526 <reg32 offset="0x0e15" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a5xx_hlsq_perfcounter_select"/>
1527 <reg32 offset="0x0e16" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a5xx_hlsq_perfcounter_select"/>
1528 <reg32 offset="0x0e17" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a5xx_hlsq_perfcounter_select"/>
1529 <reg32 offset="0x0f08" name="HLSQ_SPTP_RDSEL"/>
1530 <reg32 offset="0xbc00" name="HLSQ_DBG_READ_SEL"/>
1531 <reg32 offset="0xa000" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1533 <reg32 offset="0x0e41" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1534 <reg32 offset="0x0e42" name="VFD_MODE_CNTL"/> <!-- always 00000000? -->
1535 <reg32 offset="0x0e50" name="VFD_PERFCTR_VFD_SEL_0" type="a5xx_vfd_perfcounter_select"/>
1536 <reg32 offset="0x0e51" name="VFD_PERFCTR_VFD_SEL_1" type="a5xx_vfd_perfcounter_select"/>
1537 <reg32 offset="0x0e52" name="VFD_PERFCTR_VFD_SEL_2" type="a5xx_vfd_perfcounter_select"/>
1538 <reg32 offset="0x0e53" name="VFD_PERFCTR_VFD_SEL_3" type="a5xx_vfd_perfcounter_select"/>
1539 <reg32 offset="0x0e54" name="VFD_PERFCTR_VFD_SEL_4" type="a5xx_vfd_perfcounter_select"/>
1540 <reg32 offset="0x0e55" name="VFD_PERFCTR_VFD_SEL_5" type="a5xx_vfd_perfcounter_select"/>
1541 <reg32 offset="0x0e56" name="VFD_PERFCTR_VFD_SEL_6" type="a5xx_vfd_perfcounter_select"/>
1542 <reg32 offset="0x0e57" name="VFD_PERFCTR_VFD_SEL_7" type="a5xx_vfd_perfcounter_select"/>
1543 <reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL">
1546 <reg32 offset="0x0e61" name="VPC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1547 <reg32 offset="0x0e62" name="VPC_MODE_CNTL">
1548 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
1550 <reg32 offset="0x0e64" name="VPC_PERFCTR_VPC_SEL_0" type="a5xx_vpc_perfcounter_select"/>
1551 <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_1" type="a5xx_vpc_perfcounter_select"/>
1552 <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_2" type="a5xx_vpc_perfcounter_select"/>
1553 <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_3" type="a5xx_vpc_perfcounter_select"/>
1555 <reg32 offset="0x0e80" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1556 <reg32 offset="0x0e81" name="UCHE_MODE_CNTL"/>
1557 <reg32 offset="0x0e82" name="UCHE_SVM_CNTL"/>
1558 <reg32 offset="0x0e87" name="UCHE_WRITE_THRU_BASE_LO"/>
1559 <reg32 offset="0x0e88" name="UCHE_WRITE_THRU_BASE_HI"/>
1560 <reg32 offset="0x0e89" name="UCHE_TRAP_BASE_LO"/>
1561 <reg32 offset="0x0e8a" name="UCHE_TRAP_BASE_HI"/>
1562 <reg32 offset="0x0e8b" name="UCHE_GMEM_RANGE_MIN_LO"/>
1563 <reg32 offset="0x0e8c" name="UCHE_GMEM_RANGE_MIN_HI"/>
1564 <reg32 offset="0x0e8d" name="UCHE_GMEM_RANGE_MAX_LO"/>
1565 <reg32 offset="0x0e8e" name="UCHE_GMEM_RANGE_MAX_HI"/>
1566 <reg32 offset="0x0e8f" name="UCHE_DBG_ECO_CNTL_2"/>
1567 <reg32 offset="0x0e90" name="UCHE_DBG_ECO_CNTL"/>
1568 <reg32 offset="0x0e91" name="UCHE_CACHE_INVALIDATE_MIN_LO"/>
1569 <reg32 offset="0x0e92" name="UCHE_CACHE_INVALIDATE_MIN_HI"/>
1570 <reg32 offset="0x0e93" name="UCHE_CACHE_INVALIDATE_MAX_LO"/>
1571 <reg32 offset="0x0e94" name="UCHE_CACHE_INVALIDATE_MAX_HI"/>
1572 <reg32 offset="0x0e95" name="UCHE_CACHE_INVALIDATE"/>
1573 <reg32 offset="0x0e96" name="UCHE_CACHE_WAYS"/>
1574 <reg32 offset="0x0ea0" name="UCHE_PERFCTR_UCHE_SEL_0" type="a5xx_uche_perfcounter_select"/>
1575 <reg32 offset="0x0ea1" name="UCHE_PERFCTR_UCHE_SEL_1" type="a5xx_uche_perfcounter_select"/>
1576 <reg32 offset="0x0ea2" name="UCHE_PERFCTR_UCHE_SEL_2" type="a5xx_uche_perfcounter_select"/>
1577 <reg32 offset="0x0ea3" name="UCHE_PERFCTR_UCHE_SEL_3" type="a5xx_uche_perfcounter_select"/>
1578 <reg32 offset="0x0ea4" name="UCHE_PERFCTR_UCHE_SEL_4" type="a5xx_uche_perfcounter_select"/>
1579 <reg32 offset="0x0ea5" name="UCHE_PERFCTR_UCHE_SEL_5" type="a5xx_uche_perfcounter_select"/>
1580 <reg32 offset="0x0ea6" name="UCHE_PERFCTR_UCHE_SEL_6" type="a5xx_uche_perfcounter_select"/>
1581 <reg32 offset="0x0ea7" name="UCHE_PERFCTR_UCHE_SEL_7" type="a5xx_uche_perfcounter_select"/>
1582 <reg32 offset="0x0ea8" name="UCHE_POWERCTR_UCHE_SEL_0"/>
1583 <reg32 offset="0x0ea9" name="UCHE_POWERCTR_UCHE_SEL_1"/>
1584 <reg32 offset="0x0eaa" name="UCHE_POWERCTR_UCHE_SEL_2"/>
1585 <reg32 offset="0x0eab" name="UCHE_POWERCTR_UCHE_SEL_3"/>
1586 <reg32 offset="0x0eb1" name="UCHE_TRAP_LOG_LO"/>
1587 <reg32 offset="0x0eb2" name="UCHE_TRAP_LOG_HI"/>
1589 <reg32 offset="0x0ec0" name="SP_DBG_ECO_CNTL"/>
1590 <reg32 offset="0x0ec1" name="SP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1591 <reg32 offset="0x0ec2" name="SP_MODE_CNTL"/> <!-- always 0000001e? -->
1592 <reg32 offset="0x0ed0" name="SP_PERFCTR_SP_SEL_0" type="a5xx_sp_perfcounter_select"/>
1593 <reg32 offset="0x0ed1" name="SP_PERFCTR_SP_SEL_1" type="a5xx_sp_perfcounter_select"/>
1594 <reg32 offset="0x0ed2" name="SP_PERFCTR_SP_SEL_2" type="a5xx_sp_perfcounter_select"/>
1595 <reg32 offset="0x0ed3" name="SP_PERFCTR_SP_SEL_3" type="a5xx_sp_perfcounter_select"/>
1596 <reg32 offset="0x0ed4" name="SP_PERFCTR_SP_SEL_4" type="a5xx_sp_perfcounter_select"/>
1597 <reg32 offset="0x0ed5" name="SP_PERFCTR_SP_SEL_5" type="a5xx_sp_perfcounter_select"/>
1598 <reg32 offset="0x0ed6" name="SP_PERFCTR_SP_SEL_6" type="a5xx_sp_perfcounter_select"/>
1599 <reg32 offset="0x0ed7" name="SP_PERFCTR_SP_SEL_7" type="a5xx_sp_perfcounter_select"/>
1600 <reg32 offset="0x0ed8" name="SP_PERFCTR_SP_SEL_8" type="a5xx_sp_perfcounter_select"/>
1601 <reg32 offset="0x0ed9" name="SP_PERFCTR_SP_SEL_9" type="a5xx_sp_perfcounter_select"/>
1602 <reg32 offset="0x0eda" name="SP_PERFCTR_SP_SEL_10" type="a5xx_sp_perfcounter_select"/>
1603 <reg32 offset="0x0edb" name="SP_PERFCTR_SP_SEL_11" type="a5xx_sp_perfcounter_select"/>
1604 <reg32 offset="0x0edc" name="SP_POWERCTR_SP_SEL_0"/>
1605 <reg32 offset="0x0edd" name="SP_POWERCTR_SP_SEL_1"/>
1606 <reg32 offset="0x0ede" name="SP_POWERCTR_SP_SEL_2"/>
1607 <reg32 offset="0x0edf" name="SP_POWERCTR_SP_SEL_3"/>
1609 <reg32 offset="0x0f01" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1610 <reg32 offset="0x0f02" name="TPL1_MODE_CNTL"/> <!-- always 00000544? -->
1611 <reg32 offset="0x0f10" name="TPL1_PERFCTR_TP_SEL_0" type="a5xx_tp_perfcounter_select"/>
1612 <reg32 offset="0x0f11" name="TPL1_PERFCTR_TP_SEL_1" type="a5xx_tp_perfcounter_select"/>
1613 <reg32 offset="0x0f12" name="TPL1_PERFCTR_TP_SEL_2" type="a5xx_tp_perfcounter_select"/>
1614 <reg32 offset="0x0f13" name="TPL1_PERFCTR_TP_SEL_3" type="a5xx_tp_perfcounter_select"/>
1615 <reg32 offset="0x0f14" name="TPL1_PERFCTR_TP_SEL_4" type="a5xx_tp_perfcounter_select"/>
1616 <reg32 offset="0x0f15" name="TPL1_PERFCTR_TP_SEL_5" type="a5xx_tp_perfcounter_select"/>
1617 <reg32 offset="0x0f16" name="TPL1_PERFCTR_TP_SEL_6" type="a5xx_tp_perfcounter_select"/>
1618 <reg32 offset="0x0f17" name="TPL1_PERFCTR_TP_SEL_7" type="a5xx_tp_perfcounter_select"/>
1619 <reg32 offset="0x0f18" name="TPL1_POWERCTR_TP_SEL_0"/>
1620 <reg32 offset="0x0f19" name="TPL1_POWERCTR_TP_SEL_1"/>
1621 <reg32 offset="0x0f1a" name="TPL1_POWERCTR_TP_SEL_2"/>
1622 <reg32 offset="0x0f1b" name="TPL1_POWERCTR_TP_SEL_3"/>
1624 <reg32 offset="0x3000" name="VBIF_VERSION"/>
1625 <reg32 offset="0x3001" name="VBIF_CLKON"/>
1627 #define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_MASK 0x1
1628 #define A5XX_VBIF_CLKON_FORCE_ON_TESTBUS_SHIFT 0x1
1630 <reg32 offset="0x3028" name="VBIF_ABIT_SORT"/>
1631 <reg32 offset="0x3029" name="VBIF_ABIT_SORT_CONF"/>
1632 <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
1633 <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
1634 <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
1635 <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
1636 <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1638 #define A5XX_VBIF_XIN_HALT_CTRL0_MASK 0xF
1639 #define A510_VBIF_XIN_HALT_CTRL0_MASK 0x7
1641 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1642 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1644 #define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_MASK 0x1
1645 #define A5XX_VBIF_TEST_BUS_OUT_CTRL_EN_SHIFT 0x0
1647 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1648 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"/>
1650 #define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_MASK 0xF
1651 #define A5XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL_SHIFT 0x0
1653 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1654 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"/>
1656 #define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_MASK 0xF
1657 #define A5XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL_SHIFT 0x0
1659 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1660 <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
1661 <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
1662 <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
1663 <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
1664 <reg32 offset="0x30c8" name="VBIF_PERF_CNT_CLR0"/>
1665 <reg32 offset="0x30c9" name="VBIF_PERF_CNT_CLR1"/>
1666 <reg32 offset="0x30ca" name="VBIF_PERF_CNT_CLR2"/>
1667 <reg32 offset="0x30cb" name="VBIF_PERF_CNT_CLR3"/>
1668 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a5xx_vbif_perfcounter_select"/>
1669 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a5xx_vbif_perfcounter_select"/>
1670 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a5xx_vbif_perfcounter_select"/>
1671 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a5xx_vbif_perfcounter_select"/>
1672 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1673 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1674 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1675 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1676 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1677 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1678 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1679 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1680 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1681 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1682 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1683 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1684 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1685 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1686 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1687 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1688 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1690 <reg32 offset="0x8800" name="GPMU_INST_RAM_BASE"/>
1691 <reg32 offset="0x9800" name="GPMU_DATA_RAM_BASE"/>
1695 #define A5XX_SP_ALU_ACTIVE_CYCLES 0x1
1696 #define A5XX_SP0_ICL1_MISSES 0x35
1697 #define A5XX_SP_FS_CFLOW_INSTRUCTIONS 0x27
1700 #define A5XX_TSE_INPUT_PRIM_NUM 0x6
1702 <reg32 offset="0xa840" name="SP_POWER_COUNTER_0_LO"/>
1703 <reg32 offset="0xa841" name="SP_POWER_COUNTER_0_HI"/>
1704 <reg32 offset="0xa842" name="SP_POWER_COUNTER_1_LO"/>
1705 <reg32 offset="0xa843" name="SP_POWER_COUNTER_1_HI"/>
1706 <reg32 offset="0xa844" name="SP_POWER_COUNTER_2_LO"/>
1707 <reg32 offset="0xa845" name="SP_POWER_COUNTER_2_HI"/>
1708 <reg32 offset="0xa846" name="SP_POWER_COUNTER_3_LO"/>
1709 <reg32 offset="0xa847" name="SP_POWER_COUNTER_3_HI"/>
1710 <reg32 offset="0xa848" name="TP_POWER_COUNTER_0_LO"/>
1711 <reg32 offset="0xa849" name="TP_POWER_COUNTER_0_HI"/>
1712 <reg32 offset="0xa84a" name="TP_POWER_COUNTER_1_LO"/>
1713 <reg32 offset="0xa84b" name="TP_POWER_COUNTER_1_HI"/>
1714 <reg32 offset="0xa84c" name="TP_POWER_COUNTER_2_LO"/>
1715 <reg32 offset="0xa84d" name="TP_POWER_COUNTER_2_HI"/>
1716 <reg32 offset="0xa84e" name="TP_POWER_COUNTER_3_LO"/>
1717 <reg32 offset="0xa84f" name="TP_POWER_COUNTER_3_HI"/>
1718 <reg32 offset="0xa850" name="RB_POWER_COUNTER_0_LO"/>
1719 <reg32 offset="0xa851" name="RB_POWER_COUNTER_0_HI"/>
1720 <reg32 offset="0xa852" name="RB_POWER_COUNTER_1_LO"/>
1721 <reg32 offset="0xa853" name="RB_POWER_COUNTER_1_HI"/>
1722 <reg32 offset="0xa854" name="RB_POWER_COUNTER_2_LO"/>
1723 <reg32 offset="0xa855" name="RB_POWER_COUNTER_2_HI"/>
1724 <reg32 offset="0xa856" name="RB_POWER_COUNTER_3_LO"/>
1725 <reg32 offset="0xa857" name="RB_POWER_COUNTER_3_HI"/>
1726 <reg32 offset="0xa858" name="CCU_POWER_COUNTER_0_LO"/>
1727 <reg32 offset="0xa859" name="CCU_POWER_COUNTER_0_HI"/>
1728 <reg32 offset="0xa85a" name="CCU_POWER_COUNTER_1_LO"/>
1729 <reg32 offset="0xa85b" name="CCU_POWER_COUNTER_1_HI"/>
1730 <reg32 offset="0xa85c" name="UCHE_POWER_COUNTER_0_LO"/>
1731 <reg32 offset="0xa85d" name="UCHE_POWER_COUNTER_0_HI"/>
1732 <reg32 offset="0xa85e" name="UCHE_POWER_COUNTER_1_LO"/>
1733 <reg32 offset="0xa85f" name="UCHE_POWER_COUNTER_1_HI"/>
1734 <reg32 offset="0xa860" name="UCHE_POWER_COUNTER_2_LO"/>
1735 <reg32 offset="0xa861" name="UCHE_POWER_COUNTER_2_HI"/>
1736 <reg32 offset="0xa862" name="UCHE_POWER_COUNTER_3_LO"/>
1737 <reg32 offset="0xa863" name="UCHE_POWER_COUNTER_3_HI"/>
1738 <reg32 offset="0xa864" name="CP_POWER_COUNTER_0_LO"/>
1739 <reg32 offset="0xa865" name="CP_POWER_COUNTER_0_HI"/>
1740 <reg32 offset="0xa866" name="CP_POWER_COUNTER_1_LO"/>
1741 <reg32 offset="0xa867" name="CP_POWER_COUNTER_1_HI"/>
1742 <reg32 offset="0xa868" name="CP_POWER_COUNTER_2_LO"/>
1743 <reg32 offset="0xa869" name="CP_POWER_COUNTER_2_HI"/>
1744 <reg32 offset="0xa86a" name="CP_POWER_COUNTER_3_LO"/>
1745 <reg32 offset="0xa86b" name="CP_POWER_COUNTER_3_HI"/>
1746 <reg32 offset="0xa86c" name="GPMU_POWER_COUNTER_0_LO"/>
1747 <reg32 offset="0xa86d" name="GPMU_POWER_COUNTER_0_HI"/>
1748 <reg32 offset="0xa86e" name="GPMU_POWER_COUNTER_1_LO"/>
1749 <reg32 offset="0xa86f" name="GPMU_POWER_COUNTER_1_HI"/>
1750 <reg32 offset="0xa870" name="GPMU_POWER_COUNTER_2_LO"/>
1751 <reg32 offset="0xa871" name="GPMU_POWER_COUNTER_2_HI"/>
1752 <reg32 offset="0xa872" name="GPMU_POWER_COUNTER_3_LO"/>
1753 <reg32 offset="0xa873" name="GPMU_POWER_COUNTER_3_HI"/>
1754 <reg32 offset="0xa874" name="GPMU_POWER_COUNTER_4_LO"/>
1755 <reg32 offset="0xa875" name="GPMU_POWER_COUNTER_4_HI"/>
1756 <reg32 offset="0xa876" name="GPMU_POWER_COUNTER_5_LO"/>
1757 <reg32 offset="0xa877" name="GPMU_POWER_COUNTER_5_HI"/>
1758 <reg32 offset="0xa878" name="GPMU_POWER_COUNTER_ENABLE"/>
1759 <reg32 offset="0xa879" name="GPMU_ALWAYS_ON_COUNTER_LO"/>
1760 <reg32 offset="0xa87a" name="GPMU_ALWAYS_ON_COUNTER_HI"/>
1761 <reg32 offset="0xa87b" name="GPMU_ALWAYS_ON_COUNTER_RESET"/>
1762 <reg32 offset="0xa87c" name="GPMU_POWER_COUNTER_SELECT_0"/>
1763 <reg32 offset="0xa87d" name="GPMU_POWER_COUNTER_SELECT_1"/>
1765 <reg32 offset="0xa880" name="GPMU_GPMU_SP_CLOCK_CONTROL"/>
1766 <reg32 offset="0xa881" name="GPMU_SP_POWER_CNTL"/>
1767 <reg32 offset="0xa886" name="GPMU_RBCCU_CLOCK_CNTL"/>
1768 <reg32 offset="0xa887" name="GPMU_RBCCU_POWER_CNTL"/>
1769 <reg32 offset="0xa88b" name="GPMU_SP_PWR_CLK_STATUS">
1772 <reg32 offset="0xa88d" name="GPMU_RBCCU_PWR_CLK_STATUS">
1775 <reg32 offset="0xa891" name="GPMU_PWR_COL_STAGGER_DELAY"/>
1776 <reg32 offset="0xa892" name="GPMU_PWR_COL_INTER_FRAME_CTRL"/>
1777 <reg32 offset="0xa893" name="GPMU_PWR_COL_INTER_FRAME_HYST"/>
1778 <reg32 offset="0xa894" name="GPMU_PWR_COL_BINNING_CTRL"/>
1779 <reg32 offset="0xa8a3" name="GPMU_CLOCK_THROTTLE_CTRL"/>
1780 <reg32 offset="0xa8a8" name="GPMU_THROTTLE_UNMASK_FORCE_CTRL"/>
1781 <reg32 offset="0xa8c1" name="GPMU_WFI_CONFIG"/>
1782 <reg32 offset="0xa8d6" name="GPMU_RBBM_INTR_INFO"/>
1783 <reg32 offset="0xa8d8" name="GPMU_CM3_SYSRESET"/>
1784 <reg32 offset="0xa8e0" name="GPMU_GENERAL_0"/>
1785 <reg32 offset="0xa8e1" name="GPMU_GENERAL_1"/>
1786 <reg32 offset="0xac00" name="GPMU_TEMP_SENSOR_ID"/>
1787 <reg32 offset="0xac01" name="GPMU_TEMP_SENSOR_CONFIG"/>
1788 <reg32 offset="0xac02" name="GPMU_TEMP_VAL"/>
1789 <reg32 offset="0xac03" name="GPMU_DELTA_TEMP_THRESHOLD"/>
1790 <reg32 offset="0xac05" name="GPMU_TEMP_THRESHOLD_INTR_STATUS"/>
1791 <reg32 offset="0xac06" name="GPMU_TEMP_THRESHOLD_INTR_EN_MASK"/>
1792 <reg32 offset="0xac40" name="GPMU_LEAKAGE_TEMP_COEFF_0_1"/>
1793 <reg32 offset="0xac41" name="GPMU_LEAKAGE_TEMP_COEFF_2_3"/>
1794 <reg32 offset="0xac42" name="GPMU_LEAKAGE_VTG_COEFF_0_1"/>
1795 <reg32 offset="0xac43" name="GPMU_LEAKAGE_VTG_COEFF_2_3"/>
1796 <reg32 offset="0xac46" name="GPMU_BASE_LEAKAGE"/>
1797 <reg32 offset="0xac60" name="GPMU_GPMU_VOLTAGE"/>
1798 <reg32 offset="0xac61" name="GPMU_GPMU_VOLTAGE_INTR_STATUS"/>
1799 <reg32 offset="0xac62" name="GPMU_GPMU_VOLTAGE_INTR_EN_MASK"/>
1800 <reg32 offset="0xac80" name="GPMU_GPMU_PWR_THRESHOLD"/>
1801 <reg32 offset="0xacc4" name="GPMU_GPMU_LLM_GLM_SLEEP_CTRL"/>
1802 <reg32 offset="0xacc5" name="GPMU_GPMU_LLM_GLM_SLEEP_STATUS"/>
1803 <reg32 offset="0xb80c" name="GDPM_CONFIG1"/>
1804 <reg32 offset="0xb80d" name="GDPM_CONFIG2"/>
1805 <reg32 offset="0xb80f" name="GDPM_INT_EN"/>
1806 <reg32 offset="0xb811" name="GDPM_INT_MASK"/>
1807 <reg32 offset="0xb9a0" name="GPMU_BEC_ENABLE"/>
1808 <reg32 offset="0xc41a" name="GPU_CS_SENSOR_GENERAL_STATUS"/>
1809 <reg32 offset="0xc41d" name="GPU_CS_AMP_CALIBRATION_STATUS1_0"/>
1810 <reg32 offset="0xc41f" name="GPU_CS_AMP_CALIBRATION_STATUS1_2"/>
1811 <reg32 offset="0xc421" name="GPU_CS_AMP_CALIBRATION_STATUS1_4"/>
1812 <reg32 offset="0xc520" name="GPU_CS_ENABLE_REG"/>
1813 <reg32 offset="0xc557" name="GPU_CS_AMP_CALIBRATION_CONTROL1"/>
1816 <reg32 offset="0xe000" name="GRAS_CL_CNTL">
1820 <bitfield name="CLIP_MASK" low="0" high="7"/>
1823 <reg32 offset="0xe001" name="GRAS_VS_CL_CNTL" type="a5xx_gras_xs_cl_cntl"/>
1824 <reg32 offset="0xe004" name="UNKNOWN_E004"/> <!-- always 00000000? -->
1825 <reg32 offset="0xe005" name="GRAS_CNTL">
1827 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1835 <reg32 offset="0xe006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1836 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1839 <reg32 offset="0xe010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1840 <reg32 offset="0xe011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1841 <reg32 offset="0xe012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1842 <reg32 offset="0xe013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1843 <reg32 offset="0xe014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1844 <reg32 offset="0xe015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1845 <reg32 offset="0xe090" name="GRAS_SU_CNTL">
1846 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1854 <reg32 offset="0xe091" name="GRAS_SU_POINT_MINMAX">
1855 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1858 <reg32 offset="0xe092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1859 <reg32 offset="0xe093" name="GRAS_SU_LAYERED"/>
1860 <reg32 offset="0xe094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1861 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1864 <reg32 offset="0xe095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1865 <reg32 offset="0xe096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1866 <reg32 offset="0xe097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1868 <reg32 offset="0xe098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1869 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
1871 <reg32 offset="0xe099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL"/> <!-- always 00000000? -->
1876 <reg32 offset="0xe0a0" name="GRAS_SC_CNTL">
1877 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
1880 <!-- note, 0x4 for binning pass when frag writes z?? -->
1881 <reg32 offset="0xe0a1" name="GRAS_SC_BIN_CNTL"/> <!-- always 00000000? -->
1882 <reg32 offset="0xe0a2" name="GRAS_SC_RAS_MSAA_CNTL">
1883 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1885 <reg32 offset="0xe0a3" name="GRAS_SC_DEST_MSAA_CNTL">
1886 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1889 <reg32 offset="0xe0a4" name="GRAS_SC_SCREEN_SCISSOR_CNTL"/> <!-- always 00000000? -->
1890 <reg32 offset="0xe0aa" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
1891 <reg32 offset="0xe0ab" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
1892 <reg32 offset="0xe0ca" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
1893 <reg32 offset="0xe0cb" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
1894 <reg32 offset="0xe0ea" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1895 <reg32 offset="0xe0eb" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1915 <reg32 offset="0xe100" name="GRAS_LRZ_CNTL">
1916 <bitfield name="ENABLE" pos="0" type="boolean"/>
1926 <reg32 offset="0xe101" name="GRAS_LRZ_BUFFER_BASE_LO"/>
1927 <reg32 offset="0xe102" name="GRAS_LRZ_BUFFER_BASE_HI"/>
1935 <reg32 offset="0xe103" name="GRAS_LRZ_BUFFER_PITCH" shr="5" type="uint"/>
1936 <reg32 offset="0xe104" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
1937 <reg32 offset="0xe105" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
1939 <reg32 offset="0xe140" name="RB_CNTL">
1940 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1944 <reg32 offset="0xe141" name="RB_RENDER_CNTL">
1951 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
1962 <reg32 offset="0xe142" name="RB_RAS_MSAA_CNTL">
1963 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1965 <reg32 offset="0xe143" name="RB_DEST_MSAA_CNTL">
1966 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1973 <reg32 offset="0xe144" name="RB_RENDER_CONTROL0">
1975 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1983 <reg32 offset="0xe145" name="RB_RENDER_CONTROL1">
1984 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
1988 <reg32 offset="0xe146" name="RB_FS_OUTPUT_CNTL">
1990 <bitfield name="MRT" low="0" high="3" type="uint"/>
1993 <reg32 offset="0xe147" name="RB_RENDER_COMPONENTS">
1994 <bitfield name="RT0" low="0" high="3"/>
2003 <array offset="0xe150" name="RB_MRT" stride="7" length="8">
2004 <reg32 offset="0x0" name="CONTROL">
2005 <bitfield name="BLEND" pos="0" type="boolean"/>
2011 <reg32 offset="0x1" name="BLEND_CONTROL">
2012 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2019 <reg32 offset="0x2" name="BUF_INFO">
2026 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2036 <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2037 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2038 <reg32 offset="0x5" name="BASE_LO"/>
2039 <reg32 offset="0x6" name="BASE_HI"/>
2041 <reg32 offset="0xe1a0" name="RB_BLEND_RED">
2042 <bitfield name="UINT" low="0" high="7" type="hex"/>
2046 <reg32 offset="0xe1a1" name="RB_BLEND_RED_F32" type="float"/>
2047 <reg32 offset="0xe1a2" name="RB_BLEND_GREEN">
2048 <bitfield name="UINT" low="0" high="7" type="hex"/>
2052 <reg32 offset="0xe1a3" name="RB_BLEND_GREEN_F32" type="float"/>
2053 <reg32 offset="0xe1a4" name="RB_BLEND_BLUE">
2054 <bitfield name="UINT" low="0" high="7" type="hex"/>
2058 <reg32 offset="0xe1a5" name="RB_BLEND_BLUE_F32" type="float"/>
2059 <reg32 offset="0xe1a6" name="RB_BLEND_ALPHA">
2060 <bitfield name="UINT" low="0" high="7" type="hex"/>
2064 <reg32 offset="0xe1a7" name="RB_BLEND_ALPHA_F32" type="float"/>
2065 <reg32 offset="0xe1a8" name="RB_ALPHA_CONTROL">
2066 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2070 <reg32 offset="0xe1a9" name="RB_BLEND_CNTL">
2072 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2078 <reg32 offset="0xe1b0" name="RB_DEPTH_PLANE_CNTL">
2079 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
2082 <reg32 offset="0xe1b1" name="RB_DEPTH_CNTL">
2083 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
2089 <reg32 offset="0xe1b2" name="RB_DEPTH_BUFFER_INFO">
2090 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a5xx_depth_format"/>
2092 <reg32 offset="0xe1b3" name="RB_DEPTH_BUFFER_BASE_LO"/>
2093 <reg32 offset="0xe1b4" name="RB_DEPTH_BUFFER_BASE_HI"/>
2094 <reg32 offset="0xe1b5" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2097 <reg32 offset="0xe1b6" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2100 <reg32 offset="0xe1c0" name="RB_STENCIL_CONTROL">
2101 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2119 <reg32 offset="0xe1c1" name="RB_STENCIL_INFO">
2120 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2122 <reg32 offset="0xe1c2" name="RB_STENCIL_BASE_LO"/>
2123 <reg32 offset="0xe1c3" name="RB_STENCIL_BASE_HI"/>
2124 <reg32 offset="0xe1c4" name="RB_STENCIL_PITCH" shr="6" type="uint"/>
2125 <reg32 offset="0xe1c5" name="RB_STENCIL_ARRAY_PITCH" shr="6" type="uint"/>
2126 <reg32 offset="0xe1c6" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
2127 <reg32 offset="0xe1c7" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
2128 <reg32 offset="0xe1d0" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2129 <reg32 offset="0xe1d1" name="RB_SAMPLE_COUNT_CONTROL">
2146 for the GMEM offset, and gpuaddr from RB_MRT[0].BASE_LO/HI
2149 <reg32 offset="0xe210" name="RB_BLIT_CNTL">
2150 <bitfield name="BUF" low="0" high="3" type="a5xx_blit_buf"/>
2152 <reg32 offset="0xe211" name="RB_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
2153 <reg32 offset="0xe212" name="RB_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
2154 <reg32 offset="0xe213" name="RB_RESOLVE_CNTL_3">
2156 <bitfield name="TILED" pos="0" type="boolean"/>
2158 0xe213:
2159 0x0 mem->gmem
2160 0xf gmem->mem with flag buffer (color)
2161 0x4 gmem->mem without flag buffer (color)
2162 0x7 BYPASS mode flag buffer result (ie. on readpix)
2166 <reg32 offset="0xe214" name="RB_BLIT_DST_LO"/>
2167 <reg32 offset="0xe215" name="RB_BLIT_DST_HI"/>
2168 <reg32 offset="0xe216" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2170 <reg32 offset="0xe217" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2171 <reg32 offset="0xe218" name="RB_CLEAR_COLOR_DW0"/>
2172 <reg32 offset="0xe219" name="RB_CLEAR_COLOR_DW1"/>
2173 <reg32 offset="0xe21a" name="RB_CLEAR_COLOR_DW2"/>
2174 <reg32 offset="0xe21b" name="RB_CLEAR_COLOR_DW3"/>
2175 <reg32 offset="0xe21c" name="RB_CLEAR_CNTL">
2184 then probably a component mask, I always see 0xf
2208 100x2000, ifmt=GL_RG, fmt=GL_RG16F, type=GL_FLOAT, meta=64x512@0x8000 (7x500)
2212 0 c073a000 c0732000 - level 0 flags is address
2225 so 0xc08c3000 - 0xc0732000 = 0x00191000 (1642496); each level
2229 …Y = A5XX_TEX_Y | SWIZ_Z = A5XX_TEX_ZERO | SWIZ_W = A5XX_TEX_ONE | MIPLVLS = 0 | FMT = TFMT5_16_16_…
2232 { ARRAY_PITCH = 1642496 | 0x18800000 } - NOTE c2dc always has 0x18800000 but
2233 { BASE_LO = 0xc0732000 } this varies for blob gles driver..
2234 { BASE_HI = 0 | DEPTH = 1 } not sure what it is
2238 <reg32 offset="0xe240" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2239 <reg32 offset="0xe241" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2240 <reg32 offset="0xe242" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2242 <array offset="0xe243" name="RB_MRT_FLAG_BUFFER" stride="4" length="8">
2243 <reg32 offset="0" name="ADDR_LO"/>
2249 <reg32 offset="0xe263" name="RB_BLIT_FLAG_DST_LO"/>
2250 <reg32 offset="0xe264" name="RB_BLIT_FLAG_DST_HI"/>
2251 <reg32 offset="0xe265" name="RB_BLIT_FLAG_DST_PITCH" shr="6" type="uint"/>
2253 <reg32 offset="0xe266" name="RB_BLIT_FLAG_DST_ARRAY_PITCH" shr="6" type="uint"/>
2255 <reg32 offset="0xe267" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2256 <reg32 offset="0xe268" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2258 <reg32 offset="0xe280" name="VPC_CNTL_0">
2264 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2267 <array offset="0xe282" name="VPC_VARYING_INTERP" stride="1" length="8">
2268 <reg32 offset="0x0" name="MODE"/>
2270 <array offset="0xe28a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2271 <reg32 offset="0x0" name="MODE"/>
2273 <reg32 offset="0xe292" name="UNKNOWN_E292"/>
2274 <reg32 offset="0xe293" name="UNKNOWN_E293"/>
2275 <array offset="0xe294" name="VPC_VAR" stride="1" length="4">
2277 <reg32 offset="0" name="DISABLE"/>
2279 <reg32 offset="0xe298" name="VPC_GS_SIV_CNTL"/>
2280 <reg32 offset="0xe29a" name="VPC_CLIP_CNTL">
2281 <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
2290 <reg32 offset="0xe29d" name="VPC_PACK">
2291 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2299 <reg32 offset="0xe2a0" name="VPC_FS_PRIMITIVEID_CNTL"/>
2305 VPC_SO[0..3] registers setup details about streamout buffers, and
2314 SP_VS_OUT[0].REG: { A_REGID = r0.w | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0x7 }
2315 SP_VS_OUT[0x1].REG: { A_REGID = r1.w | A_COMPMASK = 0x3 | B_REGID = r2.y | B_COMPMASK = 0xf }
2316 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 8 | OUTLOC3 = 12 }
2320 VPC_SO_PROG: { A_BUF = 0 | A_OFF = 0 | A_EN | A_BUF = 0 | B_OFF = 4 | B_EN }
2321 VPC_SO_PROG: { A_BUF = 0 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 12 | B_EN }
2322 VPC_SO_PROG: { A_BUF = 2 | A_OFF = 0 | A_EN | A_BUF = 2 | B_OFF = 4 | B_EN }
2323 VPC_SO_PROG: { A_BUF = 2 | A_OFF = 8 | A_EN | A_BUF = 0 | B_OFF = 0 }
2324 VPC_SO_PROG: { A_BUF = 1 | A_OFF = 0 | A_EN | A_BUF = 1 | B_OFF = 4 | B_EN }
2337 <reg32 offset="0xe2a1" name="VPC_SO_BUF_CNTL">
2338 <bitfield name="BUF0" pos="0" type="boolean"/>
2344 <reg32 offset="0xe2a2" name="VPC_SO_OVERRIDE">
2345 <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2347 <reg32 offset="0xe2a3" name="VPC_SO_CNTL">
2348 <!-- always 0x10000 when SO enabled.. -->
2351 <reg32 offset="0xe2a4" name="VPC_SO_PROG">
2352 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2359 <array offset="0xe2a7" name="VPC_SO" stride="7" length="4">
2360 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2369 <reg32 offset="0xe384" name="PC_PRIMITIVE_CNTL">
2371 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2376 <reg32 offset="0xe385" name="PC_PRIM_VTX_CNTL">
2379 <reg32 offset="0xe388" name="PC_RASTER_CNTL">
2380 <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
2384 <reg32 offset="0xe389" name="PC_CLIP_CNTL">
2385 <bitfield name="CLIP_MASK" low="0" high="7"/>
2387 <reg32 offset="0xe38c" name="PC_RESTART_INDEX"/>
2388 <reg32 offset="0xe38d" name="PC_GS_LAYERED"/>
2389 <reg32 offset="0xe38e" name="PC_GS_PARAM">
2390 <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- vertices - 1 -->
2394 <reg32 offset="0xe38f" name="PC_HS_PARAM">
2395 <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
2400 <reg32 offset="0xe3b0" name="PC_POWER_CNTL"/>
2402 <reg32 offset="0xe400" name="VFD_CONTROL_0">
2403 <bitfield name="VTXCNT" low="0" high="5" type="uint"/>
2405 <reg32 offset="0xe401" name="VFD_CONTROL_1">
2406 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2410 <reg32 offset="0xe402" name="VFD_CONTROL_2">
2411 …<bitfield name="REGID_PATCHID" low="0" high="7" type="a3xx_regid"/><!-- same as VFD_CONTROL_3.REGI…
2413 <reg32 offset="0xe403" name="VFD_CONTROL_3">
2418 <reg32 offset="0xe404" name="VFD_CONTROL_4">
2420 <reg32 offset="0xe405" name="VFD_CONTROL_5">
2423 <reg32 offset="0xe408" name="VFD_INDEX_OFFSET"/>
2424 <reg32 offset="0xe409" name="VFD_INSTANCE_START_OFFSET"/>
2425 <array offset="0xe40a" name="VFD_FETCH" stride="4" length="32">
2426 <reg32 offset="0x0" name="BASE_LO"/>
2427 <reg32 offset="0x1" name="BASE_HI"/>
2428 <reg32 offset="0x2" name="SIZE" type="uint"/>
2429 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2431 <array offset="0xe48a" name="VFD_DECODE" stride="2" length="32">
2432 <reg32 offset="0x0" name="INSTR">
2434 <bitfield name="IDX" low="0" high="4" type="uint"/>
2441 <reg32 offset="0x1" name="STEP_RATE"/> <!-- ??? -->
2443 <array offset="0xe4ca" name="VFD_DEST_CNTL" stride="1" length="32">
2444 <reg32 offset="0x0" name="INSTR">
2445 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2449 <reg32 offset="0xe4f0" name="VFD_POWER_CNTL"/>
2451 <!-- 0x0 for compute, 0x10 for 3d? -->
2452 <reg32 offset="0xe580" name="SP_SP_CNTL"/>
2455 <bitfield name="ENABLED" pos="0" type="boolean"/>
2460 <bitfield name="SSBO_ENABLE" pos="0" type="boolean"/>
2481 <!-- duplicated exactly w/ corresponding HLSQ_ regs starting at 0xe78b.. -->
2482 <reg32 offset="0xe584" name="SP_VS_CONFIG" type="a5xx_xs_config"/>
2483 <reg32 offset="0xe585" name="SP_FS_CONFIG" type="a5xx_xs_config"/>
2484 <reg32 offset="0xe586" name="SP_HS_CONFIG" type="a5xx_xs_config"/>
2485 <reg32 offset="0xe587" name="SP_DS_CONFIG" type="a5xx_xs_config"/>
2486 <reg32 offset="0xe588" name="SP_GS_CONFIG" type="a5xx_xs_config"/>
2487 <reg32 offset="0xe589" name="SP_CS_CONFIG" type="a5xx_xs_config"/>
2488 <reg32 offset="0xe58a" name="SP_VS_CONFIG_MAX_CONST"/>
2489 <reg32 offset="0xe58b" name="SP_FS_CONFIG_MAX_CONST"/>
2490 <reg32 offset="0xe590" name="SP_VS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2491 <reg32 offset="0xe592" name="SP_PRIMITIVE_CNTL">
2493 <bitfield name="VSOUT" low="0" high="4" type="uint"/>
2495 <array offset="0xe593" name="SP_VS_OUT" stride="1" length="16">
2496 <reg32 offset="0x0" name="REG">
2497 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2510 <array offset="0xe5a3" name="SP_VS_VPC_DST" stride="1" length="8">
2511 <reg32 offset="0x0" name="REG">
2512 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2518 <reg32 offset="0xe5ab" name="UNKNOWN_E5AB"/>
2519 <reg32 offset="0xe5ac" name="SP_VS_OBJ_START_LO"/>
2520 <reg32 offset="0xe5ad" name="SP_VS_OBJ_START_HI"/>
2523 <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
2533 <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
2536 <reg32 offset="0xe5ae" name="SP_VS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
2537 <reg64 offset="0xe5af" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32"/>
2538 <reg32 offset="0xe5b1" name="SP_VS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
2539 <reg32 offset="0xe5c0" name="SP_FS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2540 <reg32 offset="0xe5c2" name="UNKNOWN_E5C2"/>
2541 <reg32 offset="0xe5c3" name="SP_FS_OBJ_START_LO"/>
2542 <reg32 offset="0xe5c4" name="SP_FS_OBJ_START_HI"/>
2543 <reg32 offset="0xe5c5" name="SP_FS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
2544 <reg64 offset="0xe5c6" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32"/>
2545 <reg32 offset="0xe5c8" name="SP_FS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
2546 <reg32 offset="0xe5c9" name="SP_BLEND_CNTL">
2548 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2552 <reg32 offset="0xe5ca" name="SP_FS_OUTPUT_CNTL">
2553 <bitfield name="MRT" low="0" high="3" type="uint"/>
2557 <array offset="0xe5cb" name="SP_FS_OUTPUT" stride="1" length="8">
2559 <reg32 offset="0x0" name="REG">
2560 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
2564 <array offset="0xe5d3" name="SP_FS_MRT" stride="1" length="8">
2565 <reg32 offset="0" name="REG">
2566 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2577 <reg32 offset="0xe5db" name="UNKNOWN_E5DB"/>
2578 <reg32 offset="0xe5f0" name="SP_CS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2579 <reg32 offset="0xe5f2" name="UNKNOWN_E5F2"/>
2580 <reg32 offset="0xe5f3" name="SP_CS_OBJ_START_LO"/>
2581 <reg32 offset="0xe5f4" name="SP_CS_OBJ_START_HI"/>
2582 <reg32 offset="0xe5f5" name="SP_CS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
2583 <reg64 offset="0xe5f6" name="SP_CS_PVT_MEM_ADDR" type="waddress" align="32"/>
2584 <reg32 offset="0xe5f8" name="SP_CS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
2588 <reg32 offset="0xe600" name="SP_HS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2589 <reg32 offset="0xe602" name="UNKNOWN_E602"/>
2590 <reg32 offset="0xe603" name="SP_HS_OBJ_START_LO"/>
2591 <reg32 offset="0xe604" name="SP_HS_OBJ_START_HI"/>
2592 <reg32 offset="0xe605" name="SP_HS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
2593 <reg64 offset="0xe606" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32"/>
2594 <reg32 offset="0xe608" name="SP_HS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
2595 <reg32 offset="0xe610" name="SP_DS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2596 <reg32 offset="0xe62b" name="UNKNOWN_E62B"/>
2597 <reg32 offset="0xe62c" name="SP_DS_OBJ_START_LO"/>
2598 <reg32 offset="0xe62d" name="SP_DS_OBJ_START_HI"/>
2599 <reg32 offset="0xe62e" name="SP_DS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
2600 <reg64 offset="0xe62f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32"/>
2601 <reg32 offset="0xe631" name="SP_DS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
2602 <reg32 offset="0xe640" name="SP_GS_CTRL_REG0" type="a5xx_sp_xs_ctrl_reg0"/>
2603 <reg32 offset="0xe65b" name="UNKNOWN_E65B"/>
2604 <reg32 offset="0xe65c" name="SP_GS_OBJ_START_LO"/>
2605 <reg32 offset="0xe65d" name="SP_GS_OBJ_START_HI"/>
2606 <reg32 offset="0xe65e" name="SP_GS_PVT_MEM_PARAM" type="a5xx_sp_xs_pvt_mem_param"/>
2607 <reg64 offset="0xe65f" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32"/>
2608 <reg32 offset="0xe661" name="SP_GS_PVT_MEM_SIZE" type="a5xx_sp_xs_pvt_mem_size"/>
2610 <reg32 offset="0xe704" name="TPL1_TP_RAS_MSAA_CNTL">
2611 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2613 <reg32 offset="0xe705" name="TPL1_TP_DEST_MSAA_CNTL">
2614 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2618 <reg32 offset="0xe706" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_LO"/>
2619 <reg32 offset="0xe707" name="TPL1_TP_BORDER_COLOR_BASE_ADDR_HI"/>
2626 <reg32 offset="0xe700" name="TPL1_VS_TEX_COUNT" type="uint"/>
2627 <reg32 offset="0xe701" name="TPL1_HS_TEX_COUNT" type="uint"/>
2628 <reg32 offset="0xe702" name="TPL1_DS_TEX_COUNT" type="uint"/>
2629 <reg32 offset="0xe703" name="TPL1_GS_TEX_COUNT" type="uint"/>
2631 <reg32 offset="0xe722" name="TPL1_VS_TEX_SAMP_LO"/>
2632 <reg32 offset="0xe723" name="TPL1_VS_TEX_SAMP_HI"/>
2633 <reg32 offset="0xe724" name="TPL1_HS_TEX_SAMP_LO"/>
2634 <reg32 offset="0xe725" name="TPL1_HS_TEX_SAMP_HI"/>
2635 <reg32 offset="0xe726" name="TPL1_DS_TEX_SAMP_LO"/>
2636 <reg32 offset="0xe727" name="TPL1_DS_TEX_SAMP_HI"/>
2637 <reg32 offset="0xe728" name="TPL1_GS_TEX_SAMP_LO"/>
2638 <reg32 offset="0xe729" name="TPL1_GS_TEX_SAMP_HI"/>
2640 <reg32 offset="0xe72a" name="TPL1_VS_TEX_CONST_LO"/>
2641 <reg32 offset="0xe72b" name="TPL1_VS_TEX_CONST_HI"/>
2642 <reg32 offset="0xe72c" name="TPL1_HS_TEX_CONST_LO"/>
2643 <reg32 offset="0xe72d" name="TPL1_HS_TEX_CONST_HI"/>
2644 <reg32 offset="0xe72e" name="TPL1_DS_TEX_CONST_LO"/>
2645 <reg32 offset="0xe72f" name="TPL1_DS_TEX_CONST_HI"/>
2646 <reg32 offset="0xe730" name="TPL1_GS_TEX_CONST_LO"/>
2647 <reg32 offset="0xe731" name="TPL1_GS_TEX_CONST_HI"/>
2649 <reg32 offset="0xe750" name="TPL1_FS_TEX_COUNT" type="uint"/>
2650 <reg32 offset="0xe751" name="TPL1_CS_TEX_COUNT" type="uint"/>
2652 <reg32 offset="0xe75a" name="TPL1_FS_TEX_SAMP_LO"/>
2653 <reg32 offset="0xe75b" name="TPL1_FS_TEX_SAMP_HI"/>
2654 <reg32 offset="0xe75c" name="TPL1_CS_TEX_SAMP_LO"/>
2655 <reg32 offset="0xe75d" name="TPL1_CS_TEX_SAMP_HI"/>
2656 <reg32 offset="0xe75e" name="TPL1_FS_TEX_CONST_LO"/>
2657 <reg32 offset="0xe75f" name="TPL1_FS_TEX_CONST_HI"/>
2658 <reg32 offset="0xe760" name="TPL1_CS_TEX_CONST_LO"/>
2659 <reg32 offset="0xe761" name="TPL1_CS_TEX_CONST_HI"/>
2661 <reg32 offset="0xe764" name="TPL1_TP_FS_ROTATION_CNTL"/>
2663 <reg32 offset="0xe784" name="HLSQ_CONTROL_0_REG">
2665 <bitfield name="FSTHREADSIZE" pos="0" type="a3xx_threadsize"/>
2668 <reg32 offset="0xe785" name="HLSQ_CONTROL_1_REG">
2670 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="5" type="uint"/>
2672 <reg32 offset="0xe786" name="HLSQ_CONTROL_2_REG">
2673 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
2679 <reg32 offset="0xe787" name="HLSQ_CONTROL_3_REG">
2681 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
2686 <reg32 offset="0xe788" name="HLSQ_CONTROL_4_REG">
2687 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
2693 0x020fffff for normal draws, 0x1f00000 for compute.. maybe what state
2697 <reg32 offset="0xe78a" name="HLSQ_UPDATE_CNTL"/>
2698 <reg32 offset="0xe78b" name="HLSQ_VS_CONFIG" type="a5xx_xs_config"/>
2699 <reg32 offset="0xe78c" name="HLSQ_FS_CONFIG" type="a5xx_xs_config"/>
2700 <reg32 offset="0xe78d" name="HLSQ_HS_CONFIG" type="a5xx_xs_config"/>
2701 <reg32 offset="0xe78e" name="HLSQ_DS_CONFIG" type="a5xx_xs_config"/>
2702 <reg32 offset="0xe78f" name="HLSQ_GS_CONFIG" type="a5xx_xs_config"/>
2703 <reg32 offset="0xe790" name="HLSQ_CS_CONFIG" type="a5xx_xs_config"/>
2704 <reg32 offset="0xe791" name="HLSQ_VS_CNTL" type="a5xx_xs_cntl"/>
2705 <reg32 offset="0xe792" name="HLSQ_FS_CNTL" type="a5xx_xs_cntl"/>
2706 <reg32 offset="0xe793" name="HLSQ_HS_CNTL" type="a5xx_xs_cntl"/>
2707 <reg32 offset="0xe794" name="HLSQ_DS_CNTL" type="a5xx_xs_cntl"/>
2708 <reg32 offset="0xe795" name="HLSQ_GS_CNTL" type="a5xx_xs_cntl"/>
2709 <reg32 offset="0xe796" name="HLSQ_CS_CNTL" type="a5xx_xs_cntl"/>
2710 <reg32 offset="0xe7b9" name="HLSQ_CS_KERNEL_GROUP_X"/>
2711 <reg32 offset="0xe7ba" name="HLSQ_CS_KERNEL_GROUP_Y"/>
2712 <reg32 offset="0xe7bb" name="HLSQ_CS_KERNEL_GROUP_Z"/>
2713 <reg32 offset="0xe7b0" name="HLSQ_CS_NDRANGE_0">
2714 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
2720 <reg32 offset="0xe7b1" name="HLSQ_CS_NDRANGE_1">
2721 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
2723 <reg32 offset="0xe7b2" name="HLSQ_CS_NDRANGE_2">
2724 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
2726 <reg32 offset="0xe7b3" name="HLSQ_CS_NDRANGE_3">
2727 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
2729 <reg32 offset="0xe7b4" name="HLSQ_CS_NDRANGE_4">
2730 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
2732 <reg32 offset="0xe7b5" name="HLSQ_CS_NDRANGE_5">
2733 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
2735 <reg32 offset="0xe7b6" name="HLSQ_CS_NDRANGE_6">
2736 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
2738 <reg32 offset="0xe7b7" name="HLSQ_CS_CNTL_0">
2739 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
2752 <reg32 offset="0xe7b8" name="HLSQ_CS_CNTL_1"/>
2753 <reg32 offset="0xe7c0" name="UNKNOWN_E7C0"/>
2754 <reg32 offset="0xe7c3" name="HLSQ_VS_CONSTLEN" type="uint"/>
2755 <reg32 offset="0xe7c4" name="HLSQ_VS_INSTRLEN" type="uint"/>
2756 <reg32 offset="0xe7c5" name="UNKNOWN_E7C5"/>
2757 <reg32 offset="0xe7c8" name="HLSQ_HS_CONSTLEN" type="uint"/>
2758 <reg32 offset="0xe7c9" name="HLSQ_HS_INSTRLEN" type="uint"/>
2759 <reg32 offset="0xe7ca" name="UNKNOWN_E7CA"/>
2760 <reg32 offset="0xe7cd" name="HLSQ_DS_CONSTLEN" type="uint"/>
2761 <reg32 offset="0xe7ce" name="HLSQ_DS_INSTRLEN" type="uint"/>
2762 <reg32 offset="0xe7cf" name="UNKNOWN_E7CF"/>
2763 <reg32 offset="0xe7d2" name="HLSQ_GS_CONSTLEN" type="uint"/>
2764 <reg32 offset="0xe7d3" name="HLSQ_GS_INSTRLEN" type="uint"/>
2765 <reg32 offset="0xe7d4" name="UNKNOWN_E7D4"/>
2766 <reg32 offset="0xe7d7" name="HLSQ_FS_CONSTLEN" type="uint"/>
2767 <reg32 offset="0xe7d8" name="HLSQ_FS_INSTRLEN" type="uint"/>
2768 <reg32 offset="0xe7d9" name="UNKNOWN_E7D9"/>
2769 <reg32 offset="0xe7dc" name="HLSQ_CS_CONSTLEN" type="uint"/>
2770 <reg32 offset="0xe7dd" name="HLSQ_CS_INSTRLEN" type="uint"/>
2775 in render-mode 0x5..
2790 regs 0x2000 to 0x2004 (plus all-zero regs 0x2005-0x2009) look
2793 src via sampler, to enable scaling??) 0x2040 also used in this
2796 <reg32 offset="0x2100" name="RB_2D_BLIT_CNTL"/> <!-- same as 0x2180 -->
2797 <reg32 offset="0x2101" name="RB_2D_SRC_SOLID_DW0"/>
2798 <reg32 offset="0x2102" name="RB_2D_SRC_SOLID_DW1"/>
2799 <reg32 offset="0x2103" name="RB_2D_SRC_SOLID_DW2"/>
2800 <reg32 offset="0x2104" name="RB_2D_SRC_SOLID_DW3"/>
2803 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a5xx_color_fmt"/>
2811 <reg32 offset="0x2107" name="RB_2D_SRC_INFO" type="a5xx_2d_surf_info"/>
2812 <reg32 offset="0x2108" name="RB_2D_SRC_LO"/>
2813 <reg32 offset="0x2109" name="RB_2D_SRC_HI"/>
2814 <reg32 offset="0x210a" name="RB_2D_SRC_SIZE">
2815 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2819 <reg32 offset="0x2110" name="RB_2D_DST_INFO" type="a5xx_2d_surf_info"/>
2820 <reg32 offset="0x2111" name="RB_2D_DST_LO"/>
2821 <reg32 offset="0x2112" name="RB_2D_DST_HI"/>
2822 <reg32 offset="0x2113" name="RB_2D_DST_SIZE">
2823 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2826 <reg32 offset="0x2140" name="RB_2D_SRC_FLAGS_LO"/>
2827 <reg32 offset="0x2141" name="RB_2D_SRC_FLAGS_HI"/>
2828 <reg32 offset="0x2142" name="RB_2D_SRC_FLAGS_PITCH" shr="6" type="uint"/>
2829 <reg32 offset="0x2143" name="RB_2D_DST_FLAGS_LO"/>
2830 <reg32 offset="0x2144" name="RB_2D_DST_FLAGS_HI"/>
2831 <reg32 offset="0x2145" name="RB_2D_DST_FLAGS_PITCH" shr="6" type="uint"/>
2832 <reg32 offset="0x2180" name="GRAS_2D_BLIT_CNTL"/> <!-- same as 0x2100 -->
2833 <!-- looks same as 0x2107: -->
2834 <reg32 offset="0x2181" name="GRAS_2D_SRC_INFO" type="a5xx_2d_surf_info"/>
2835 <!-- looks same as 0x2110: -->
2836 <reg32 offset="0x2182" name="GRAS_2D_DST_INFO" type="a5xx_2d_surf_info"/>
2838 0x2100 and 0x2180 look like same thing (RB and GRAS versions)..
2839 0x86000000 for copy, 0x00000000 for fill?
2841 0x2184 0x9 for copy, 0x1 for blit (maybe bitmask of enabled src/dst???)
2843 <reg32 offset="0x2184" name="UNKNOWN_2184"/>
2849 <value name="A5XX_TEX_NEAREST" value="0"/>
2854 <value name="A5XX_TEX_REPEAT" value="0"/>
2861 <value name="A5XX_TEX_ANISO_1" value="0"/>
2867 <reg32 offset="0" name="0">
2868 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
2887 offset into border-color buffer? Blob always uses 0x80 for FS state
2889 Seems like when both VS and FS have bcolor, one starts 0x300 after other..
2890 and 0x80 in TEX_SAMP.2 .. blob doesn't seem to be able to cope w/ multiple
2909 <value name="A5XX_TEX_X" value="0"/>
2917 <value name="A5XX_TEX_1D" value="0"/>
2923 <reg32 offset="0" name="0">
2924 <bitfield name="TILE_MODE" low="0" high="1" type="a5xx_tile_mode"/>
2936 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
2949 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
2961 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
2975 <bitfield name="BASE_HI" low="0" high="16"/>
2992 <reg32 offset="0" name="0">
2998 <bitfield name="PITCH" low="0" high="21" type="uint"/>
3005 <bitfield name="CPP" low="0" high="5" type="uint"/>
3010 <reg32 offset="0" name="0">
3015 <bitfield name="HEIGHT" low="0" high="15" type="uint"/>
3021 <reg32 offset="0" name="0">
3022 <bitfield name="BASE_LO" low="0" high="31"/>
3025 <bitfield name="BASE_HI" low="0" high="31"/>
3030 <reg32 offset="0" name="0">
3031 <bitfield name="BASE_LO" low="0" high="31"/>
3034 <bitfield name="BASE_HI" low="0" high="16"/>