35 /* first irq byte normally 0x08 */
36 /* second irq byte base 0x7d + below */
37 /* third irq byte base 0x94 + below */
38 /* fourth irq byte normally 0xee */
41 #define CH341_MULT_STAT 0x04 /* multiple status since last interrupt event */
45 #define CH341_BIT_CTS 0x01
46 #define CH341_BIT_DSR 0x02
47 #define CH341_BIT_RI  0x04
48 #define CH341_BIT_DCD 0x08
49 #define CH341_BITS_MODEM_STAT 0x0f /* all bits */
55 #define CH341_REQ_READ_VERSION 0x5F
56 #define CH341_REQ_WRITE_REG    0x9A
57 #define CH341_REQ_READ_REG     0x95
58 #define CH341_REQ_SERIAL_INIT  0xA1
59 #define CH341_REQ_MODEM_CTRL   0xA4
61 #define CH341_REG_BREAK        0x05
62 #define CH341_REG_PRESCALER    0x12
63 #define CH341_REG_DIVISOR      0x13
64 #define CH341_REG_LCR          0x18
65 #define CH341_REG_LCR2         0x25
67 #define CH341_NBREAK_BITS      0x01
69 #define CH341_LCR_ENABLE_RX    0x80
70 #define CH341_LCR_ENABLE_TX    0x40
71 #define CH341_LCR_MARK_SPACE   0x20
72 #define CH341_LCR_PAR_EVEN     0x10
73 #define CH341_LCR_ENABLE_PAR   0x08
74 #define CH341_LCR_STOP_BITS_2  0x04
75 #define CH341_LCR_CS8          0x03
76 #define CH341_LCR_CS7          0x02
77 #define CH341_LCR_CS6          0x01
78 #define CH341_LCR_CS5          0x00
80 #define CH341_QUIRK_LIMITED_PRESCALER	BIT(0)
84 	{ USB_DEVICE(0x1a86, 0x5523) },
85 	{ USB_DEVICE(0x1a86, 0x7522) },
86 	{ USB_DEVICE(0x1a86, 0x7523) },
87 	{ USB_DEVICE(0x2184, 0x0057) },
88 	{ USB_DEVICE(0x4348, 0x5523) },
89 	{ USB_DEVICE(0x9986, 0x7523) },
119 	r = usb_control_msg(dev, usb_sndctrlpipe(dev, 0), request,  in ch341_control_out()
121 			    value, index, NULL, 0, DEFAULT_TIMEOUT);  in ch341_control_out()
122 	if (r < 0)  in ch341_control_out()
137 	r = usb_control_msg_recv(dev, 0, request,  in ch341_control_in()
147 	return 0;  in ch341_control_in()
155 	CH341_MIN_RATE(0),
162 #define CH341_MIN_BPS	DIV_ROUND_UP(CH341_CLKRATE, CH341_CLK_DIV(0, 0) * 256)
163 #define CH341_MAX_BPS	(CH341_CLKRATE / (CH341_CLK_DIV(3, 0) * 2))
170  *		0 <= ps <= 3,
171  *		0 <= fact <= 1,
172  *		2 <= div <= 256 if fact = 0, or
182 	 * Clamp to supported range, this makes the (ps < 0) and (div < 2)  in ch341_get_divisor()
192 	for (ps = 3; ps >= 0; ps--) {  in ch341_get_divisor()
197 	if (ps < 0)  in ch341_get_divisor()
208 	/* Halve base clock (fact = 0) if required. */  in ch341_get_divisor()
212 		fact = 0;  in ch341_get_divisor()
227 	 * Prefer lower base clock (fact = 0) if even divisor.  in ch341_get_divisor()
231 	if (fact == 1 && div % 2 == 0) {  in ch341_get_divisor()
233 		fact = 0;  in ch341_get_divisor()
236 	return (0x100 - div) << 8 | fact << 2 | ps;  in ch341_get_divisor()
250 	if (val < 0)  in ch341_set_baudrate_lcr()
257 	 * At least one device with version 0x27 appears to have this bit  in ch341_set_baudrate_lcr()
260 	if (priv->version > 0x27)  in ch341_set_baudrate_lcr()
270 	 * Chip versions before version 0x30 as read using  in ch341_set_baudrate_lcr()
272 	 * (stop bits, parity and word length). Version 0x30 and above use  in ch341_set_baudrate_lcr()
275 	if (priv->version < 0x30)  in ch341_set_baudrate_lcr()
276 		return 0;  in ch341_set_baudrate_lcr()
288 	return ch341_control_out(dev, CH341_REQ_MODEM_CTRL, ~control, 0);  in ch341_set_handshake()
298 	r = ch341_control_in(dev, CH341_REQ_READ_REG, 0x0706, 0, buffer, size);  in ch341_get_status()
306 	return 0;  in ch341_get_status()
317 	/* expect two bytes 0x27 0x00 */  in ch341_configure()
318 	r = ch341_control_in(dev, CH341_REQ_READ_VERSION, 0, 0, buffer, size);  in ch341_configure()
322 	priv->version = buffer[0];  in ch341_configure()
323 	dev_dbg(&dev->dev, "Chip version: 0x%02x\n", priv->version);  in ch341_configure()
325 	r = ch341_control_out(dev, CH341_REQ_SERIAL_INIT, 0, 0);  in ch341_configure()
326 	if (r < 0)  in ch341_configure()
330 	if (r < 0)  in ch341_configure()
334 	if (r < 0)  in ch341_configure()
337 	return 0;  in ch341_configure()
345 	unsigned long quirks = 0;  in ch341_detect_quirks()
355 	r = usb_control_msg_recv(udev, 0, CH341_REQ_READ_REG,  in ch341_detect_quirks()
357 				 CH341_REG_BREAK, 0, &buffer, size,  in ch341_detect_quirks()
362 		r = 0;  in ch341_detect_quirks()
368 		dev_dbg(&port->dev, "enabling quirk flags: 0x%02lx\n", quirks);  in ch341_detect_quirks()
393 	if (r < 0)  in ch341_port_probe()
399 	if (r < 0)  in ch341_port_probe()
402 	return 0;  in ch341_port_probe()
421 	return 0;  in ch341_carrier_raised()
464 	if (r < 0) {  in ch341_open()
473 	return 0;  in ch341_open()
519 		if (C_PARODD(tty) == 0)  in ch341_set_termios()
533 		if (r < 0 && old_termios) {  in ch341_set_termios()
536 		} else if (r == 0) {  in ch341_set_termios()
572 	if (break_state != 0) {  in ch341_simulate_break()
578 		if (r < 0) {  in ch341_simulate_break()
585 		r = tty_put_char(tty, '\0');  in ch341_simulate_break()
586 		if (r < 0) {  in ch341_simulate_break()
602 		return 0;  in ch341_simulate_break()
618 	r = 0;  in ch341_simulate_break()
623 	if (r2 < 0) {  in ch341_simulate_break()
647 			ch341_break_reg, 0, break_reg, 2);  in ch341_break_ctl()
651 		if (r > 0)  in ch341_break_ctl()
656 		__func__, break_reg[0], break_reg[1]);  in ch341_break_ctl()
657 	if (break_state != 0) {  in ch341_break_ctl()
659 		break_reg[0] &= ~CH341_NBREAK_BITS;  in ch341_break_ctl()
663 		break_reg[0] |= CH341_NBREAK_BITS;  in ch341_break_ctl()
667 		__func__, break_reg[0], break_reg[1]);  in ch341_break_ctl()
671 	if (r < 0) {  in ch341_break_ctl()
677 	return 0;  in ch341_break_ctl()
755 	case 0:  in ch341_read_int_callback()
795 	result = ((mcr & CH341_BIT_DTR)		? TIOCM_DTR : 0)  in ch341_tiocmget()
796 		  | ((mcr & CH341_BIT_RTS)	? TIOCM_RTS : 0)  in ch341_tiocmget()
797 		  | ((status & CH341_BIT_CTS)	? TIOCM_CTS : 0)  in ch341_tiocmget()
798 		  | ((status & CH341_BIT_DSR)	? TIOCM_DSR : 0)  in ch341_tiocmget()
799 		  | ((status & CH341_BIT_RI)	? TIOCM_RI  : 0)  in ch341_tiocmget()
800 		  | ((status & CH341_BIT_DCD)	? TIOCM_CD  : 0);  in ch341_tiocmget()
809 	struct usb_serial_port *port = serial->port[0];  in ch341_reset_resume()
815 		return 0;  in ch341_reset_resume()
829 		if (ret < 0) {  in ch341_reset_resume()