Lines Matching +full:0 +full:x2184
36 .offset = 0x0,
51 { P_BI_TCXO, 0 },
63 { P_BI_TCXO, 0 },
75 { P_BI_TCXO, 0 },
83 { P_BI_TCXO, 0 },
97 { P_BI_TCXO, 0 },
110 .cmd_rcgr = 0x20d0,
111 .mnd_width = 0,
125 .cmd_rcgr = 0x20ec,
126 .mnd_width = 0,
139 F(19200000, P_BI_TCXO, 1, 0, 0),
144 .cmd_rcgr = 0x219c,
145 .mnd_width = 0,
159 .cmd_rcgr = 0x2154,
160 .mnd_width = 0,
172 .cmd_rcgr = 0x2138,
173 .mnd_width = 0,
186 .cmd_rcgr = 0x2184,
200 .cmd_rcgr = 0x216c,
214 F(19200000, P_BI_TCXO, 1, 0, 0),
219 .cmd_rcgr = 0x2108,
220 .mnd_width = 0,
233 .cmd_rcgr = 0x2120,
234 .mnd_width = 0,
247 F(19200000, P_BI_TCXO, 1, 0, 0),
248 F(85714286, P_GPLL0_OUT_MAIN, 7, 0, 0),
249 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
250 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
251 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
252 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
253 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
254 F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
255 F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
260 .cmd_rcgr = 0x2088,
261 .mnd_width = 0,
275 .cmd_rcgr = 0x2058,
290 .cmd_rcgr = 0x2070,
304 F(19200000, P_BI_TCXO, 1, 0, 0),
305 F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
306 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
307 F(344000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
308 F(430000000, P_DISP_CC_PLL0_OUT_MAIN, 2, 0, 0),
313 .cmd_rcgr = 0x20a0,
314 .mnd_width = 0,
327 .cmd_rcgr = 0x20b8,
328 .mnd_width = 0,
341 .halt_reg = 0x4004,
344 .enable_reg = 0x4004,
345 .enable_mask = BIT(0),
354 .halt_reg = 0x4008,
357 .enable_reg = 0x4008,
358 .enable_mask = BIT(0),
368 .halt_reg = 0x2028,
371 .enable_reg = 0x2028,
372 .enable_mask = BIT(0),
387 .reg = 0x20e8,
388 .shift = 0,
404 .halt_reg = 0x202c,
407 .enable_reg = 0x202c,
408 .enable_mask = BIT(0),
423 .halt_reg = 0x2030,
426 .enable_reg = 0x2030,
427 .enable_mask = BIT(0),
442 .reg = 0x2104,
443 .shift = 0,
459 .halt_reg = 0x2034,
462 .enable_reg = 0x2034,
463 .enable_mask = BIT(0),
477 .halt_reg = 0x2054,
480 .enable_reg = 0x2054,
481 .enable_mask = BIT(0),
495 .halt_reg = 0x2048,
498 .enable_reg = 0x2048,
499 .enable_mask = BIT(0),
513 .halt_reg = 0x2040,
516 .enable_reg = 0x2040,
517 .enable_mask = BIT(0),
530 /* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */
532 .halt_reg = 0x2044,
535 .enable_reg = 0x2044,
536 .enable_mask = BIT(0),
549 .halt_reg = 0x2050,
552 .enable_reg = 0x2050,
553 .enable_mask = BIT(0),
567 .halt_reg = 0x204c,
570 .enable_reg = 0x204c,
571 .enable_mask = BIT(0),
585 .halt_reg = 0x2038,
588 .enable_reg = 0x2038,
589 .enable_mask = BIT(0),
603 .halt_reg = 0x203c,
606 .enable_reg = 0x203c,
607 .enable_mask = BIT(0),
621 .halt_reg = 0x200c,
624 .enable_reg = 0x200c,
625 .enable_mask = BIT(0),
639 .halt_reg = 0x201c,
642 .enable_reg = 0x201c,
643 .enable_mask = BIT(0),
657 .halt_reg = 0x2004,
660 .enable_reg = 0x2004,
661 .enable_mask = BIT(0),
676 .halt_reg = 0x2008,
679 .enable_reg = 0x2008,
680 .enable_mask = BIT(0),
694 .halt_reg = 0x2014,
697 .enable_reg = 0x2014,
698 .enable_mask = BIT(0),
712 .halt_reg = 0x5004,
715 .enable_reg = 0x5004,
716 .enable_mask = BIT(0),
725 .halt_reg = 0x5008,
728 .enable_reg = 0x5008,
729 .enable_mask = BIT(0),
743 .halt_reg = 0x2024,
746 .enable_reg = 0x2024,
747 .enable_mask = BIT(0),
761 .gdscr = 0x3000,
762 .en_few_wait_val = 0x6,
763 .en_rest_wait_val = 0x5,
818 [DISP_CC_MDSS_RSCC_BCR] = { 0x5000 },
829 .max_register = 0x10000,
858 disp_cc_pll0_config.l = 0x2c; in disp_cc_sdm845_probe()
859 disp_cc_pll0_config.alpha = 0xcaaa; in disp_cc_sdm845_probe()
864 regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0); in disp_cc_sdm845_probe()