Lines Matching +full:0 +full:x2184
11 <value name="DITHER_PIXEL" value="0"/>
16 <value name="COLORX_4_4_4_4" value="0"/>
34 <value name="FMT_1_REVERSE" value="0"/>
91 <value name="POSITION_1_VECTOR" value="0"/>
102 <value name="CENTROIDS_ONLY" value="0"/>
108 <value name="DXCLIP_OPENGL" value="0"/>
113 <value name="POLY_DISABLED" value="0"/>
118 <value name="EDRAM_NOP" value="0"/>
125 <value name="LITTLE" value="0"/>
130 <value name="NEVER" value="0"/>
136 <value name="PIXCENTER_D3D" value="0"/>
141 <value name="TRUNCATE" value="0"/>
148 <value name="ONE_SIXTEENTH" value="0"/>
156 <value name="SAMPLE_0" value="0"/>
166 <value name="BLEND2_DST_PLUS_SRC" value="0"/>
175 <value value="0" name="PERF_PAPC_PASX_REQ"/>
276 <value value="0" name="SC_SR_WINDOW_VALID"/>
297 <value value="0" name="VGT_SQ_EVENT_WINDOW_ACTIVE"/>
349 <value value="0" name="DGMMPD_IPMUX0_STALL"/>
355 <value value="0" name="POINT_QUADS"/>
397 <value value="0" name="QUAD0_RD_LAT_FIFO_EMPTY"/>
412 <value value="0" name="VALID_CYCLES"/>
552 <value value="0" name="SQ_PIXEL_VECTORS_SUB"/>
710 <value value="0" name="SX_EXPORT_VECTORS"/>
720 <value value="0" name="RBBM1_COUNT"/>
739 <value value="0" name="ALWAYS_COUNT"/>
778 <value value="0" name="RBPERF_CNTX_BUSY"/>
838 <value value="0" name="CP_R0_REQUESTS"/>
1023 <value name="PERF_STATE_RESET" value="0"/>
1031 <bitfield name="COLUMN" low="0" high="2" type="uint"/>
1036 <reg32 offset="0x0001" name="RBBM_PATCH_RELEASE"/>
1037 <reg32 offset="0x003b" name="RBBM_CNTL"/>
1038 <reg32 offset="0x003c" name="RBBM_SOFT_RESET"/>
1039 <reg32 offset="0x00c0" name="CP_PFP_UCODE_ADDR"/>
1040 <reg32 offset="0x00c1" name="CP_PFP_UCODE_DATA"/>
1043 <value name="BEH_NEVR" value="0"/>
1051 it doesn't make sense, so I think offset 0x40 must be a different
1054 <reg32 offset="0x0040" name="MH_MMU_CONFIG">
1055 <bitfield name="MMU_ENABLE" pos="0" type="boolean"/>
1069 <reg32 offset="0x0041" name="MH_MMU_VA_RANGE">
1070 <bitfield name="NUM_64KB_REGIONS" low="0" high="11" type="uint"/>
1073 <reg32 offset="0x0042" name="MH_MMU_PT_BASE"/>
1074 <reg32 offset="0x0043" name="MH_MMU_PAGE_FAULT"/>
1075 <reg32 offset="0x0044" name="MH_MMU_TRAN_ERROR"/>
1076 <reg32 offset="0x0045" name="MH_MMU_INVALIDATE">
1077 <bitfield name="INVALIDATE_ALL" pos="0" type="boolean"/>
1080 <reg32 offset="0x0046" name="MH_MMU_MPU_BASE"/>
1081 <reg32 offset="0x0047" name="MH_MMU_MPU_END"/>
1083 <reg32 offset="0x0394" name="NQWAIT_UNTIL"/>
1084 <reg32 offset="0x0395" name="RBBM_PERFCOUNTER0_SELECT"/>
1085 <reg32 offset="0x0396" name="RBBM_PERFCOUNTER1_SELECT"/>
1086 <reg32 offset="0x0397" name="RBBM_PERFCOUNTER0_LO"/>
1087 <reg32 offset="0x0398" name="RBBM_PERFCOUNTER0_HI"/>
1088 <reg32 offset="0x0399" name="RBBM_PERFCOUNTER1_LO"/>
1089 <reg32 offset="0x039a" name="RBBM_PERFCOUNTER1_HI"/>
1090 <reg32 offset="0x039b" name="RBBM_DEBUG"/>
1091 <reg32 offset="0x039c" name="RBBM_PM_OVERRIDE1">
1092 <bitfield name="RBBM_AHBCLK_PM_OVERRIDE" pos="0" type="boolean"/>
1125 <reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2">
1126 <bitfield name="PA_REG_SCLK_PM_OVERRIDE" pos="0" type="boolean"/>
1139 <reg32 offset="0x03a0" name="RBBM_DEBUG_OUT"/>
1140 <reg32 offset="0x03a1" name="RBBM_DEBUG_CNTL"/>
1141 <reg32 offset="0x03b3" name="RBBM_READ_ERROR"/>
1142 <reg32 offset="0x03b4" name="RBBM_INT_CNTL">
1143 <bitfield name="RDERR_INT_MASK" pos="0" type="boolean"/>
1147 <reg32 offset="0x03b5" name="RBBM_INT_STATUS"/>
1148 <reg32 offset="0x03b6" name="RBBM_INT_ACK"/>
1149 <reg32 offset="0x03b7" name="MASTER_INT_SIGNAL">
1155 <reg32 offset="0x03f9" name="RBBM_PERIPHID1"/>
1156 <reg32 offset="0x03fa" name="RBBM_PERIPHID2"/>
1157 <reg32 offset="0x0444" name="CP_PERFMON_CNTL">
1159 <bitfield name="PERF_MODE_CNT" low="0" high="2" type="perf_mode_cnt"/>
1161 <reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/>
1162 <reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/>
1163 <reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/>
1164 <reg32 offset="0x05d0" name="RBBM_STATUS">
1165 <bitfield name="CMDFIFO_AVAIL" low="0" high="4" type="uint"/>
1186 <reg32 offset="0x0a40" name="MH_ARBITER_CONFIG">
1187 <bitfield name="SAME_PAGE_LIMIT" low="0" high="5" type="uint"/>
1203 <reg32 offset="0x0a42" name="MH_INTERRUPT_MASK">
1204 <bitfield name="AXI_READ_ERROR" pos="0" type="boolean"/>
1208 <reg32 offset="0x0a43" name="MH_INTERRUPT_STATUS"/>
1209 <reg32 offset="0x0a44" name="MH_INTERRUPT_CLEAR"/>
1210 <reg32 offset="0x0a54" name="MH_CLNT_INTF_CTRL_CONFIG1"/>
1211 <reg32 offset="0x0a55" name="MH_CLNT_INTF_CTRL_CONFIG2"/>
1212 <reg32 offset="0x0c01" name="A220_VSC_BIN_SIZE">
1213 <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
1216 <array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
1217 <reg32 offset="0x0" name="CONFIG"/>
1218 <reg32 offset="0x1" name="DATA_ADDRESS"/>
1219 <reg32 offset="0x2" name="DATA_LENGTH"/>
1221 <reg32 offset="0x0c38" name="PC_DEBUG_CNTL"/>
1222 <reg32 offset="0x0c39" name="PC_DEBUG_DATA"/>
1223 <reg32 offset="0x0c44" name="PA_SC_VIZ_QUERY_STATUS"/>
1224 <reg32 offset="0x0c80" name="GRAS_DEBUG_CNTL"/>
1225 <reg32 offset="0x0c80" name="PA_SU_DEBUG_CNTL"/>
1226 <reg32 offset="0x0c81" name="GRAS_DEBUG_DATA"/>
1227 <reg32 offset="0x0c81" name="PA_SU_DEBUG_DATA"/>
1228 <reg32 offset="0x0c86" name="PA_SU_FACE_DATA">
1231 <reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT">
1232 <bitfield name="REG_DYNAMIC" pos="0" type="boolean"/>
1236 <reg32 offset="0x0d01" name="SQ_FLOW_CONTROL"/>
1237 <reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT">
1238 <bitfield name="INST_BASE_PIX" low="0" high="11" type="uint"/>
1241 <reg32 offset="0x0d05" name="SQ_DEBUG_MISC"/>
1242 <reg32 offset="0x0d34" name="SQ_INT_CNTL"/>
1243 <reg32 offset="0x0d35" name="SQ_INT_STATUS"/>
1244 <reg32 offset="0x0d36" name="SQ_INT_ACK"/>
1245 <reg32 offset="0x0dae" name="SQ_DEBUG_INPUT_FSM"/>
1246 <reg32 offset="0x0daf" name="SQ_DEBUG_CONST_MGR_FSM"/>
1247 <reg32 offset="0x0db0" name="SQ_DEBUG_TP_FSM"/>
1248 <reg32 offset="0x0db1" name="SQ_DEBUG_FSM_ALU_0"/>
1249 <reg32 offset="0x0db2" name="SQ_DEBUG_FSM_ALU_1"/>
1250 <reg32 offset="0x0db3" name="SQ_DEBUG_EXP_ALLOC"/>
1251 <reg32 offset="0x0db4" name="SQ_DEBUG_PTR_BUFF"/>
1252 <reg32 offset="0x0db5" name="SQ_DEBUG_GPR_VTX"/>
1253 <reg32 offset="0x0db6" name="SQ_DEBUG_GPR_PIX"/>
1254 <reg32 offset="0x0db7" name="SQ_DEBUG_TB_STATUS_SEL"/>
1255 <reg32 offset="0x0db8" name="SQ_DEBUG_VTX_TB_0"/>
1256 <reg32 offset="0x0db9" name="SQ_DEBUG_VTX_TB_1"/>
1257 <reg32 offset="0x0dba" name="SQ_DEBUG_VTX_TB_STATUS_REG"/>
1258 <reg32 offset="0x0dbb" name="SQ_DEBUG_VTX_TB_STATE_MEM"/>
1259 <reg32 offset="0x0dbc" name="SQ_DEBUG_PIX_TB_0"/>
1260 <reg32 offset="0x0dbd" name="SQ_DEBUG_PIX_TB_STATUS_REG_0"/>
1261 <reg32 offset="0x0dbe" name="SQ_DEBUG_PIX_TB_STATUS_REG_1"/>
1262 <reg32 offset="0x0dbf" name="SQ_DEBUG_PIX_TB_STATUS_REG_2"/>
1263 <reg32 offset="0x0dc0" name="SQ_DEBUG_PIX_TB_STATUS_REG_3"/>
1264 <reg32 offset="0x0dc1" name="SQ_DEBUG_PIX_TB_STATE_MEM"/>
1265 <reg32 offset="0x0e00" name="TC_CNTL_STATUS">
1266 <bitfield name="L2_INVALIDATE" pos="0" type="boolean"/>
1268 <reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
1269 <reg32 offset="0x0f01" name="RB_BC_CONTROL">
1270 <bitfield name="ACCUM_LINEAR_MODE_ENABLE" pos="0" type="boolean"/>
1290 <reg32 offset="0x0f02" name="RB_EDRAM_INFO"/>
1291 <reg32 offset="0x0f26" name="RB_DEBUG_CNTL"/>
1292 <reg32 offset="0x0f27" name="RB_DEBUG_DATA"/>
1293 <reg32 offset="0x2000" name="RB_SURFACE_INFO">
1294 <bitfield name="SURFACE_PITCH" low="0" high="13" type="uint"/>
1297 <reg32 offset="0x2001" name="RB_COLOR_INFO">
1298 <bitfield name="FORMAT" low="0" high="3" type="a2xx_colorformatx"/>
1305 <reg32 offset="0x2002" name="RB_DEPTH_INFO">
1306 <bitfield name="DEPTH_FORMAT" pos="0" type="adreno_rb_depth_format"/>
1309 <reg32 offset="0x2005" name="A225_RB_COLOR_INFO3"/>
1310 <reg32 offset="0x2006" name="COHER_DEST_BASE_0"/>
1311 <reg32 offset="0x200e" name="PA_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
1312 <reg32 offset="0x200f" name="PA_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
1313 <reg32 offset="0x2080" name="PA_SC_WINDOW_OFFSET">
1314 <bitfield name="X" low="0" high="14" type="int"/>
1318 <reg32 offset="0x2081" name="PA_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1319 <reg32 offset="0x2082" name="PA_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1320 <reg32 offset="0x2010" name="UNKNOWN_2010"/>
1321 <reg32 offset="0x2100" name="VGT_MAX_VTX_INDX"/>
1322 <reg32 offset="0x2101" name="VGT_MIN_VTX_INDX"/>
1323 <reg32 offset="0x2102" name="VGT_INDX_OFFSET"/>
1324 <reg32 offset="0x2103" name="A225_PC_MULTI_PRIM_IB_RESET_INDX"/>
1325 <reg32 offset="0x2104" name="RB_COLOR_MASK">
1326 <bitfield name="WRITE_RED" pos="0" type="boolean"/>
1331 <reg32 offset="0x2105" name="RB_BLEND_RED"/>
1332 <reg32 offset="0x2106" name="RB_BLEND_GREEN"/>
1333 <reg32 offset="0x2107" name="RB_BLEND_BLUE"/>
1334 <reg32 offset="0x2108" name="RB_BLEND_ALPHA"/>
1335 <reg32 offset="0x2109" name="RB_FOG_COLOR">
1336 <bitfield name="FOG_RED" low="0" high="7" type="uint"/>
1340 <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
1341 <reg32 offset="0x210d" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
1342 <reg32 offset="0x210e" name="RB_ALPHA_REF"/>
1343 <reg32 offset="0x210f" name="PA_CL_VPORT_XSCALE" type="float"/>
1344 <reg32 offset="0x2110" name="PA_CL_VPORT_XOFFSET" type="float"/>
1345 <reg32 offset="0x2111" name="PA_CL_VPORT_YSCALE" type="float"/>
1346 <reg32 offset="0x2112" name="PA_CL_VPORT_YOFFSET" type="float"/>
1347 <reg32 offset="0x2113" name="PA_CL_VPORT_ZSCALE" type="float"/>
1348 <reg32 offset="0x2114" name="PA_CL_VPORT_ZOFFSET" type="float"/>
1349 <reg32 offset="0x2180" name="SQ_PROGRAM_CNTL">
1351 note: only 0x3f worth of valid register values for VS_REGS and
1352 PS_REGS, but high bit is set to indicate '0 registers used':
1354 <bitfield name="VS_REGS" low="0" high="7" type="uint"/>
1365 <reg32 offset="0x2181" name="SQ_CONTEXT_MISC">
1366 <bitfield name="INST_PRED_OPTIMIZE" pos="0" type="boolean"/>
1374 <reg32 offset="0x2182" name="SQ_INTERPOLATOR_CNTL">
1375 <bitfield name="PARAM_SHADE" low="0" high="15" type="uint"/>
1378 <reg32 offset="0x2183" name="SQ_WRAPPING_0">
1379 <bitfield name="PARAM_WRAP_0" low="0" high="3" type="uint"/>
1388 <reg32 offset="0x2184" name="SQ_WRAPPING_1">
1389 <bitfield name="PARAM_WRAP_8" low="0" high="3" type="uint"/>
1398 <reg32 offset="0x21f6" name="SQ_PS_PROGRAM">
1399 <bitfield name="BASE" low="0" high="11" type="uint"/>
1402 <reg32 offset="0x21f7" name="SQ_VS_PROGRAM">
1403 <bitfield name="BASE" low="0" high="11" type="uint"/>
1406 <reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
1407 <reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
1408 <reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
1409 <reg32 offset="0x2200" name="RB_DEPTHCONTROL">
1410 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
1425 <reg32 offset="0x2201" name="RB_BLEND_CONTROL">
1426 <bitfield name="COLOR_SRCBLEND" low="0" high="4" type="adreno_rb_blend_factor"/>
1435 <reg32 offset="0x2202" name="RB_COLORCONTROL">
1436 <bitfield name="ALPHA_FUNC" low="0" high="2" type="adreno_compare_func"/>
1451 <reg32 offset="0x2203" name="VGT_CURRENT_BIN_ID_MAX" type="a2xx_vgt_current_bin_id_min_max"/>
1452 <reg32 offset="0x2204" name="PA_CL_CLIP_CNTL">
1462 <reg32 offset="0x2205" name="PA_SU_SC_MODE_CNTL">
1463 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1486 <reg32 offset="0x2206" name="PA_CL_VTE_CNTL">
1487 <bitfield name="VPORT_X_SCALE_ENA" pos="0" type="boolean"/>
1498 <reg32 offset="0x2207" name="VGT_CURRENT_BIN_ID_MIN" type="a2xx_vgt_current_bin_id_min_max"/>
1499 <reg32 offset="0x2208" name="RB_MODECONTROL">
1500 <bitfield name="EDRAM_MODE" low="0" high="2" type="a2xx_rb_edram_mode"/>
1502 <reg32 offset="0x2209" name="A220_RB_LRZ_VSC_CONTROL"/>
1503 <reg32 offset="0x220a" name="RB_SAMPLE_POS"/>
1504 <reg32 offset="0x220b" name="CLEAR_COLOR">
1505 <bitfield name="RED" low="0" high="7"/>
1510 <reg32 offset="0x2210" name="A220_GRAS_CONTROL"/>
1511 <reg32 offset="0x2280" name="PA_SU_POINT_SIZE">
1512 <bitfield name="HEIGHT" low="0" high="15" type="ufixed" radix="4"/>
1515 <reg32 offset="0x2281" name="PA_SU_POINT_MINMAX">
1516 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1519 <reg32 offset="0x2282" name="PA_SU_LINE_CNTL">
1520 <bitfield name="WIDTH" low="0" high="15" type="ufixed" radix="4"/>
1522 <reg32 offset="0x2283" name="PA_SC_LINE_STIPPLE">
1523 <bitfield name="LINE_PATTERN" low="0" high="15" type="hex"/>
1528 <reg32 offset="0x2293" name="PA_SC_VIZ_QUERY">
1529 <bitfield name="VIZ_QUERY_ENA" pos="0" type="boolean"/>
1533 <reg32 offset="0x2294" name="VGT_ENHANCE"/>
1534 <reg32 offset="0x2300" name="PA_SC_LINE_CNTL">
1535 <bitfield name="BRES_CNTL" low="0" high="15" type="uint"/>
1540 <reg32 offset="0x2301" name="PA_SC_AA_CONFIG">
1541 <bitfield name="MSAA_NUM_SAMPLES" low="0" high="2" type="uint"/>
1544 <reg32 offset="0x2302" name="PA_SU_VTX_CNTL">
1545 <bitfield name="PIX_CENTER" pos="0" type="a2xx_pa_pixcenter"/>
1549 <reg32 offset="0x2303" name="PA_CL_GB_VERT_CLIP_ADJ" type="float"/>
1550 <reg32 offset="0x2304" name="PA_CL_GB_VERT_DISC_ADJ" type="float"/>
1551 <reg32 offset="0x2305" name="PA_CL_GB_HORZ_CLIP_ADJ" type="float"/>
1552 <reg32 offset="0x2306" name="PA_CL_GB_HORZ_DISC_ADJ" type="float"/>
1553 <reg32 offset="0x2307" name="SQ_VS_CONST">
1554 <bitfield name="BASE" low="0" high="8" type="uint"/>
1557 <reg32 offset="0x2308" name="SQ_PS_CONST">
1558 <bitfield name="BASE" low="0" high="8" type="uint"/>
1561 <reg32 offset="0x2309" name="SQ_DEBUG_MISC_0"/>
1562 <reg32 offset="0x230a" name="SQ_DEBUG_MISC_1"/>
1563 <reg32 offset="0x2312" name="PA_SC_AA_MASK"/>
1564 <reg32 offset="0x2316" name="VGT_VERTEX_REUSE_BLOCK_CNTL">
1565 <bitfield name="VTX_REUSE_DEPTH" low="0" high="2" type="uint"/>
1567 <reg32 offset="0x2317" name="VGT_OUT_DEALLOC_CNTL">
1568 <bitfield name="DEALLOC_DIST" low="0" high="1" type="uint"/>
1570 <reg32 offset="0x2318" name="RB_COPY_CONTROL">
1571 <bitfield name="COPY_SAMPLE_SELECT" low="0" high="2" type="a2xx_rb_copy_sample_select"/>
1575 <reg32 offset="0x2319" name="RB_COPY_DEST_BASE"/>
1576 <reg32 offset="0x231a" name="RB_COPY_DEST_PITCH" shr="5" type="uint"/>
1577 <reg32 offset="0x231b" name="RB_COPY_DEST_INFO">
1578 <bitfield name="DEST_ENDIAN" low="0" high="2" type="adreno_rb_surface_endian"/>
1589 <reg32 offset="0x231c" name="RB_COPY_DEST_OFFSET">
1590 <bitfield name="X" low="0" high="12" type="uint"/>
1593 <reg32 offset="0x231d" name="RB_DEPTH_CLEAR"/>
1594 <reg32 offset="0x2324" name="RB_SAMPLE_COUNT_CTL"/>
1595 <reg32 offset="0x2326" name="RB_COLOR_DEST_MASK"/>
1596 <reg32 offset="0x2340" name="A225_GRAS_UCP0X"/>
1597 <reg32 offset="0x2357" name="A225_GRAS_UCP5W"/>
1598 <reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/>
1599 <reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/>
1600 <reg32 offset="0x2381" name="PA_SU_POLY_OFFSET_FRONT_OFFSET"/>
1601 <reg32 offset="0x2382" name="PA_SU_POLY_OFFSET_BACK_SCALE"/>
1602 <reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/>
1603 <reg32 offset="0x4000" name="SQ_CONSTANT_0"/>
1604 <reg32 offset="0x4800" name="SQ_FETCH_0"/>
1605 <reg32 offset="0x4900" name="SQ_CF_BOOLEANS"/>
1606 <reg32 offset="0x4908" name="SQ_CF_LOOP"/>
1607 <reg32 offset="0xa29" name="COHER_SIZE_PM4"/>
1608 <reg32 offset="0xa2a" name="COHER_BASE_PM4"/>
1609 <reg32 offset="0xa2b" name="COHER_STATUS_PM4"/>
1611 <reg32 offset="0x0c88" name="PA_SU_PERFCOUNTER0_SELECT"/>
1612 <reg32 offset="0x0c89" name="PA_SU_PERFCOUNTER1_SELECT"/>
1613 <reg32 offset="0x0c8a" name="PA_SU_PERFCOUNTER2_SELECT"/>
1614 <reg32 offset="0x0c8b" name="PA_SU_PERFCOUNTER3_SELECT"/>
1615 <reg32 offset="0x0c8c" name="PA_SU_PERFCOUNTER0_LOW"/>
1616 <reg32 offset="0x0c8d" name="PA_SU_PERFCOUNTER0_HI"/>
1617 <reg32 offset="0x0c8e" name="PA_SU_PERFCOUNTER1_LOW"/>
1618 <reg32 offset="0x0c8f" name="PA_SU_PERFCOUNTER1_HI"/>
1619 <reg32 offset="0x0c90" name="PA_SU_PERFCOUNTER2_LOW"/>
1620 <reg32 offset="0x0c91" name="PA_SU_PERFCOUNTER2_HI"/>
1621 <reg32 offset="0x0c92" name="PA_SU_PERFCOUNTER3_LOW"/>
1622 <reg32 offset="0x0c93" name="PA_SU_PERFCOUNTER3_HI"/>
1623 <reg32 offset="0x0c98" name="PA_SC_PERFCOUNTER0_SELECT"/>
1624 <reg32 offset="0x0c99" name="PA_SC_PERFCOUNTER0_LOW"/>
1625 <reg32 offset="0x0c9a" name="PA_SC_PERFCOUNTER0_HI"/>
1626 <reg32 offset="0x0c48" name="VGT_PERFCOUNTER0_SELECT"/>
1627 <reg32 offset="0x0c49" name="VGT_PERFCOUNTER1_SELECT"/>
1628 <reg32 offset="0x0c4a" name="VGT_PERFCOUNTER2_SELECT"/>
1629 <reg32 offset="0x0c4b" name="VGT_PERFCOUNTER3_SELECT"/>
1630 <reg32 offset="0x0c4c" name="VGT_PERFCOUNTER0_LOW"/>
1631 <reg32 offset="0x0c4e" name="VGT_PERFCOUNTER1_LOW"/>
1632 <reg32 offset="0x0c50" name="VGT_PERFCOUNTER2_LOW"/>
1633 <reg32 offset="0x0c52" name="VGT_PERFCOUNTER3_LOW"/>
1634 <reg32 offset="0x0c4d" name="VGT_PERFCOUNTER0_HI"/>
1635 <reg32 offset="0x0c4f" name="VGT_PERFCOUNTER1_HI"/>
1636 <reg32 offset="0x0c51" name="VGT_PERFCOUNTER2_HI"/>
1637 <reg32 offset="0x0c53" name="VGT_PERFCOUNTER3_HI"/>
1638 <reg32 offset="0x0e05" name="TCR_PERFCOUNTER0_SELECT"/>
1639 <reg32 offset="0x0e08" name="TCR_PERFCOUNTER1_SELECT"/>
1640 <reg32 offset="0x0e06" name="TCR_PERFCOUNTER0_HI"/>
1641 <reg32 offset="0x0e09" name="TCR_PERFCOUNTER1_HI"/>
1642 <reg32 offset="0x0e07" name="TCR_PERFCOUNTER0_LOW"/>
1643 <reg32 offset="0x0e0a" name="TCR_PERFCOUNTER1_LOW"/>
1644 <reg32 offset="0x0e1f" name="TP0_PERFCOUNTER0_SELECT"/>
1645 <reg32 offset="0x0e20" name="TP0_PERFCOUNTER0_HI"/>
1646 <reg32 offset="0x0e21" name="TP0_PERFCOUNTER0_LOW"/>
1647 <reg32 offset="0x0e22" name="TP0_PERFCOUNTER1_SELECT"/>
1648 <reg32 offset="0x0e23" name="TP0_PERFCOUNTER1_HI"/>
1649 <reg32 offset="0x0e24" name="TP0_PERFCOUNTER1_LOW"/>
1650 <reg32 offset="0x0e54" name="TCM_PERFCOUNTER0_SELECT"/>
1651 <reg32 offset="0x0e57" name="TCM_PERFCOUNTER1_SELECT"/>
1652 <reg32 offset="0x0e55" name="TCM_PERFCOUNTER0_HI"/>
1653 <reg32 offset="0x0e58" name="TCM_PERFCOUNTER1_HI"/>
1654 <reg32 offset="0x0e56" name="TCM_PERFCOUNTER0_LOW"/>
1655 <reg32 offset="0x0e59" name="TCM_PERFCOUNTER1_LOW"/>
1656 <reg32 offset="0x0e5a" name="TCF_PERFCOUNTER0_SELECT"/>
1657 <reg32 offset="0x0e5d" name="TCF_PERFCOUNTER1_SELECT"/>
1658 <reg32 offset="0x0e60" name="TCF_PERFCOUNTER2_SELECT"/>
1659 <reg32 offset="0x0e63" name="TCF_PERFCOUNTER3_SELECT"/>
1660 <reg32 offset="0x0e66" name="TCF_PERFCOUNTER4_SELECT"/>
1661 <reg32 offset="0x0e69" name="TCF_PERFCOUNTER5_SELECT"/>
1662 <reg32 offset="0x0e6c" name="TCF_PERFCOUNTER6_SELECT"/>
1663 <reg32 offset="0x0e6f" name="TCF_PERFCOUNTER7_SELECT"/>
1664 <reg32 offset="0x0e72" name="TCF_PERFCOUNTER8_SELECT"/>
1665 <reg32 offset="0x0e75" name="TCF_PERFCOUNTER9_SELECT"/>
1666 <reg32 offset="0x0e78" name="TCF_PERFCOUNTER10_SELECT"/>
1667 <reg32 offset="0x0e7b" name="TCF_PERFCOUNTER11_SELECT"/>
1668 <reg32 offset="0x0e5b" name="TCF_PERFCOUNTER0_HI"/>
1669 <reg32 offset="0x0e5e" name="TCF_PERFCOUNTER1_HI"/>
1670 <reg32 offset="0x0e61" name="TCF_PERFCOUNTER2_HI"/>
1671 <reg32 offset="0x0e64" name="TCF_PERFCOUNTER3_HI"/>
1672 <reg32 offset="0x0e67" name="TCF_PERFCOUNTER4_HI"/>
1673 <reg32 offset="0x0e6a" name="TCF_PERFCOUNTER5_HI"/>
1674 <reg32 offset="0x0e6d" name="TCF_PERFCOUNTER6_HI"/>
1675 <reg32 offset="0x0e70" name="TCF_PERFCOUNTER7_HI"/>
1676 <reg32 offset="0x0e73" name="TCF_PERFCOUNTER8_HI"/>
1677 <reg32 offset="0x0e76" name="TCF_PERFCOUNTER9_HI"/>
1678 <reg32 offset="0x0e79" name="TCF_PERFCOUNTER10_HI"/>
1679 <reg32 offset="0x0e7c" name="TCF_PERFCOUNTER11_HI"/>
1680 <reg32 offset="0x0e5c" name="TCF_PERFCOUNTER0_LOW"/>
1681 <reg32 offset="0x0e5f" name="TCF_PERFCOUNTER1_LOW"/>
1682 <reg32 offset="0x0e62" name="TCF_PERFCOUNTER2_LOW"/>
1683 <reg32 offset="0x0e65" name="TCF_PERFCOUNTER3_LOW"/>
1684 <reg32 offset="0x0e68" name="TCF_PERFCOUNTER4_LOW"/>
1685 <reg32 offset="0x0e6b" name="TCF_PERFCOUNTER5_LOW"/>
1686 <reg32 offset="0x0e6e" name="TCF_PERFCOUNTER6_LOW"/>
1687 <reg32 offset="0x0e71" name="TCF_PERFCOUNTER7_LOW"/>
1688 <reg32 offset="0x0e74" name="TCF_PERFCOUNTER8_LOW"/>
1689 <reg32 offset="0x0e77" name="TCF_PERFCOUNTER9_LOW"/>
1690 <reg32 offset="0x0e7a" name="TCF_PERFCOUNTER10_LOW"/>
1691 <reg32 offset="0x0e7d" name="TCF_PERFCOUNTER11_LOW"/>
1692 <reg32 offset="0x0dc8" name="SQ_PERFCOUNTER0_SELECT"/>
1693 <reg32 offset="0x0dc9" name="SQ_PERFCOUNTER1_SELECT"/>
1694 <reg32 offset="0x0dca" name="SQ_PERFCOUNTER2_SELECT"/>
1695 <reg32 offset="0x0dcb" name="SQ_PERFCOUNTER3_SELECT"/>
1696 <reg32 offset="0x0dcc" name="SQ_PERFCOUNTER0_LOW"/>
1697 <reg32 offset="0x0dcd" name="SQ_PERFCOUNTER0_HI"/>
1698 <reg32 offset="0x0dce" name="SQ_PERFCOUNTER1_LOW"/>
1699 <reg32 offset="0x0dcf" name="SQ_PERFCOUNTER1_HI"/>
1700 <reg32 offset="0x0dd0" name="SQ_PERFCOUNTER2_LOW"/>
1701 <reg32 offset="0x0dd1" name="SQ_PERFCOUNTER2_HI"/>
1702 <reg32 offset="0x0dd2" name="SQ_PERFCOUNTER3_LOW"/>
1703 <reg32 offset="0x0dd3" name="SQ_PERFCOUNTER3_HI"/>
1704 <reg32 offset="0x0dd4" name="SX_PERFCOUNTER0_SELECT"/>
1705 <reg32 offset="0x0dd8" name="SX_PERFCOUNTER0_LOW"/>
1706 <reg32 offset="0x0dd9" name="SX_PERFCOUNTER0_HI"/>
1707 <reg32 offset="0x0a46" name="MH_PERFCOUNTER0_SELECT"/>
1708 <reg32 offset="0x0a4a" name="MH_PERFCOUNTER1_SELECT"/>
1709 <reg32 offset="0x0a47" name="MH_PERFCOUNTER0_CONFIG"/>
1710 <reg32 offset="0x0a4b" name="MH_PERFCOUNTER1_CONFIG"/>
1711 <reg32 offset="0x0a48" name="MH_PERFCOUNTER0_LOW"/>
1712 <reg32 offset="0x0a4c" name="MH_PERFCOUNTER1_LOW"/>
1713 <reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/>
1714 <reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/>
1715 <reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/>
1716 <reg32 offset="0x0f05" name="RB_PERFCOUNTER1_SELECT"/>
1717 <reg32 offset="0x0f06" name="RB_PERFCOUNTER2_SELECT"/>
1718 <reg32 offset="0x0f07" name="RB_PERFCOUNTER3_SELECT"/>
1719 <reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/>
1720 <reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/>
1721 <reg32 offset="0x0f0a" name="RB_PERFCOUNTER1_LOW"/>
1722 <reg32 offset="0x0f0b" name="RB_PERFCOUNTER1_HI"/>
1723 <reg32 offset="0x0f0c" name="RB_PERFCOUNTER2_LOW"/>
1724 <reg32 offset="0x0f0d" name="RB_PERFCOUNTER2_HI"/>
1725 <reg32 offset="0x0f0e" name="RB_PERFCOUNTER3_LOW"/>
1726 <reg32 offset="0x0f0f" name="RB_PERFCOUNTER3_HI"/>
1732 <value name="SQ_TEX_WRAP" value="0"/>
1742 <value name="SQ_TEX_X" value="0"/>
1750 <value name="SQ_TEX_FILTER_POINT" value="0"/>
1756 <value name="SQ_TEX_ANISO_FILTER_DISABLED" value="0"/>
1765 <value name="SQ_TEX_DIMENSION_1D" value="0"/>
1771 <value name="SQ_TEX_BORDER_COLOR_BLACK" value="0"/>
1777 <value name="SQ_TEX_SIGN_UNSIGNED" value="0"/>
1785 <value name="SQ_TEX_ENDIAN_NONE" value="0"/>
1791 <value name="SQ_TEX_CLAMP_POLICY_D3D" value="0"/>
1795 <value name="SQ_TEX_NUM_FORMAT_FRAC" value="0"/>
1799 <value name="SQ_TEX_TYPE_0" value="0"/>
1804 <reg32 offset="0" name="0">
1805 <bitfield name="TYPE" low="0" high="1" type="sq_tex_type"/>
1817 <bitfield name="FORMAT" low="0" high="5" type="a2xx_sq_surfaceformat"/>
1825 <bitfield name="WIDTH" low="0" high="12" type="uint"/>
1831 <bitfield name="NUM_FORMAT" pos="0" type="sq_tex_num_format"/>
1844 <bitfield name="VOL_MAG_FILTER" pos="0" type="sq_tex_filter"/>
1855 <bitfield name="BORDER_COLOR" low="0" high="1" type="sq_tex_border_color"/>
1858 <bitfield name="ANISO_BIAS" low="5" high="8" type="fixed" radix="0"/> <!-- radix unknown -->