Lines Matching +full:0 +full:x2184
41 const u32 hoff = 0x800 * head; in gv100_sor_hda_device_entry()
43 nvkm_mask(device, 0x616528 + hoff, 0x00000070, head << 4); in gv100_sor_hda_device_entry()
57 const u32 hoff = head * 0x800; in gv100_sor_dp_watermark()
59 nvkm_mask(device, 0x616550 + hoff, 0x0c00003f, 0x08000000 | watermark); in gv100_sor_dp_watermark()
66 const u32 hoff = head * 0x800; in gv100_sor_dp_audio_sym()
68 nvkm_mask(device, 0x616568 + hoff, 0x0000ffff, h); in gv100_sor_dp_audio_sym()
69 nvkm_mask(device, 0x61656c + hoff, 0x00ffffff, v); in gv100_sor_dp_audio_sym()
76 const u32 hoff = 0x800 * head; in gv100_sor_dp_audio()
77 const u32 data = 0x80000000 | (0x00000001 * enable); in gv100_sor_dp_audio()
78 const u32 mask = 0x8000000d; in gv100_sor_dp_audio()
80 nvkm_mask(device, 0x616560 + hoff, mask, data); in gv100_sor_dp_audio()
82 if (!(nvkm_rd32(device, 0x616560 + hoff) & 0x80000000)) in gv100_sor_dp_audio()
89 .lanes = { 0, 1, 2, 3 },
104 const u32 hoff = head * 0x400; in gv100_sor_hdmi_infoframe_vsi()
108 nvkm_mask(device, 0x6f0100 + hoff, 0x00010001, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
112 nvkm_wr32(device, 0x6f0108 + hoff, vsi.header); in gv100_sor_hdmi_infoframe_vsi()
113 nvkm_wr32(device, 0x6f010c + hoff, vsi.subpack0_low); in gv100_sor_hdmi_infoframe_vsi()
114 nvkm_wr32(device, 0x6f0110 + hoff, vsi.subpack0_high); in gv100_sor_hdmi_infoframe_vsi()
115 nvkm_wr32(device, 0x6f0114 + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
116 nvkm_wr32(device, 0x6f0118 + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
117 nvkm_wr32(device, 0x6f011c + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
118 nvkm_wr32(device, 0x6f0120 + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
119 nvkm_wr32(device, 0x6f0124 + hoff, 0x00000000); in gv100_sor_hdmi_infoframe_vsi()
120 nvkm_mask(device, 0x6f0100 + hoff, 0x00000001, 0x00000001); in gv100_sor_hdmi_infoframe_vsi()
128 const u32 hoff = head * 0x400; in gv100_sor_hdmi_infoframe_avi()
132 nvkm_mask(device, 0x6f0000 + hoff, 0x00000001, 0x00000000); in gv100_sor_hdmi_infoframe_avi()
136 nvkm_wr32(device, 0x6f0008 + hoff, avi.header); in gv100_sor_hdmi_infoframe_avi()
137 nvkm_wr32(device, 0x6f000c + hoff, avi.subpack0_low); in gv100_sor_hdmi_infoframe_avi()
138 nvkm_wr32(device, 0x6f0010 + hoff, avi.subpack0_high); in gv100_sor_hdmi_infoframe_avi()
139 nvkm_wr32(device, 0x6f0014 + hoff, avi.subpack1_low); in gv100_sor_hdmi_infoframe_avi()
140 nvkm_wr32(device, 0x6f0018 + hoff, avi.subpack1_high); in gv100_sor_hdmi_infoframe_avi()
142 nvkm_mask(device, 0x6f0000 + hoff, 0x00000001, 0x00000001); in gv100_sor_hdmi_infoframe_avi()
149 const u32 ctrl = 0x40000000 * enable | in gv100_sor_hdmi_ctrl()
152 const u32 hoff = head * 0x800; in gv100_sor_hdmi_ctrl()
153 const u32 hdmi = head * 0x400; in gv100_sor_hdmi_ctrl()
155 if (!(ctrl & 0x40000000)) { in gv100_sor_hdmi_ctrl()
156 nvkm_mask(device, 0x6165c0 + hoff, 0x40000000, 0x00000000); in gv100_sor_hdmi_ctrl()
157 nvkm_mask(device, 0x6f0100 + hdmi, 0x00000001, 0x00000000); in gv100_sor_hdmi_ctrl()
158 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); in gv100_sor_hdmi_ctrl()
159 nvkm_mask(device, 0x6f0000 + hdmi, 0x00000001, 0x00000000); in gv100_sor_hdmi_ctrl()
164 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000000); in gv100_sor_hdmi_ctrl()
165 nvkm_wr32(device, 0x6f00cc + hdmi, 0x00000010); in gv100_sor_hdmi_ctrl()
166 nvkm_mask(device, 0x6f00c0 + hdmi, 0x00000001, 0x00000001); in gv100_sor_hdmi_ctrl()
169 nvkm_wr32(device, 0x6f0080 + hdmi, 0x82000000); in gv100_sor_hdmi_ctrl()
172 nvkm_mask(device, 0x6165c0 + hoff, 0x401f007f, ctrl); in gv100_sor_hdmi_ctrl()
187 const u32 coff = (state == &sor->arm) * 0x8000 + sor->id * 0x20; in gv100_sor_state()
188 u32 ctrl = nvkm_rd32(device, 0x680300 + coff); in gv100_sor_state()
190 state->proto_evo = (ctrl & 0x00000f00) >> 8; in gv100_sor_state()
192 case 0: state->proto = LVDS; state->link = 1; break; in gv100_sor_state()
203 state->head = ctrl & 0x000000ff; in gv100_sor_state()
227 if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000)) in gv100_sor_new()
228 hda = nvkm_rd32(device, 0x118fb0) >> 8; in gv100_sor_new()
238 *pmask = (nvkm_rd32(device, 0x610060) & 0x0000ff00) >> 8; in gv100_sor_cnt()
239 return (nvkm_rd32(device, 0x610074) & 0x00000f00) >> 8; in gv100_sor_cnt()
246 nvkm_mask(device, 0x611d80 + (head->id * 4), 0x00000004, 0x00000000); in gv100_head_vblank_put()
253 nvkm_mask(device, 0x611d80 + (head->id * 4), 0x00000004, 0x00000004); in gv100_head_vblank_get()
260 const u32 hoff = head->id * 0x800; in gv100_head_rgpos()
262 *vline = nvkm_rd32(device, 0x616330 + hoff) & 0x0000ffff; in gv100_head_rgpos()
263 *hline = nvkm_rd32(device, 0x616334 + hoff) & 0x0000ffff; in gv100_head_rgpos()
270 const u32 hoff = (state == &head->arm) * 0x8000 + head->id * 0x400; in gv100_head_state()
273 data = nvkm_rd32(device, 0x682064 + hoff); in gv100_head_state()
274 state->vtotal = (data & 0xffff0000) >> 16; in gv100_head_state()
275 state->htotal = (data & 0x0000ffff); in gv100_head_state()
276 data = nvkm_rd32(device, 0x682068 + hoff); in gv100_head_state()
277 state->vsynce = (data & 0xffff0000) >> 16; in gv100_head_state()
278 state->hsynce = (data & 0x0000ffff); in gv100_head_state()
279 data = nvkm_rd32(device, 0x68206c + hoff); in gv100_head_state()
280 state->vblanke = (data & 0xffff0000) >> 16; in gv100_head_state()
281 state->hblanke = (data & 0x0000ffff); in gv100_head_state()
282 data = nvkm_rd32(device, 0x682070 + hoff); in gv100_head_state()
283 state->vblanks = (data & 0xffff0000) >> 16; in gv100_head_state()
284 state->hblanks = (data & 0x0000ffff); in gv100_head_state()
285 state->hz = nvkm_rd32(device, 0x68200c + hoff); in gv100_head_state()
287 data = nvkm_rd32(device, 0x682004 + hoff); in gv100_head_state()
288 switch ((data & 0x000000f0) >> 4) { in gv100_head_state()
313 if (!(nvkm_rd32(device, 0x610060) & (0x00000001 << id))) in gv100_head_new()
314 return 0; in gv100_head_new()
324 *pmask = nvkm_rd32(device, 0x610060) & 0x000000ff; in gv100_head_cnt()
325 return nvkm_rd32(device, 0x610074) & 0x0000000f; in gv100_head_cnt()
335 *psize = 0x1000; in gv100_disp_chan_user()
336 return 0x690000 + ((chan->chid.user - 1) * 0x1000); in gv100_disp_chan_user()
343 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_dmac_idle()
345 u32 stat = nvkm_rd32(device, 0x610664 + soff); in gv100_disp_dmac_idle()
346 if ((stat & 0x000f0000) == 0x00040000) in gv100_disp_dmac_idle()
347 return 0; in gv100_disp_dmac_idle()
357 chan->chid.user << 25 | 0x00000040); in gv100_disp_dmac_bind()
364 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_fini()
365 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_fini()
366 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000000); in gv100_disp_dmac_fini()
368 nvkm_mask(device, 0x6104e0 + coff, 0x00000002, 0x00000000); in gv100_disp_dmac_fini()
369 chan->suspend_put = nvkm_rd32(device, 0x690000 + uoff); in gv100_disp_dmac_fini()
377 const u32 uoff = (chan->chid.ctrl - 1) * 0x1000; in gv100_disp_dmac_init()
378 const u32 poff = chan->chid.ctrl * 0x10; in gv100_disp_dmac_init()
379 const u32 coff = chan->chid.ctrl * 0x04; in gv100_disp_dmac_init()
381 nvkm_wr32(device, 0x610b24 + poff, lower_32_bits(chan->push)); in gv100_disp_dmac_init()
382 nvkm_wr32(device, 0x610b20 + poff, upper_32_bits(chan->push)); in gv100_disp_dmac_init()
383 nvkm_wr32(device, 0x610b28 + poff, 0x00000001); in gv100_disp_dmac_init()
384 nvkm_wr32(device, 0x610b2c + poff, 0x00000040); in gv100_disp_dmac_init()
386 nvkm_mask(device, 0x6104e0 + coff, 0x00000010, 0x00000010); in gv100_disp_dmac_init()
387 nvkm_wr32(device, 0x690000 + uoff, chan->suspend_put); in gv100_disp_dmac_init()
388 nvkm_wr32(device, 0x6104e0 + coff, 0x00000013); in gv100_disp_dmac_init()
396 const u32 mask = 0x00000001 << chan->head; in gv100_disp_wimm_intr()
397 const u32 data = en ? mask : 0; in gv100_disp_wimm_intr()
398 nvkm_mask(device, 0x611da8, mask, data); in gv100_disp_wimm_intr()
419 .mthd = 0x0000,
420 .addr = 0x000000,
422 { 0x0200, 0x690200 },
423 { 0x020c, 0x69020c },
424 { 0x0210, 0x690210 },
425 { 0x0214, 0x690214 },
426 { 0x0218, 0x690218 },
427 { 0x021c, 0x69021c },
428 { 0x0220, 0x690220 },
429 { 0x0224, 0x690224 },
430 { 0x0228, 0x690228 },
431 { 0x022c, 0x69022c },
432 { 0x0230, 0x690230 },
433 { 0x0234, 0x690234 },
434 { 0x0238, 0x690238 },
435 { 0x0240, 0x690240 },
436 { 0x0244, 0x690244 },
437 { 0x0248, 0x690248 },
438 { 0x024c, 0x69024c },
439 { 0x0250, 0x690250 },
440 { 0x0254, 0x690254 },
441 { 0x0260, 0x690260 },
442 { 0x0264, 0x690264 },
443 { 0x0268, 0x690268 },
444 { 0x026c, 0x69026c },
445 { 0x0270, 0x690270 },
446 { 0x0274, 0x690274 },
447 { 0x0280, 0x690280 },
448 { 0x0284, 0x690284 },
449 { 0x0288, 0x690288 },
450 { 0x028c, 0x69028c },
451 { 0x0290, 0x690290 },
452 { 0x0298, 0x690298 },
453 { 0x029c, 0x69029c },
454 { 0x02a0, 0x6902a0 },
455 { 0x02a4, 0x6902a4 },
456 { 0x02a8, 0x6902a8 },
457 { 0x02ac, 0x6902ac },
458 { 0x02b0, 0x6902b0 },
459 { 0x02b4, 0x6902b4 },
460 { 0x02b8, 0x6902b8 },
461 { 0x02bc, 0x6902bc },
462 { 0x02c0, 0x6902c0 },
463 { 0x02c4, 0x6902c4 },
464 { 0x02c8, 0x6902c8 },
465 { 0x02cc, 0x6902cc },
466 { 0x02d0, 0x6902d0 },
467 { 0x02d4, 0x6902d4 },
468 { 0x02d8, 0x6902d8 },
469 { 0x02dc, 0x6902dc },
470 { 0x02e0, 0x6902e0 },
471 { 0x02e4, 0x6902e4 },
472 { 0x02e8, 0x6902e8 },
473 { 0x02ec, 0x6902ec },
474 { 0x02f0, 0x6902f0 },
475 { 0x02f4, 0x6902f4 },
476 { 0x02f8, 0x6902f8 },
477 { 0x02fc, 0x6902fc },
478 { 0x0300, 0x690300 },
479 { 0x0304, 0x690304 },
480 { 0x0308, 0x690308 },
481 { 0x0310, 0x690310 },
482 { 0x0314, 0x690314 },
483 { 0x0318, 0x690318 },
484 { 0x031c, 0x69031c },
485 { 0x0320, 0x690320 },
486 { 0x0324, 0x690324 },
487 { 0x0328, 0x690328 },
488 { 0x032c, 0x69032c },
489 { 0x033c, 0x69033c },
490 { 0x0340, 0x690340 },
491 { 0x0344, 0x690344 },
492 { 0x0348, 0x690348 },
493 { 0x034c, 0x69034c },
494 { 0x0350, 0x690350 },
495 { 0x0354, 0x690354 },
496 { 0x0358, 0x690358 },
497 { 0x0364, 0x690364 },
498 { 0x0368, 0x690368 },
499 { 0x036c, 0x69036c },
500 { 0x0370, 0x690370 },
501 { 0x0374, 0x690374 },
502 { 0x0380, 0x690380 },
510 .addr = 0x001000,
511 .prev = 0x000800,
522 const u32 mask = 0x00000001 << chan->head; in gv100_disp_wndw_intr()
523 const u32 data = en ? mask : 0; in gv100_disp_wndw_intr()
524 nvkm_mask(device, 0x611da4, mask, data); in gv100_disp_wndw_intr()
550 *pmask = nvkm_rd32(device, 0x610064); in gv100_disp_wndw_cnt()
551 return (nvkm_rd32(device, 0x610074) & 0x03f00000) >> 20; in gv100_disp_wndw_cnt()
558 const u32 soff = (chan->chid.ctrl - 1) * 0x04; in gv100_disp_curs_idle()
560 u32 stat = nvkm_rd32(device, 0x610664 + soff); in gv100_disp_curs_idle()
561 if ((stat & 0x00070000) == 0x00040000) in gv100_disp_curs_idle()
562 return 0; in gv100_disp_curs_idle()
571 const u32 mask = 0x00010000 << chan->head; in gv100_disp_curs_intr()
572 const u32 data = en ? mask : 0; in gv100_disp_curs_intr()
573 nvkm_mask(device, 0x611dac, mask, data); in gv100_disp_curs_intr()
581 nvkm_mask(device, 0x6104e0 + hoff, 0x00000010, 0x00000010); in gv100_disp_curs_fini()
583 nvkm_mask(device, 0x6104e0 + hoff, 0x00000001, 0x00000000); in gv100_disp_curs_fini()
591 nvkm_wr32(device, 0x6104e0 + chan->chid.ctrl * 4, 0x00000001); in gv100_disp_curs_init()
612 .mthd = 0x0000,
613 .addr = 0x000000,
615 { 0x0200, 0x680200 },
616 { 0x0208, 0x680208 },
617 { 0x020c, 0x68020c },
618 { 0x0210, 0x680210 },
619 { 0x0214, 0x680214 },
620 { 0x0218, 0x680218 },
621 { 0x021c, 0x68021c },
628 .mthd = 0x0020,
629 .addr = 0x000020,
631 { 0x0300, 0x680300 },
632 { 0x0304, 0x680304 },
633 { 0x0308, 0x680308 },
634 { 0x030c, 0x68030c },
641 .mthd = 0x0080,
642 .addr = 0x000080,
644 { 0x1000, 0x681000 },
645 { 0x1004, 0x681004 },
646 { 0x1008, 0x681008 },
647 { 0x100c, 0x68100c },
648 { 0x1010, 0x681010 },
655 .mthd = 0x0400,
656 .addr = 0x000400,
658 { 0x2000, 0x682000 },
659 { 0x2004, 0x682004 },
660 { 0x2008, 0x682008 },
661 { 0x200c, 0x68200c },
662 { 0x2014, 0x682014 },
663 { 0x2018, 0x682018 },
664 { 0x201c, 0x68201c },
665 { 0x2020, 0x682020 },
666 { 0x2028, 0x682028 },
667 { 0x202c, 0x68202c },
668 { 0x2030, 0x682030 },
669 { 0x2038, 0x682038 },
670 { 0x203c, 0x68203c },
671 { 0x2048, 0x682048 },
672 { 0x204c, 0x68204c },
673 { 0x2050, 0x682050 },
674 { 0x2054, 0x682054 },
675 { 0x2058, 0x682058 },
676 { 0x205c, 0x68205c },
677 { 0x2060, 0x682060 },
678 { 0x2064, 0x682064 },
679 { 0x2068, 0x682068 },
680 { 0x206c, 0x68206c },
681 { 0x2070, 0x682070 },
682 { 0x2074, 0x682074 },
683 { 0x2078, 0x682078 },
684 { 0x207c, 0x68207c },
685 { 0x2080, 0x682080 },
686 { 0x2088, 0x682088 },
687 { 0x2090, 0x682090 },
688 { 0x209c, 0x68209c },
689 { 0x20a0, 0x6820a0 },
690 { 0x20a4, 0x6820a4 },
691 { 0x20a8, 0x6820a8 },
692 { 0x20ac, 0x6820ac },
693 { 0x2180, 0x682180 },
694 { 0x2184, 0x682184 },
695 { 0x218c, 0x68218c },
696 { 0x2194, 0x682194 },
697 { 0x2198, 0x682198 },
698 { 0x219c, 0x68219c },
699 { 0x21a0, 0x6821a0 },
700 { 0x21a4, 0x6821a4 },
701 { 0x2214, 0x682214 },
702 { 0x2218, 0x682218 },
710 .addr = 0x000000,
711 .prev = 0x008000,
726 u32 stat = nvkm_rd32(device, 0x610630); in gv100_disp_core_idle()
727 if ((stat & 0x001f0000) == 0x000b0000) in gv100_disp_core_idle()
728 return 0; in gv100_disp_core_idle()
736 *psize = 0x10000; in gv100_disp_core_user()
737 return 0x680000; in gv100_disp_core_user()
744 const u32 mask = 0x00000001; in gv100_disp_core_intr()
745 const u32 data = en ? mask : 0; in gv100_disp_core_intr()
746 nvkm_mask(device, 0x611dac, mask, data); in gv100_disp_core_intr()
753 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000000); in gv100_disp_core_fini()
755 nvkm_mask(device, 0x6104e0, 0x00000002, 0x00000000); in gv100_disp_core_fini()
756 chan->suspend_put = nvkm_rd32(device, 0x680000); in gv100_disp_core_fini()
765 nvkm_wr32(device, 0x610b24, lower_32_bits(chan->push)); in gv100_disp_core_init()
766 nvkm_wr32(device, 0x610b20, upper_32_bits(chan->push)); in gv100_disp_core_init()
767 nvkm_wr32(device, 0x610b28, 0x00000001); in gv100_disp_core_init()
768 nvkm_wr32(device, 0x610b2c, 0x00000040); in gv100_disp_core_init()
770 nvkm_mask(device, 0x6104e0, 0x00000010, 0x00000010); in gv100_disp_core_init()
771 nvkm_wr32(device, 0x680000, chan->suspend_put); in gv100_disp_core_init()
772 nvkm_wr32(device, 0x6104e0, 0x00000013); in gv100_disp_core_init()
789 .ctrl = 0,
790 .user = 0,
808 *addr = 0x640000 + device->func->resource_addr(device, 0); in gv100_disp_caps_map()
809 *size = 0x1000; in gv100_disp_caps_map()
810 return 0; in gv100_disp_caps_map()
831 return 0; in gv100_disp_caps_new()
844 stat = nvkm_rd32(device, 0x6107a8); in gv100_disp_super()
848 mask[head->id] = nvkm_rd32(device, 0x6107ac + (head->id * 4)); in gv100_disp_super()
852 if (disp->super.pending & 0x00000001) { in gv100_disp_super()
853 nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG); in gv100_disp_super()
856 if (!(mask[head->id] & 0x00001000)) in gv100_disp_super()
861 if (disp->super.pending & 0x00000002) { in gv100_disp_super()
863 if (!(mask[head->id] & 0x00001000)) in gv100_disp_super()
868 if (!(mask[head->id] & 0x00010000)) in gv100_disp_super()
873 if (!(mask[head->id] & 0x00001000)) in gv100_disp_super()
878 if (disp->super.pending & 0x00000004) { in gv100_disp_super()
880 if (!(mask[head->id] & 0x00001000)) in gv100_disp_super()
887 nvkm_wr32(device, 0x6107ac + (head->id * 4), 0x00000000); in gv100_disp_super()
889 nvkm_wr32(device, 0x6107a8, 0x80000000); in gv100_disp_super()
898 u32 stat = nvkm_rd32(device, 0x611020 + (chid * 12)); in gv100_disp_exception()
899 u32 type = (stat & 0x00007000) >> 12; in gv100_disp_exception()
900 u32 mthd = (stat & 0x00000fff) << 2; in gv100_disp_exception()
910 u32 data = nvkm_rd32(device, 0x611024 + (chid * 12)); in gv100_disp_exception()
911 u32 code = nvkm_rd32(device, 0x611028 + (chid * 12)); in gv100_disp_exception()
924 case 0x0200: in gv100_disp_exception()
932 nvkm_wr32(device, 0x611020 + (chid * 12), 0x90000000); in gv100_disp_exception()
940 u32 stat = nvkm_rd32(device, 0x611c30); in gv100_disp_intr_ctrl_disp()
942 if (stat & 0x00000007) { in gv100_disp_intr_ctrl_disp()
943 disp->super.pending = (stat & 0x00000007); in gv100_disp_intr_ctrl_disp()
945 nvkm_wr32(device, 0x611860, disp->super.pending); in gv100_disp_intr_ctrl_disp()
946 stat &= ~0x00000007; in gv100_disp_intr_ctrl_disp()
952 if (stat & 0x00000008) in gv100_disp_intr_ctrl_disp()
953 stat &= ~0x00000008; in gv100_disp_intr_ctrl_disp()
955 if (stat & 0x00000080) { in gv100_disp_intr_ctrl_disp()
956 u32 error = nvkm_mask(device, 0x611848, 0x00000000, 0x00000000); in gv100_disp_intr_ctrl_disp()
958 stat &= ~0x00000080; in gv100_disp_intr_ctrl_disp()
961 if (stat & 0x00000100) { in gv100_disp_intr_ctrl_disp()
962 unsigned long wndws = nvkm_rd32(device, 0x611858); in gv100_disp_intr_ctrl_disp()
963 unsigned long other = nvkm_rd32(device, 0x61185c); in gv100_disp_intr_ctrl_disp()
966 nvkm_wr32(device, 0x611858, wndws); in gv100_disp_intr_ctrl_disp()
967 nvkm_wr32(device, 0x61185c, other); in gv100_disp_intr_ctrl_disp()
970 if (other & 0x00000001) in gv100_disp_intr_ctrl_disp()
971 nv50_disp_chan_uevent_send(disp, 0); in gv100_disp_intr_ctrl_disp()
988 u32 stat = nvkm_rd32(device, 0x611854); in gv100_disp_intr_exc_other()
992 if (stat & 0x00000001) { in gv100_disp_intr_exc_other()
993 nvkm_wr32(device, 0x611854, 0x00000001); in gv100_disp_intr_exc_other()
994 gv100_disp_exception(disp, 0); in gv100_disp_intr_exc_other()
995 stat &= ~0x00000001; in gv100_disp_intr_exc_other()
998 if ((mask = (stat & 0x00ff0000) >> 16)) { in gv100_disp_intr_exc_other()
1000 nvkm_wr32(device, 0x611854, 0x00010000 << head); in gv100_disp_intr_exc_other()
1002 stat &= ~(0x00010000 << head); in gv100_disp_intr_exc_other()
1008 nvkm_wr32(device, 0x611854, stat); in gv100_disp_intr_exc_other()
1017 unsigned long stat = nvkm_rd32(device, 0x611850); in gv100_disp_intr_exc_winim()
1021 nvkm_wr32(device, 0x611850, BIT(wndw)); in gv100_disp_intr_exc_winim()
1028 nvkm_wr32(device, 0x611850, stat); in gv100_disp_intr_exc_winim()
1037 unsigned long stat = nvkm_rd32(device, 0x61184c); in gv100_disp_intr_exc_win()
1041 nvkm_wr32(device, 0x61184c, BIT(wndw)); in gv100_disp_intr_exc_win()
1048 nvkm_wr32(device, 0x61184c, stat); in gv100_disp_intr_exc_win()
1057 u32 stat = nvkm_rd32(device, 0x611800 + (head * 0x04)); in gv100_disp_intr_head_timing()
1060 if (stat & 0x00000003) { in gv100_disp_intr_head_timing()
1061 nvkm_wr32(device, 0x611800 + (head * 0x04), stat & 0x00000003); in gv100_disp_intr_head_timing()
1062 stat &= ~0x00000003; in gv100_disp_intr_head_timing()
1065 if (stat & 0x00000004) { in gv100_disp_intr_head_timing()
1067 nvkm_wr32(device, 0x611800 + (head * 0x04), 0x00000004); in gv100_disp_intr_head_timing()
1068 stat &= ~0x00000004; in gv100_disp_intr_head_timing()
1073 nvkm_wr32(device, 0x611800 + (head * 0x04), stat); in gv100_disp_intr_head_timing()
1082 u32 stat = nvkm_rd32(device, 0x611ec0); in gv100_disp_intr()
1086 if ((mask = (stat & 0x000000ff))) { in gv100_disp_intr()
1093 if (stat & 0x00000200) { in gv100_disp_intr()
1095 stat &= ~0x00000200; in gv100_disp_intr()
1098 if (stat & 0x00000400) { in gv100_disp_intr()
1100 stat &= ~0x00000400; in gv100_disp_intr()
1103 if (stat & 0x00000800) { in gv100_disp_intr()
1105 stat &= ~0x00000800; in gv100_disp_intr()
1108 if (stat & 0x00001000) { in gv100_disp_intr()
1110 stat &= ~0x00001000; in gv100_disp_intr()
1121 nvkm_wr32(device, 0x611db0, 0x00000000); in gv100_disp_fini()
1133 if (nvkm_rd32(device, 0x6254e8) & 0x00000002) { in gv100_disp_init()
1134 nvkm_mask(device, 0x6254e8, 0x00000001, 0x00000000); in gv100_disp_init()
1136 if (!(nvkm_rd32(device, 0x6254e8) & 0x00000002)) in gv100_disp_init()
1138 ) < 0) in gv100_disp_init()
1143 tmp = nvkm_rd32(device, 0x610068); in gv100_disp_init()
1144 nvkm_wr32(device, 0x640008, tmp); in gv100_disp_init()
1147 for (i = 0; i < disp->sor.nr; i++) { in gv100_disp_init()
1148 tmp = nvkm_rd32(device, 0x61c000 + (i * 0x800)); in gv100_disp_init()
1149 nvkm_mask(device, 0x640000, 0x00000100 << i, 0x00000100 << i); in gv100_disp_init()
1150 nvkm_wr32(device, 0x640144 + (i * 0x08), tmp); in gv100_disp_init()
1158 tmp = nvkm_rd32(device, 0x616300 + (id * 0x800)); in gv100_disp_init()
1159 nvkm_wr32(device, 0x640048 + (id * 0x020), tmp); in gv100_disp_init()
1162 for (j = 0; j < 6 * 4; j += 4) { in gv100_disp_init()
1163 tmp = nvkm_rd32(device, 0x616100 + (id * 0x800) + j); in gv100_disp_init()
1164 nvkm_wr32(device, 0x640030 + (id * 0x20) + j, tmp); in gv100_disp_init()
1169 for (i = 0; i < disp->wndw.nr; i++) { in gv100_disp_init()
1170 nvkm_mask(device, 0x640004, 1 << i, 1 << i); in gv100_disp_init()
1171 for (j = 0; j < 6 * 4; j += 4) { in gv100_disp_init()
1172 tmp = nvkm_rd32(device, 0x630050 + (i * 0x800) + j); in gv100_disp_init()
1173 nvkm_wr32(device, 0x6401e4 + (i * 0x20) + j, tmp); in gv100_disp_init()
1178 for (i = 0; i < 4; i++) { in gv100_disp_init()
1179 tmp = nvkm_rd32(device, 0x62e000 + (i * 0x04)); in gv100_disp_init()
1180 nvkm_wr32(device, 0x640010 + (i * 0x04), tmp); in gv100_disp_init()
1183 nvkm_mask(device, 0x610078, 0x00000001, 0x00000001); in gv100_disp_init()
1187 case NVKM_MEM_TARGET_VRAM: tmp = 0x00000001; break; in gv100_disp_init()
1188 case NVKM_MEM_TARGET_NCOH: tmp = 0x00000002; break; in gv100_disp_init()
1189 case NVKM_MEM_TARGET_HOST: tmp = 0x00000003; break; in gv100_disp_init()
1193 nvkm_wr32(device, 0x610010, 0x00000008 | tmp); in gv100_disp_init()
1194 nvkm_wr32(device, 0x610014, disp->inst->addr >> 16); in gv100_disp_init()
1197 nvkm_wr32(device, 0x611cf0, 0x00000187); /* MSK. */ in gv100_disp_init()
1198 nvkm_wr32(device, 0x611db0, 0x00000187); /* EN. */ in gv100_disp_init()
1201 nvkm_wr32(device, 0x611cec, disp->head.mask << 16 | in gv100_disp_init()
1202 0x00000001); /* MSK. */ in gv100_disp_init()
1203 nvkm_wr32(device, 0x611dac, 0x00000000); /* EN. */ in gv100_disp_init()
1206 nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */ in gv100_disp_init()
1207 nvkm_wr32(device, 0x611da8, 0x00000000); /* EN. */ in gv100_disp_init()
1210 nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */ in gv100_disp_init()
1211 nvkm_wr32(device, 0x611da4, 0x00000000); /* EN. */ in gv100_disp_init()
1216 nvkm_wr32(device, 0x611cc0 + hoff, 0x00000004); /* MSK. */ in gv100_disp_init()
1217 nvkm_wr32(device, 0x611d80 + hoff, 0x00000000); /* EN. */ in gv100_disp_init()
1221 nvkm_wr32(device, 0x611cf4, 0x00000000); /* MSK. */ in gv100_disp_init()
1222 nvkm_wr32(device, 0x611db4, 0x00000000); /* EN. */ in gv100_disp_init()
1223 return 0; in gv100_disp_init()
1237 .ramht_size = 0x2000,
1238 .root = { 0, 0,GV100_DISP },
1241 {{ 0, 0,GV100_DISP_CURSOR }, nvkm_disp_chan_new, &gv100_disp_curs },
1242 {{ 0, 0,GV100_DISP_WINDOW_IMM_CHANNEL_DMA}, nvkm_disp_wndw_new, &gv100_disp_wimm },
1243 {{ 0, 0,GV100_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gv100_disp_core },
1244 {{ 0, 0,GV100_DISP_WINDOW_CHANNEL_DMA }, nvkm_disp_wndw_new, &gv100_disp_wndw },