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/linux/arch/x86/kernel/cpu/
H A Damd_cache_disable.c3 * AMD L3 cache_disable_{0,1} sysfs handling
23 u32 val = 0; in amd_calc_l3_indices()
25 pci_read_config_dword(nb->misc, 0x1C4, &val); in amd_calc_l3_indices()
28 l3->subcaches[0] = sc0 = !(val & BIT(0)); in amd_calc_l3_indices()
31 if (boot_cpu_data.x86 == 0x15) { in amd_calc_l3_indices()
32 l3->subcaches[0] = sc0 += !(val & BIT(1)); in amd_calc_l3_indices()
45 * @slot: slot number (0..1)
51 unsigned int reg = 0; in amd_get_l3_disable_slot()
53 pci_read_config_dword(nb->misc, 0x1BC + slot * 4, &reg); in amd_get_l3_disable_slot()
57 return reg & 0xfff; in amd_get_l3_disable_slot()
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcs-ufs-v3.h9 #define QPHY_V3_PCS_UFS_PHY_START 0x000
10 #define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL 0x004
11 #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
12 #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034
13 #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134
14 #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138
15 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c
16 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140
17 #define QPHY_V3_PCS_UFS_READY_STATUS 0x160
18 #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc
[all …]
H A Dphy-qcom-qmp-pcs-v5_20.h9 #define QPHY_V5_20_PCS_INSIG_SW_CTRL7 0x060
10 #define QPHY_V5_20_PCS_INSIG_MX_CTRL7 0x07c
11 #define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG1 0x0c4
12 #define QPHY_V5_20_PCS_LOCK_DETECT_CONFIG2 0x0c8
13 #define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
14 #define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
15 #define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG1 0x1b8
16 #define QPHY_V5_20_PCS_ALIGN_DETECT_CONFIG2 0x1bc
17 #define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8
18 #define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-ufs-v8.h9 #define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX (0x34)
10 #define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX (0x38)
11 #define QSERDES_UFS_V8_TX_LANE_MODE_1 (0x80)
12 #define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2 (0x1bc)
13 #define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4 (0x1c4)
14 #define QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4 (0x1dc)
15 #define QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x2c8)
16 #define QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS (0x1e4)
17 #define QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3 (0x2d0)
18 #define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 (0x120)
[all …]
H A Dphy-qcom-qmp-qserdes-com-v10.h11 #define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1 0x00
12 #define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1 0x04
13 #define QSERDES_V10_COM_CP_CTRL_MODE1 0x10
14 #define QSERDES_V10_COM_PLL_RCTRL_MODE1 0x14
15 #define QSERDES_V10_COM_PLL_CCTRL_MODE1 0x18
16 #define QSERDES_V10_COM_CORECLK_DIV_MODE1 0x1c
17 #define QSERDES_V10_COM_LOCK_CMP1_MODE1 0x20
18 #define QSERDES_V10_COM_LOCK_CMP2_MODE1 0x24
19 #define QSERDES_V10_COM_DEC_START_MODE1 0x28
20 #define QSERDES_V10_COM_DEC_START_MSB_MODE1 0x2c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v7.h11 #define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1 0x00
12 #define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1 0x04
13 #define QSERDES_V7_COM_CP_CTRL_MODE1 0x10
14 #define QSERDES_V7_COM_PLL_RCTRL_MODE1 0x14
15 #define QSERDES_V7_COM_PLL_CCTRL_MODE1 0x18
16 #define QSERDES_V7_COM_CORECLK_DIV_MODE1 0x1c
17 #define QSERDES_V7_COM_LOCK_CMP1_MODE1 0x20
18 #define QSERDES_V7_COM_LOCK_CMP2_MODE1 0x24
19 #define QSERDES_V7_COM_DEC_START_MODE1 0x28
20 #define QSERDES_V7_COM_DEC_START_MSB_MODE1 0x2c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v10_60.h9 #define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_TX 0x034
10 #define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_RX 0x038
11 #define QSERDES_V10_60_TXRX_LANE_MODE_1 0x080
12 #define QSERDES_V10_60_TXRX_LANE_MODE_2 0x084
13 #define QSERDES_V10_60_TXRX_LANE_MODE_3 0x088
14 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x0c8
15 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x0cc
16 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x0d0
17 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x0d4
18 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x0e0
[all …]
H A Dphy-qcom-qmp-qserdes-com-v5.h10 #define QSERDES_V5_COM_ATB_SEL1 0x000
11 #define QSERDES_V5_COM_ATB_SEL2 0x004
12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V5_COM_BG_TIMER 0x00c
14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V5_COM_SSC_PER1 0x01c
18 #define QSERDES_V5_COM_SSC_PER2 0x020
19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v4.h10 #define QSERDES_V4_COM_ATB_SEL1 0x000
11 #define QSERDES_V4_COM_ATB_SEL2 0x004
12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V4_COM_BG_TIMER 0x00c
14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V4_COM_SSC_PER1 0x01c
18 #define QSERDES_V4_COM_SSC_PER2 0x020
19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
H A Dphy-qcom-qmp-pcs-v4.h10 #define QPHY_V4_PCS_SW_RESET 0x000
11 #define QPHY_V4_PCS_REVISION_ID0 0x004
12 #define QPHY_V4_PCS_REVISION_ID1 0x008
13 #define QPHY_V4_PCS_REVISION_ID2 0x00c
14 #define QPHY_V4_PCS_REVISION_ID3 0x010
15 #define QPHY_V4_PCS_PCS_STATUS1 0x014
16 #define QPHY_V4_PCS_PCS_STATUS2 0x018
17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c
18 #define QPHY_V4_PCS_PCS_STATUS4 0x020
19 #define QPHY_V4_PCS_PCS_STATUS5 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
/linux/drivers/media/platform/chips-media/coda/
H A Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/linux/drivers/video/fbdev/
H A Dwm8505fb_regs.h15 * Color space select register, default value 0x1c
22 #define WMT_GOVR_COLORSPACE 0x1e4
28 #define WMT_GOVR_COLORSPACE1 0x30
30 #define WMT_GOVR_CONTRAST 0x1b8
31 #define WMT_GOVR_BRGHTNESS 0x1bc /* incompatible with RGB? */
34 #define WMT_GOVR_FBADDR 0x90
35 #define WMT_GOVR_FBADDR1 0x94 /* UV offset in YUV mode */
38 #define WMT_GOVR_XPAN 0xa4
39 #define WMT_GOVR_YPAN 0xa0
41 #define WMT_GOVR_XRES 0x98
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dti,dra7-iodelay.yaml30 const: 0
64 reg = <0x4844a000 0x0d1c>;
66 #size-cells = <0>;
71 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
72 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
73 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
74 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
75 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
76 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
77 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/linux/tools/perf/util/kvm-stat-arch/
H A Dbook3s_hcalls.h9 {0x4, "H_REMOVE"}, \
10 {0x8, "H_ENTER"}, \
11 {0xc, "H_READ"}, \
12 {0x10, "H_CLEAR_MOD"}, \
13 {0x14, "H_CLEAR_REF"}, \
14 {0x18, "H_PROTECT"}, \
15 {0x1c, "H_GET_TCE"}, \
16 {0x20, "H_PUT_TCE"}, \
17 {0x24, "H_SET_SPRG0"}, \
18 {0x28, "H_SET_DABR"}, \
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e-evm-quad-port-eth-exp.dtso67 pinctrl-0 = <&mdio0_pins_default>;
71 #size-cells = <0>;
99 J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
100 J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
124 #size-cells = <0>;
129 #phy-cells = <0>;
/linux/drivers/pci/controller/
H A Dpci-thunder-ecam.c25 v &= 0xff; in set_val()
27 v &= 0xffff; in set_val()
38 int where_a = where & 0xc; in handle_ea_bar()
40 if (where_a == 0) { in handle_ea_bar()
44 if (where_a == 0x4) { in handle_ea_bar()
45 addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */ in handle_ea_bar()
50 v &= ~0xf; in handle_ea_bar()
55 if (where_a == 0x8) { in handle_ea_bar()
59 addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */ in handle_ea_bar()
63 barl_orig = readl(addr + 0); in handle_ea_bar()
[all …]
/linux/drivers/scsi/mvsas/
H A Dmv_64xx.h19 MVS_GBL_CTL = 0x04, /* global control */
20 MVS_GBL_INT_STAT = 0x08, /* global irq status */
21 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
23 MVS_PHY_CTL = 0x40, /* SOC PHY Control */
24 MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
26 MVS_GBL_PORT_TYPE = 0xa0, /* port type */
28 MVS_CTL = 0x100, /* SAS/SATA port configuration */
29 MVS_PCS = 0x104, /* SAS/SATA port control/status */
30 MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
31 MVS_CMD_LIST_HI = 0x10C,
[all …]

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