1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_60_H_ 7 #define QCOM_PHY_QMP_QSERDES_TXRX_V10_60_H_ 8 9 #define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_TX 0x034 10 #define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_RX 0x038 11 #define QSERDES_V10_60_TXRX_LANE_MODE_1 0x080 12 #define QSERDES_V10_60_TXRX_LANE_MODE_2 0x084 13 #define QSERDES_V10_60_TXRX_LANE_MODE_3 0x088 14 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x0c8 15 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x0cc 16 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x0d0 17 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x0d4 18 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x0e0 19 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE2 0x0e4 20 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE3 0x0e8 21 #define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x0ec 22 #define QSERDES_V10_60_TXRX_UCDR_PI_CTRL1 0x12c 23 #define QSERDES_V10_60_TXRX_UCDR_PI_CTRL2 0x130 24 #define QSERDES_V10_60_TXRX_UCDR_PI_CTRL3 0x134 25 #define QSERDES_V10_60_TXRX_UCDR_PI_CTRL4 0x138 26 #define QSERDES_V10_60_TXRX_SVS_MODE_CTRL 0x19c 27 #define QSERDES_V10_60_TXRX_RXCLK_DIV2_CTRL 0x1a0 28 #define QSERDES_V10_60_TXRX_RX_BAND_CTRL0 0x1a4 29 #define QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL0 0x1ac 30 #define QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL1 0x1b0 31 #define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE1 0x1b8 32 #define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE2 0x1bc 33 #define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE3 0x1c0 34 #define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE4 0x1c4 35 #define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE1 0x1d0 36 #define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE2 0x1d4 37 #define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE3 0x1d8 38 #define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE4 0x1dc 39 #define QSERDES_V10_60_TXRX_UCDR_PI_CONTROLS 0x1e4 40 #define QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE3 0x200 41 #define QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE4 0x204 42 #define QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_LSB 0x218 43 #define QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_MSB 0x21c 44 #define QSERDES_V10_60_TXRX_VGA_CAL_CNTRL1 0x280 45 #define QSERDES_V10_60_TXRX_VGA_CAL_MAN_VAL 0x288 46 #define QSERDES_V10_60_TXRX_GM_CAL 0x29c 47 #define QSERDES_V10_60_TXRX_RX_EQU_ADAPTOR_CNTRL6 0x2b8 48 #define QSERDES_V10_60_TXRX_SIGDET_ENABLES 0x2d4 49 #define QSERDES_V10_60_TXRX_SIGDET_CNTRL 0x2d8 50 #define QSERDES_V10_60_TXRX_SIGDET_LVL 0x2dc 51 #define QSERDES_V10_60_TXRX_SIGDET_DEGLITCH_CNTRL 0x2e0 52 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B0 0x314 53 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B1 0x318 54 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B2 0x31c 55 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B3 0x320 56 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B4 0x324 57 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B5 0x328 58 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B6 0x32c 59 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B7 0x330 60 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B8 0x334 61 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B9 0x338 62 #define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B10 0x33c 63 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B0 0x340 64 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B1 0x344 65 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B2 0x348 66 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B3 0x34c 67 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B4 0x350 68 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B5 0x354 69 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B6 0x358 70 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B7 0x35c 71 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B8 0x360 72 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B9 0x364 73 #define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B10 0x368 74 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B0 0x36c 75 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B1 0x370 76 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B2 0x374 77 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B3 0x378 78 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B4 0x37c 79 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B5 0x380 80 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B6 0x384 81 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B7 0x388 82 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B8 0x38c 83 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B9 0x390 84 #define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B10 0x394 85 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B0 0x398 86 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B1 0x39c 87 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B2 0x3a0 88 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B3 0x3a4 89 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B4 0x3a8 90 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B5 0x3ac 91 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B6 0x3b0 92 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B7 0x3b4 93 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B8 0x3b8 94 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B9 0x3bc 95 #define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B10 0x3c0 96 #define QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE32 0x478 97 #define QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE45 0x47c 98 #define QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL1 0x4c8 99 #define QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL2 0x4cc 100 #define QSERDES_V10_60_TXRX_SIGDET_CAL_TRIM 0x4d0 101 #define QSERDES_V10_60_TXRX_TX_BAND0 0x4e8 102 #define QSERDES_V10_60_TXRX_TX_BAND1 0x4ec 103 #define QSERDES_V10_60_TXRX_SEL_10B_8B 0x4f4 104 #define QSERDES_V10_60_TXRX_SEL_20B_10B 0x4f8 105 #define QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE3 0x53c 106 #define QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE4 0x540 107 #define QSERDES_V10_60_TXRX_PHPRE_CTRL 0x5e8 108 109 #endif 110