1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2026, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_ 7 #define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V8_H_ 8 9 #define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_TX (0x34) 10 #define QSERDES_UFS_V8_TX_RES_CODE_LANE_OFFSET_RX (0x38) 11 #define QSERDES_UFS_V8_TX_LANE_MODE_1 (0x80) 12 #define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE2 (0x1bc) 13 #define QSERDES_UFS_V8_RX_UCDR_FO_GAIN_RATE4 (0x1c4) 14 #define QSERDES_UFS_V8_RX_UCDR_SO_GAIN_RATE4 (0x1dc) 15 #define QSERDES_UFS_V8_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (0x2c8) 16 #define QSERDES_UFS_V8_RX_UCDR_PI_CONTROLS (0x1e4) 17 #define QSERDES_UFS_V8_RX_OFFSET_ADAPTOR_CNTRL3 (0x2d0) 18 #define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 (0x120) 19 #define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 (0xd4) 20 #define QSERDES_UFS_V8_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 (0xec) 21 #define QSERDES_UFS_V8_RX_VGA_CAL_MAN_VAL (0x288) 22 #define QSERDES_UFS_V8_RX_EQU_ADAPTOR_CNTRL4 (0x2b0) 23 #define QSERDES_UFS_V8_RX_MODE_RATE_0_1_B4 (0x324) 24 #define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B7 (0x3b4) 25 #define QSERDES_UFS_V8_RX_MODE_RATE4_SA_B9 (0x3bc) 26 #define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B7 (0x3e0) 27 #define QSERDES_UFS_V8_RX_MODE_RATE4_SB_B9 (0x3e8) 28 #define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B7 (0x40c) 29 #define QSERDES_UFS_V8_RX_MODE_RATE5_SA_B9 (0x414) 30 #define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B7 (0x438) 31 #define QSERDES_UFS_V8_RX_MODE_RATE5_SB_B9 (0x440) 32 #define QSERDES_UFS_V8_RX_UCDR_SO_SATURATION (0xf4) 33 #define QSERDES_UFS_V8_RX_TERM_BW_CTRL0 (0x1ac) 34 #define QSERDES_UFS_V8_RX_DLL0_FTUNE_CTRL (0x498) 35 #define QSERDES_UFS_V8_RX_SIGDET_CAL_TRIM (0x4d0) 36 37 #endif 38