10696cc73SMatthew Leung /* SPDX-License-Identifier: GPL-2.0 */ 20696cc73SMatthew Leung /* 30696cc73SMatthew Leung * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 40696cc73SMatthew Leung */ 50696cc73SMatthew Leung 60696cc73SMatthew Leung #ifndef QCOM_PHY_QMP_QSERDES_COM_V10_H_ 70696cc73SMatthew Leung #define QCOM_PHY_QMP_QSERDES_COM_V10_H_ 80696cc73SMatthew Leung 90696cc73SMatthew Leung /* Only for QMP V10 PHY - QSERDES COM registers */ 10*eca0e717SRonak Raheja 110696cc73SMatthew Leung #define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1 0x00 120696cc73SMatthew Leung #define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1 0x04 130696cc73SMatthew Leung #define QSERDES_V10_COM_CP_CTRL_MODE1 0x10 140696cc73SMatthew Leung #define QSERDES_V10_COM_PLL_RCTRL_MODE1 0x14 150696cc73SMatthew Leung #define QSERDES_V10_COM_PLL_CCTRL_MODE1 0x18 160696cc73SMatthew Leung #define QSERDES_V10_COM_CORECLK_DIV_MODE1 0x1c 170696cc73SMatthew Leung #define QSERDES_V10_COM_LOCK_CMP1_MODE1 0x20 180696cc73SMatthew Leung #define QSERDES_V10_COM_LOCK_CMP2_MODE1 0x24 190696cc73SMatthew Leung #define QSERDES_V10_COM_DEC_START_MODE1 0x28 20*eca0e717SRonak Raheja #define QSERDES_V10_COM_DEC_START_MSB_MODE1 0x2c 210696cc73SMatthew Leung #define QSERDES_V10_COM_DIV_FRAC_START1_MODE1 0x30 220696cc73SMatthew Leung #define QSERDES_V10_COM_DIV_FRAC_START2_MODE1 0x34 230696cc73SMatthew Leung #define QSERDES_V10_COM_DIV_FRAC_START3_MODE1 0x38 240696cc73SMatthew Leung #define QSERDES_V10_COM_HSCLK_SEL_1 0x3c 25*eca0e717SRonak Raheja #define QSERDES_V10_COM_INTEGLOOP_GAIN0_MODE1 0x40 26*eca0e717SRonak Raheja #define QSERDES_V10_COM_INTEGLOOP_GAIN1_MODE1 0x44 27*eca0e717SRonak Raheja #define QSERDES_V10_COM_VCO_TUNE1_MODE1 0x48 28*eca0e717SRonak Raheja #define QSERDES_V10_COM_VCO_TUNE2_MODE1 0x4c 29*eca0e717SRonak Raheja #define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50 30*eca0e717SRonak Raheja #define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54 31*eca0e717SRonak Raheja #define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58 32*eca0e717SRonak Raheja #define QSERDES_V10_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c 330696cc73SMatthew Leung #define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0 0x60 340696cc73SMatthew Leung #define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0 0x64 350696cc73SMatthew Leung #define QSERDES_V10_COM_CP_CTRL_MODE0 0x70 360696cc73SMatthew Leung #define QSERDES_V10_COM_PLL_RCTRL_MODE0 0x74 370696cc73SMatthew Leung #define QSERDES_V10_COM_PLL_CCTRL_MODE0 0x78 38*eca0e717SRonak Raheja #define QSERDES_V10_COM_PLL_CORE_CLK_DIV_MODE0 0x7c 390696cc73SMatthew Leung #define QSERDES_V10_COM_LOCK_CMP1_MODE0 0x80 400696cc73SMatthew Leung #define QSERDES_V10_COM_LOCK_CMP2_MODE0 0x84 410696cc73SMatthew Leung #define QSERDES_V10_COM_DEC_START_MODE0 0x88 42*eca0e717SRonak Raheja #define QSERDES_V10_COM_DEC_START_MSB_MODE0 0x8c 430696cc73SMatthew Leung #define QSERDES_V10_COM_DIV_FRAC_START1_MODE0 0x90 440696cc73SMatthew Leung #define QSERDES_V10_COM_DIV_FRAC_START2_MODE0 0x94 450696cc73SMatthew Leung #define QSERDES_V10_COM_DIV_FRAC_START3_MODE0 0x98 46*eca0e717SRonak Raheja #define QSERDES_V10_COM_HSCLK_HS_SWITCH_SEL_1 0x9c 47*eca0e717SRonak Raheja #define QSERDES_V10_COM_INTEGLOOP_GAIN0_MODE0 0xa0 48*eca0e717SRonak Raheja #define QSERDES_V10_COM_INTEGLOOP_GAIN1_MODE0 0xa4 49*eca0e717SRonak Raheja #define QSERDES_V10_COM_VCO_TUNE1_MODE0 0xa8 50*eca0e717SRonak Raheja #define QSERDES_V10_COM_VCO_TUNE2_MODE0 0xac 510696cc73SMatthew Leung #define QSERDES_V10_COM_BG_TIMER 0xbc 520696cc73SMatthew Leung #define QSERDES_V10_COM_SSC_EN_CENTER 0xc0 53*eca0e717SRonak Raheja #define QSERDES_V10_COM_SSC_ADJ_PER1 0xc4 540696cc73SMatthew Leung #define QSERDES_V10_COM_SSC_PER1 0xcc 550696cc73SMatthew Leung #define QSERDES_V10_COM_SSC_PER2 0xd0 56*eca0e717SRonak Raheja #define QSERDES_V10_COM_POST_DIV_MUX 0xd8 57*eca0e717SRonak Raheja #define QSERDES_V10_COM_BIAS_EN_CLKBUFLR_EN 0xdc 580696cc73SMatthew Leung #define QSERDES_V10_COM_CLK_ENABLE1 0xe0 590696cc73SMatthew Leung #define QSERDES_V10_COM_SYS_CLK_CTRL 0xe4 60*eca0e717SRonak Raheja #define QSERDES_V10_COM_SYSCLK_BUF_ENABLE 0xe8 610696cc73SMatthew Leung #define QSERDES_V10_COM_PLL_IVCO 0xf4 62*eca0e717SRonak Raheja #define QSERDES_V10_COM_PLL_IVCO_MODE1 0xf8 63*eca0e717SRonak Raheja #define QSERDES_V10_COM_CMN_IETRIM 0xfc 64*eca0e717SRonak Raheja #define QSERDES_V10_COM_CMN_IPTRIM 0x100 650696cc73SMatthew Leung #define QSERDES_V10_COM_SYSCLK_EN_SEL 0x110 66*eca0e717SRonak Raheja #define QSERDES_V10_COM_RESETSM_CNTRL 0x118 670696cc73SMatthew Leung #define QSERDES_V10_COM_LOCK_CMP_EN 0x120 68*eca0e717SRonak Raheja #define QSERDES_V10_COM_LOCK_CMP_CFG 0x124 69*eca0e717SRonak Raheja #define QSERDES_V10_COM_VCO_TUNE_CTRL 0x13c 700696cc73SMatthew Leung #define QSERDES_V10_COM_VCO_TUNE_MAP 0x140 71*eca0e717SRonak Raheja #define QSERDES_V10_COM_VCO_TUNE_INITVAL2 0x148 72*eca0e717SRonak Raheja #define QSERDES_V10_COM_VCO_TUNE_MAXVAL2 0x158 730696cc73SMatthew Leung #define QSERDES_V10_COM_CLK_SELECT 0x164 740696cc73SMatthew Leung #define QSERDES_V10_COM_CORE_CLK_EN 0x170 750696cc73SMatthew Leung #define QSERDES_V10_COM_CMN_CONFIG_1 0x174 76*eca0e717SRonak Raheja #define QSERDES_V10_COM_SVS_MODE_CLK_SEL 0x17c 77*eca0e717SRonak Raheja #define QSERDES_V10_COM_CMN_MISC_1 0x184 78*eca0e717SRonak Raheja #define QSERDES_V10_COM_CMN_MODE 0x188 79*eca0e717SRonak Raheja #define QSERDES_V10_COM_PLL_VCO_DC_LEVEL_CTRL 0x198 80*eca0e717SRonak Raheja #define QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4 81*eca0e717SRonak Raheja #define QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8 82*eca0e717SRonak Raheja #define QSERDES_V10_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac 83*eca0e717SRonak Raheja #define QSERDES_V10_COM_ADDITIONAL_MISC 0x1b4 84*eca0e717SRonak Raheja #define QSERDES_V10_COM_ADDITIONAL_MISC_2 0x1b8 850696cc73SMatthew Leung #define QSERDES_V10_COM_ADDITIONAL_MISC_3 0x1bc 86*eca0e717SRonak Raheja #define QSERDES_V10_COM_CMN_STATUS 0x2c8 87*eca0e717SRonak Raheja #define QSERDES_V10_COM_C_READY_STATUS 0x2f0 880696cc73SMatthew Leung 890696cc73SMatthew Leung #endif 90