xref: /linux/Documentation/devicetree/bindings/pinctrl/ti,dra7-iodelay.yaml (revision cf9610f9116d55c5a66ef9f1faecacabd93a9322) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/ti,dra7-iodelay.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Pin configuration for TI IODELAY controller
8
9maintainers:
10  - Nishanth Menon <nm@ti.com>
11  - Bhargav Joshi <j.bhargav.u@gmail.com>
12
13description:
14  TI dra7 based SoCs such as am57xx have a controller for setting the IO delay
15  for each pin. For most part the IO delay values are programmed by the
16  bootloader, but some pins need to be configured dynamically by the kernel such
17  as the MMC pins.
18
19properties:
20  compatible:
21    const: ti,dra7-iodelay
22
23  reg:
24    maxItems: 1
25
26  '#address-cells':
27    const: 1
28
29  '#size-cells':
30    const: 0
31
32  '#pinctrl-cells':
33    const: 2
34
35patternProperties:
36  ^.*_conf$:
37    type: object
38    additionalProperties: false
39
40    properties:
41      pinctrl-pin-array:
42        $ref: /schemas/types.yaml#/definitions/uint32-array
43        description: |
44          An array of 32-bit integers defining the pin delay configuration.
45
46    required:
47      - pinctrl-pin-array
48
49required:
50  - compatible
51  - reg
52  - '#address-cells'
53  - '#size-cells'
54  - '#pinctrl-cells'
55
56additionalProperties: false
57
58examples:
59  - |
60    #include <dt-bindings/pinctrl/dra.h>
61
62    padconf@4844a000 {
63        compatible = "ti,dra7-iodelay";
64        reg = <0x4844a000 0x0d1c>;
65        #address-cells = <1>;
66        #size-cells = <0>;
67        #pinctrl-cells = <2>;
68
69        mmc2_iodelay_3v3_conf {
70            pinctrl-pin-array = <
71            0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
72            0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
73            0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
74            0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
75            0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
76            0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
77            0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
78            0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
79            0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */
80            0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */
81            >;
82        };
83    };
84