3  * AMD L3 cache_disable_{0,1} sysfs handling
23 	u32 val = 0;  in amd_calc_l3_indices()
25 	pci_read_config_dword(nb->misc, 0x1C4, &val);  in amd_calc_l3_indices()
28 	l3->subcaches[0] = sc0 = !(val & BIT(0));  in amd_calc_l3_indices()
31 	if (boot_cpu_data.x86 == 0x15) {  in amd_calc_l3_indices()
32 		l3->subcaches[0] = sc0 += !(val & BIT(1));  in amd_calc_l3_indices()
45  * @slot: slot number (0..1)
51 	unsigned int reg = 0;  in amd_get_l3_disable_slot()
53 	pci_read_config_dword(nb->misc, 0x1BC + slot * 4, &reg);  in amd_get_l3_disable_slot()
57 		return reg & 0xfff;  in amd_get_l3_disable_slot()
68 	if (index >= 0)  in show_cache_disable()
83 SHOW_CACHE_DISABLE(0)
96 	for (i = 0; i < 4; i++) {  in amd_l3_disable_index()
102 		pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg);  in amd_l3_disable_index()
112 		pci_write_config_dword(nb->misc, 0x1BC + slot * 4, reg);  in amd_l3_disable_index()
121  * @slot:  slot number (0..1)
124  * @return: 0 on success, error status on failure
129 	int ret = 0;  in amd_set_l3_disable_slot()
133 	if (ret >= 0)  in amd_set_l3_disable_slot()
145 	return 0;  in amd_set_l3_disable_slot()
152 	unsigned long val = 0;  in store_cache_disable()
153 	int cpu, err = 0;  in store_cache_disable()
160 	if (kstrtoul(buf, 10, &val) < 0)  in store_cache_disable()
183 STORE_CACHE_DISABLE(0)
206 	if (kstrtoul(buf, 16, &val) < 0)  in subcaches_store()
227 		return 0;  in cache_private_attrs_is_visible()
238 	return 0;  in cache_private_attrs_is_visible()
262 	n = 0;  in init_amd_l3_attrs()