1*7716c99fSBhargav Joshi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*7716c99fSBhargav Joshi%YAML 1.2 3*7716c99fSBhargav Joshi--- 4*7716c99fSBhargav Joshi$id: http://devicetree.org/schemas/pinctrl/ti,dra7-iodelay.yaml# 5*7716c99fSBhargav Joshi$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7716c99fSBhargav Joshi 7*7716c99fSBhargav Joshititle: Pin configuration for TI IODELAY controller 8*7716c99fSBhargav Joshi 9*7716c99fSBhargav Joshimaintainers: 10*7716c99fSBhargav Joshi - Nishanth Menon <nm@ti.com> 11*7716c99fSBhargav Joshi - Bhargav Joshi <j.bhargav.u@gmail.com> 12*7716c99fSBhargav Joshi 13*7716c99fSBhargav Joshidescription: 14*7716c99fSBhargav Joshi TI dra7 based SoCs such as am57xx have a controller for setting the IO delay 15*7716c99fSBhargav Joshi for each pin. For most part the IO delay values are programmed by the 16*7716c99fSBhargav Joshi bootloader, but some pins need to be configured dynamically by the kernel such 17*7716c99fSBhargav Joshi as the MMC pins. 18*7716c99fSBhargav Joshi 19*7716c99fSBhargav Joshiproperties: 20*7716c99fSBhargav Joshi compatible: 21*7716c99fSBhargav Joshi const: ti,dra7-iodelay 22*7716c99fSBhargav Joshi 23*7716c99fSBhargav Joshi reg: 24*7716c99fSBhargav Joshi maxItems: 1 25*7716c99fSBhargav Joshi 26*7716c99fSBhargav Joshi '#address-cells': 27*7716c99fSBhargav Joshi const: 1 28*7716c99fSBhargav Joshi 29*7716c99fSBhargav Joshi '#size-cells': 30*7716c99fSBhargav Joshi const: 0 31*7716c99fSBhargav Joshi 32*7716c99fSBhargav Joshi '#pinctrl-cells': 33*7716c99fSBhargav Joshi const: 2 34*7716c99fSBhargav Joshi 35*7716c99fSBhargav JoshipatternProperties: 36*7716c99fSBhargav Joshi ^.*_conf$: 37*7716c99fSBhargav Joshi type: object 38*7716c99fSBhargav Joshi additionalProperties: false 39*7716c99fSBhargav Joshi 40*7716c99fSBhargav Joshi properties: 41*7716c99fSBhargav Joshi pinctrl-pin-array: 42*7716c99fSBhargav Joshi $ref: /schemas/types.yaml#/definitions/uint32-array 43*7716c99fSBhargav Joshi description: | 44*7716c99fSBhargav Joshi An array of 32-bit integers defining the pin delay configuration. 45*7716c99fSBhargav Joshi 46*7716c99fSBhargav Joshi required: 47*7716c99fSBhargav Joshi - pinctrl-pin-array 48*7716c99fSBhargav Joshi 49*7716c99fSBhargav Joshirequired: 50*7716c99fSBhargav Joshi - compatible 51*7716c99fSBhargav Joshi - reg 52*7716c99fSBhargav Joshi - '#address-cells' 53*7716c99fSBhargav Joshi - '#size-cells' 54*7716c99fSBhargav Joshi - '#pinctrl-cells' 55*7716c99fSBhargav Joshi 56*7716c99fSBhargav JoshiadditionalProperties: false 57*7716c99fSBhargav Joshi 58*7716c99fSBhargav Joshiexamples: 59*7716c99fSBhargav Joshi - | 60*7716c99fSBhargav Joshi #include <dt-bindings/pinctrl/dra.h> 61*7716c99fSBhargav Joshi 62*7716c99fSBhargav Joshi padconf@4844a000 { 63*7716c99fSBhargav Joshi compatible = "ti,dra7-iodelay"; 64*7716c99fSBhargav Joshi reg = <0x4844a000 0x0d1c>; 65*7716c99fSBhargav Joshi #address-cells = <1>; 66*7716c99fSBhargav Joshi #size-cells = <0>; 67*7716c99fSBhargav Joshi #pinctrl-cells = <2>; 68*7716c99fSBhargav Joshi 69*7716c99fSBhargav Joshi mmc2_iodelay_3v3_conf { 70*7716c99fSBhargav Joshi pinctrl-pin-array = < 71*7716c99fSBhargav Joshi 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ 72*7716c99fSBhargav Joshi 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ 73*7716c99fSBhargav Joshi 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ 74*7716c99fSBhargav Joshi 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ 75*7716c99fSBhargav Joshi 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ 76*7716c99fSBhargav Joshi 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ 77*7716c99fSBhargav Joshi 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ 78*7716c99fSBhargav Joshi 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ 79*7716c99fSBhargav Joshi 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ 80*7716c99fSBhargav Joshi 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ 81*7716c99fSBhargav Joshi >; 82*7716c99fSBhargav Joshi }; 83*7716c99fSBhargav Joshi }; 84