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/linux/arch/powerpc/boot/dts/
H A Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-am64.dtsi54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
58 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
63 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
H A Dk3-j721e-evm-pcie0-ep.dtso34 reg = <0x00 0x02900000 0x00 0x1000>,
35 <0x00 0x02907000 0x00 0x400>,
36 <0x00 0x0d000000 0x00 0x00800000>,
37 <0x00 0x10000000 0x00 0x08000000>;
41 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
48 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
H A Dk3-j722s.dtsi24 #size-cells = <0>;
46 cpu0: cpu@0 {
48 reg = <0x000>;
51 i-cache-size = <0x8000>;
54 d-cache-size = <0x8000>;
58 clocks = <&k3_clks 135 0>;
63 reg = <0x001>;
66 i-cache-size = <0x8000>;
69 d-cache-size = <0x8000>;
73 clocks = <&k3_clks 136 0>;
[all …]
H A Dk3-j784s4-evm-pcie0-pcie1-ep.dtso38 reg = <0x00 0x02900000 0x00 0x1000>,
39 <0x00 0x02907000 0x00 0x400>,
40 <0x00 0x0d000000 0x00 0x00800000>,
41 <0x00 0x10000000 0x00 0x08000000>;
45 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
49 clocks = <&k3_clks 332 0>;
52 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
60 reg = <0x00 0x02910000 0x00 0x1000>,
61 <0x00 0x02917000 0x00 0x400>,
62 <0x00 0x0d800000 0x00 0x00800000>,
[all …]
H A Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j722s-main.dtsi12 serdes_refclk: clk-0 {
14 #clock-cells = <0>;
15 clock-frequency = <0>;
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
37 reg = <0x0f000000 0x00010000>;
39 resets = <&serdes_wiz0 0>;
51 #size-cells = <0>;
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
[all …]
/linux/arch/sh/configs/
H A Dhp6xx_defconfig8 CONFIG_MEMORY_START=0x0d000000
9 CONFIG_MEMORY_SIZE=0x00400000
/linux/arch/xtensa/boot/dts/
H A Dcsp.dts11 …bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw e…
14 memory@0 {
16 reg = <0x00000000 0x40000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
36 #clock-cells = <0>;
45 ranges = <0x00000000 0xf0000000 0x10000000>;
47 uart0: serial@0d000000 {
51 reg = <0x0d000000 0x1000>;
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-ep.yaml127 reg = <0x00 0x02900000 0x00 0x1000>,
128 <0x00 0x02907000 0x00 0x400>,
129 <0x00 0x0d000000 0x00 0x00800000>,
130 <0x00 0x10000000 0x00 0x08000000>;
132 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
H A Dti,j721e-pci-host.yaml78 const: 0x104c
82 - 0xb00d
83 - 0xb00f
84 - 0xb010
85 - 0xb012
86 - 0xb013
177 reg = <0x00 0x02900000 0x00 0x1000>,
178 <0x00 0x02907000 0x00 0x400>,
179 <0x00 0x0d000000 0x00 0x00800000>,
180 <0x00 0x10000000 0x00 0x00001000>;
[all …]
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/linux/arch/arm/nwfpe/
H A Dentry.S50 EmulateAll returns 1 if the emulation was successful, or 0 if not.
83 cmp r0, #0 @ was emulation successful
91 and r2, r6, #0x0F000000 @ test for FP insns
92 teq r2, #0x0C000000
93 teqne r2, #0x0D000000
94 teqne r2, #0x0E000000
138 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
140 and r8, r0, #0x00000f00 @ mask out CP number
144 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
152 ret lr @ CP#0
/linux/arch/powerpc/platforms/embedded6xx/
H A Dusbgecko_udbg.c23 #define EXI_CSR 0x00
24 #define EXI_CSR_CLKMASK (0x7<<4)
26 #define EXI_CSR_CSMASK (0x7<<7)
27 #define EXI_CSR_CS_0 (0x1<<7) /* Chip Select 001 */
29 #define EXI_CR 0x0c
30 #define EXI_CR_TSTART (1<<0)
35 #define EXI_DATA 0x10
67 out_be32(csr_reg, 0); in ug_io_transaction()
81 return 0; in ug_is_adapter_present()
83 return ug_io_transaction(0x90000000) == 0x04700000; in ug_is_adapter_present()
[all …]
/linux/drivers/crypto/chelsio/
H A Dchcr_crypto.h63 #define CHCR_ENCRYPT_OP 0
72 #define CHCR_SCMD_AUTH_CTRL_AUTH_CIPHER 0
75 #define CHCR_SCMD_CIPHER_MODE_NOP 0
83 #define CHCR_SCMD_AUTH_MODE_NOP 0
95 #define CHCR_SCMD_HMAC_CTRL_NOP 0
103 #define VERIFY_HW 0
106 #define CHCR_SCMD_IVGEN_CTRL_HW 0
111 #define CHCR_KEYCTX_MAC_KEY_SIZE_128 0
116 #define CHCR_KEYCTX_CIPHER_KEY_SIZE_128 0
128 #define IV_NOP 0
[all …]
/linux/arch/mips/alchemy/devboards/
H A Ddb1000.c50 return 0; in db1000_board_setup()
57 if ((slot < 12) || (slot > 13) || pin == 0) in db1500_map_pci_irq()
60 return (pin == 1) ? AU1500_PCI_INTA : 0xff; in db1500_map_pci_irq()
75 [0] = {
77 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
89 .id = 0,
100 [0] = {
102 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
114 .id = 0,
124 [0] = {
[all …]
/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
36 interrupt-map-mask = <0 0 0 0>;
37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
39 bus-range = <0x00 0xff>;
43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c54 #define FIJI_SMC_SIZE 0x20000
58 #define MC_CG_ARB_FREQ_F1 0x0b
64 {600, 1050, 3, 0}, {600, 1050, 6, 1} };
70 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
73 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
77 {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
81 {1, 0xF, 0xFD,
83 0x19, 5, 45}
89 …0x3c0fd047, 0x30750000, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000…
90 …0xa00fd047, 0x409c0000, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0x21680000, 0x11000000…
[all …]
/linux/drivers/scsi/lpfc/
H A Dlpfc_hw.h23 #define FDMI_DID 0xfffffaU
24 #define NameServer_DID 0xfffffcU
25 #define Fabric_Cntl_DID 0xfffffdU
26 #define Fabric_DID 0xfffffeU
27 #define Bcast_DID 0xffffffU
28 #define Mask_DID 0xffffffU
29 #define CT_DID_MASK 0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
42 0 */
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c63 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
64 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
65 #define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002
66 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
78 #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK 0x00000001L
79 #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK 0x00000002L
80 #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK 0x00000004L
81 #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK 0x00000008L
82 #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK 0x00000010L
83 #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK 0x00000020L
[all …]

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