Lines Matching +full:0 +full:x0d000000
25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
114 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
115 <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
116 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
117 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
118 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
119 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
120 <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, /* MSMC RAM */
121 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
122 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
125 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
126 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
127 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
128 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
129 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
130 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
131 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
132 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
133 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
134 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
135 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
136 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
137 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
143 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
144 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
145 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
146 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
147 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
148 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
149 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
150 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
151 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
152 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
153 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
154 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
155 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */