1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/** 3 * DT Overlay for enabling PCIE0 and PCIE1 instances in Endpoint Configuration 4 * on J784S4 EVM. 5 * 6 * J784S4 EVM Product Link: https://www.ti.com/tool/J784S4XEVM 7 * 8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ 9 */ 10 11/dts-v1/; 12/plugin/; 13 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/soc/ti,sci_pm_domain.h> 16 17#include "k3-pinctrl.h" 18 19/* 20 * Since Root Complex and Endpoint modes are mutually exclusive 21 * disable Root Complex mode. 22 */ 23&pcie0_rc { 24 status = "disabled"; 25}; 26 27&pcie1_rc { 28 status = "disabled"; 29}; 30 31&cbass_main { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 interrupt-parent = <&gic500>; 35 36 pcie0_ep: pcie-ep@2900000 { 37 compatible = "ti,j784s4-pcie-ep"; 38 reg = <0x00 0x02900000 0x00 0x1000>, 39 <0x00 0x02907000 0x00 0x400>, 40 <0x00 0x0d000000 0x00 0x00800000>, 41 <0x00 0x10000000 0x00 0x08000000>; 42 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 43 interrupt-names = "link_state"; 44 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 45 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 46 max-link-speed = <3>; 47 num-lanes = <4>; 48 power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; 49 clocks = <&k3_clks 332 0>; 50 clock-names = "fck"; 51 max-functions = /bits/ 8 <6>; 52 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 53 dma-coherent; 54 phys = <&serdes1_pcie0_link>; 55 phy-names = "pcie-phy"; 56 }; 57 58 pcie1_ep: pcie-ep@2910000 { 59 compatible = "ti,j784s4-pcie-ep"; 60 reg = <0x00 0x02910000 0x00 0x1000>, 61 <0x00 0x02917000 0x00 0x400>, 62 <0x00 0x0d800000 0x00 0x00800000>, 63 <0x00 0x18000000 0x00 0x08000000>; 64 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 65 interrupt-names = "link_state"; 66 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 67 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; 68 max-link-speed = <3>; 69 num-lanes = <2>; 70 power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; 71 clocks = <&k3_clks 333 0>; 72 clock-names = "fck"; 73 max-functions = /bits/ 8 <6>; 74 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 75 dma-coherent; 76 phys = <&serdes0_pcie1_link>; 77 phy-names = "pcie-phy"; 78 }; 79}; 80