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12

/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap36xx-clocks.dtsi9 #clock-cells = <0>;
12 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
16 #clock-cells = <0>;
19 ti,bit-shift = <0x1e>;
20 reg = <0x0d00>;
26 #clock-cells = <0>;
29 ti,bit-shift = <0x1b>;
30 reg = <0x0d00>;
35 #clock-cells = <0>;
38 ti,bit-shift = <0xc>;
[all …]
H A Domap3xxx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
18 reg = <0x0d40>;
22 #clock-cells = <0>;
27 reg = <0x1270>;
32 #clock-cells = <0>;
35 reg = <0x0d70>;
40 #clock-cells = <0>;
48 #clock-cells = <0>;
56 #clock-cells = <0>;
[all …]
/freebsd/sys/arm/ti/
H A Dti_pruss.h32 #define PRUSS_AM18XX_INTC 0x04000
33 #define PRUSS_AM18XX_REV 0x4e825900
34 #define PRUSS_AM33XX_REV 0x4e82A900
35 #define PRUSS_AM33XX_INTC 0x20000
37 #define PRUSS_INTC_GER (PRUSS_AM33XX_INTC + 0x0010)
38 #define PRUSS_INTC_SISR (PRUSS_AM33XX_INTC + 0x0020)
39 #define PRUSS_INTC_SICR (PRUSS_AM33XX_INTC + 0x0024)
40 #define PRUSS_INTC_EISR (PRUSS_AM33XX_INTC + 0x0028)
41 #define PRUSS_INTC_EICR (PRUSS_AM33XX_INTC + 0x002C)
42 #define PRUSS_INTC_HIEISR (PRUSS_AM33XX_INTC + 0x0034)
[all …]
/freebsd/sys/arm64/include/
H A Dcmn600_reg.h34 #define CMN600_COMMON_PMU_EVENT_SEL 0x2000 /* rw */
36 #define CMN600_COMMON_PMU_EVENT_SEL_OCC_MASK (0x7UL << 32)
68 #define POR_CFGM_NODE_INFO 0x0000 /* ro */
69 #define POR_CFGM_NODE_INFO_LOGICAL_ID_MASK 0xffff00000000UL
71 #define POR_CFGM_NODE_INFO_NODE_ID_MASK 0xffff0000
73 #define POR_CFGM_NODE_INFO_NODE_TYPE_MASK 0xffff
74 #define POR_CFGM_NODE_INFO_NODE_TYPE_SHIFT 0
76 #define NODE_ID_SUB_MASK 0x3
77 #define NODE_ID_SUB_SHIFT 0
78 #define NODE_ID_PORT_MASK 0x4
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dti,gate-clock.yaml46 const: 0
61 default: 0
99 #size-cells = <0>;
102 #clock-cells = <0>;
105 reg = <0x0a00>;
111 reg = <0x0d00>;
112 #clock-cells = <0>;
114 ti,bit-shift = <0x1b>;
121 #clock-cells = <0>;
H A Dgate.txt31 - #clock-cells : from common clock binding; shall be set to 0
45 #clock-cells = <0>;
48 reg = <0x0a00>;
53 #clock-cells = <0>;
56 reg = <0x0a00>;
61 #clock-cells = <0>;
64 reg = <0x0e00>;
65 ti,bit-shift = <0>;
69 #clock-cells = <0>;
72 reg = <0x059c>;
[all …]
/freebsd/sys/powerpc/include/
H A Dtrap.h39 #define EXC_RSVD 0x0000 /* Reserved */
40 #define EXC_RST 0x0100 /* Reset; all but IBM4xx */
41 #define EXC_MCHK 0x0200 /* Machine Check */
42 #define EXC_DSI 0x0300 /* Data Storage Interrupt */
43 #define EXC_DSE 0x0380 /* Data Segment Interrupt */
44 #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
45 #define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
46 #define EXC_EXI 0x0500 /* External Interrupt */
47 #define EXC_ALI 0x0600 /* Alignment Interrupt */
48 #define EXC_PGM 0x0700 /* Program Interrupt */
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8723d.h14 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
18 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
20 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
22 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
24 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
26 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
28 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
30 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
[all...]
H A Drtw8723x.h28 IQK_ROUND_INVALID = 0xff,
45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 res4[48]; /* 0xd0 */
54 u8 vendor_id[2]; /* 0x100 */
55 u8 product_id[2]; /* 0x102 */
56 u8 usb_option; /* 0x104 */
57 u8 res5[2]; /* 0x105 */
58 u8 mac_addr[ETH_ALEN]; /* 0x107 */
62 u8 res4[0x4a]; /* 0xd0 */
63 u8 mac_addr[ETH_ALEN]; /* 0x11a */
[all …]
H A Dreg.h8 #define REG_SYS_FUNC_EN 0x0002
15 #define BIT_FEN_BB_RSTB BIT(0)
18 #define REG_SYS_PW_CTRL 0x0004
21 #define REG_APS_FSMCO 0x0004
25 #define REG_SYS_CLK_CTRL 0x0008
28 #define REG_SYS_CLKR 0x0008
33 #define REG_RSV_CTRL 0x001C
34 #define DISABLE_PI 0x3
35 #define ENABLE_PI 0x2
37 #define BIT_WLMCU_IOIF BIT(0)
[all …]
H A Ddebug.c140 return 0; in rtw_debugfs_close()
178 seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); in rtw_debugfs_get_read_reg()
182 seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); in rtw_debugfs_get_read_reg()
186 seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); in rtw_debugfs_get_read_reg()
189 return 0; in rtw_debugfs_get_read_reg()
207 seq_printf(m, "rf_read path:%d addr:0x%08x mask:0x%08x val=0x%08x\n", in rtw_debugfs_get_rf_read()
210 return 0; in rtw_debugfs_get_rf_read()
222 return 0; in rtw_debugfs_get_fix_rate()
226 return 0; in rtw_debugfs_get_fix_rate()
235 memset(tmp, 0, size); in rtw_debugfs_copy_from_user()
[all …]
/freebsd/sys/arm/ti/cpsw/
H A Dif_cpswreg.h32 #define CPSW_SS_OFFSET 0x0000
33 #define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
34 #define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
35 #define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
36 #define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
37 #define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
39 #define CPSW_PORT_OFFSET 0x0100
40 #define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
41 #define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
42 #define CPSW_PORT_P_VLAN(p) (CPSW_PORT_OFFSET + 0x14 + ((p) * 0x100))
[all …]
/freebsd/sys/dev/eqos/
H A Dif_eqos_reg.h38 #define GMAC_MAC_CONFIGURATION 0x0000
49 #define GMAC_MAC_CONFIGURATION_RE (1U << 0)
50 #define GMAC_MAC_EXT_CONFIGURATION 0x0004
51 #define GMAC_MAC_PACKET_FILTER 0x0008
59 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0)
60 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C
61 #define GMAC_MAC_HASH_TABLE_REG0 0x0010
62 #define GMAC_MAC_HASH_TABLE_REG1 0x0014
63 #define GMAC_MAC_VLAN_TAG 0x0050
64 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070
[all …]
/freebsd/sys/arm64/arm64/
H A Dgic_v3_reg.h40 #define GIC_PRIORITY_MAX (0x00UL)
42 #define GIC_PRIORITY_MIN (0xFCUL)
53 #define GICD_CTLR_G1 (1 << 0)
64 #define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1)
69 #define GICD_STATUSR 0x0010
71 #define GICD_SETSPI_NSR 0x0040
72 #define GICD_CLRSPI_NSR 0x0048
73 #define GICD_SETSPI_SR 0x0050
74 #define GICD_CLRSPI_SR 0x0058
75 #define GICD_SPI_INTID_MASK 0x3ff
[all …]
/freebsd/sys/dev/mii/
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DUnicode.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
28 // https://unicode.org/Public/15.1.0/ucdxml/ in isPrintable()
30 {0x0020, 0x007E}, {0x00A0, 0x00AC}, {0x00AE, 0x0377}, in isPrintable()
31 {0x037A, 0x037 in isPrintable()
[all...]
/freebsd/contrib/less/
H A Dcompose.uni1 /* Generated by "./mkutable -f2 Mn Me -- unicode/UnicodeData.txt" on Aug 11 0:27:25 GMT 2025 */
2 { 0x0300, 0x036f }, /* Mn */
3 { 0x0483, 0x0487 }, /* Mn */
4 { 0x0488, 0x0489 }, /* Me */
5 { 0x0591, 0x05bd }, /* Mn */
6 { 0x05bf, 0x05bf }, /* Mn */
7 { 0x05c1, 0x05c2 }, /* Mn */
8 { 0x05c4, 0x05c5 }, /* Mn */
9 { 0x05c7, 0x05c7 }, /* Mn */
10 { 0x0610, 0x061a }, /* Mn */
[all …]
/freebsd/usr.sbin/bhyve/
H A Dpci_emul.c66 #define CONF1_ADDR_PORT 0x0cf8
67 #define CONF1_DATA_PORT 0x0cfc
69 #define CONF1_ENABLE 0x80000000ul
132 #define PCI_EMUL_IOBASE 0x2000
133 #define PCI_EMUL_IOLIMIT 0x10000
134 #define PCI_EMUL_IOMASK 0xffff
136 * OVMF always uses 0xc0000000 as base address for 32 bit PCI MMIO. Don't
139 #define PCI_EMUL_MEMBASE32 0xc0000000
141 #define PCI_EMUL_IOBASE 0xdf000000UL
142 #define PCI_EMUL_IOLIMIT 0xe0000000UL
[all …]
/freebsd/sys/dev/sk/
H A Dif_skreg.h54 #define SK_GENESIS 0x0A
55 #define SK_YUKON 0xB0
56 #define SK_YUKON_LITE 0xB1
57 #define SK_YUKON_LP 0xB2
58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
61 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
62 #define SK_YUKON_LITE_REV_A1 0x3
63 #define SK_YUKON_LITE_REV_A3 0x7
68 #define VENDORID_SK 0x1148
73 #define VENDORID_MARVELL 0x11AB
[all …]
/freebsd/sys/dev/axgbe/
H A Dxgbe-common.h121 #define DMA_MR 0x3000
122 #define DMA_SBMR 0x3004
123 #define DMA_ISR 0x3008
124 #define DMA_AXIARCR 0x3010
125 #define DMA_AXIAWCR 0x3018
126 #define DMA_AXIAWARCR 0x301c
127 #define DMA_DSR0 0x3020
128 #define DMA_DSR1 0x3024
129 #define DMA_DSR2 0x3028
130 #define DMA_DSR3 0x302
[all...]
/freebsd/sys/dev/e1000/
H A De1000_defines.h44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
46 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
47 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
48 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/freebsd/sys/dev/igc/
H A Digc_defines.h16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
18 #define IGC_WUC_PME_STATUS 0x00000004 /* PME Status */
19 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
20 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8550.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #size-cells = <0>;
69 cpu0: cpu@0 {
72 reg = <0 0>;
73 clocks = <&cpufreq_hw 0>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0 0x100>;
[all …]
/freebsd/sys/dev/bxe/
H A Decore_reg.h35 (0x1<<0)
37 (0x1<<2)
39 (0x1<<5)
41 (0x1<<3)
43 (0x1<<4)
45 (0x1<<1)
47 0x1100bcUL
49 0x1101c0UL
51 0x1101d8UL
53 0x1101d0UL
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_tables.c84 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
85 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
86 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
87 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
88 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
90 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
91 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
92 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
93 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]

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