Lines Matching +full:0 +full:x0d00
66 #define CONF1_ADDR_PORT 0x0cf8
67 #define CONF1_DATA_PORT 0x0cfc
69 #define CONF1_ENABLE 0x80000000ul
132 #define PCI_EMUL_IOBASE 0x2000
133 #define PCI_EMUL_IOLIMIT 0x10000
134 #define PCI_EMUL_IOMASK 0xffff
136 * OVMF always uses 0xc0000000 as base address for 32 bit PCI MMIO. Don't
139 #define PCI_EMUL_MEMBASE32 0xc0000000
141 #define PCI_EMUL_IOBASE 0xdf000000UL
142 #define PCI_EMUL_IOLIMIT 0xe0000000UL
143 #define PCI_EMUL_MEMBASE32 0xa0000000UL
148 #define PCI_EMUL_ROMSIZE 0x10000000
150 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
193 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)); in is_pcir_bar()
212 * slot is 0..31
213 * func is 0..7
219 * 3:0,dummy
240 return (0); in pci_parse_legacy_config()
246 *value = '\0'; in pci_parse_legacy_config()
253 return (0); in pci_parse_legacy_config()
284 *cp = '\0'; in pci_parse_slot()
287 *cp = '\0'; in pci_parse_slot()
297 bnum = 0; in pci_parse_slot()
300 fnum = 0; in pci_parse_slot()
308 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || in pci_parse_slot()
309 fnum < 0 || fnum >= MAXFUNCS) { in pci_parse_slot()
391 } else if (host_sel != NULL && strcmp(config, "host") == 0) { in pci_config_read_reg()
407 return (0); in pci_valid_pba_offset()
410 return (0); in pci_valid_pba_offset()
438 if ((msix_entry_offset % size) != 0) in pci_emul_msix_twrite()
449 return (0); in pci_emul_msix_twrite()
458 uint64_t retval = ~0; in pci_emul_msix_tread()
471 if ((msix_entry_offset % size) != 0) { in pci_emul_msix_tread()
489 /* return 0 for PBA access */ in pci_emul_msix_tread()
490 retval = 0; in pci_emul_msix_tread()
526 assert(port >= 0); in pci_emul_io_handler()
528 for (i = 0; i <= PCI_BARMAX; i++) { in pci_emul_io_handler()
540 return (0); in pci_emul_io_handler()
567 return (0); in pci_emul_iomem_handler()
591 4, *val & 0xffffffff); in pci_emul_mem_handler()
610 return (0); in pci_emul_mem_handler()
620 assert((size & (size - 1)) == 0); /* must be a power of 2 */ in pci_emul_alloc_resource()
627 return (0); in pci_emul_alloc_resource()
700 error = 0; in modify_bar_registration()
706 assert(error == 0); in modify_bar_registration()
716 modify_bar_registration(pi, idx, 0); in unregister_bar()
781 pi->pi_bar[idx].addr &= ~0xffffffffUL; in update_bar_address()
785 pi->pi_bar[idx].addr &= 0xffffffff; in update_bar_address()
789 assert(0); in update_bar_address()
800 assert((type == PCIBAR_ROM) || (idx >= 0 && idx <= PCI_BARMAX)); in pci_emul_alloc_bar()
803 if ((size & (size - 1)) != 0) in pci_emul_alloc_bar()
827 memset(new_bar, 0, sizeof(*new_bar)); in pci_emul_alloc_bar()
864 return (0); in pci_emul_alloc_bar()
871 uint16_t enbit = 0; in pci_emul_alloc_bar()
881 enbit = 0; in pci_emul_alloc_bar()
888 return (0); in pci_emul_alloc_bar()
901 addr = mask = lobits = 0; in pci_emul_assign_bar()
939 limit = 0; in pci_emul_assign_bar()
941 lobits = 0; in pci_emul_assign_bar()
945 assert(0); in pci_emul_assign_bar()
950 if (error != 0) in pci_emul_assign_bar()
953 addr = 0; in pci_emul_assign_bar()
963 if (pdi->pi_bar[idx].lobits != 0) { in pci_emul_assign_bar()
994 return (0); in pci_emul_assign_bar()
1002 if (pci_emul_rombase == 0) { in pci_emul_alloc_rom()
1010 pci_emul_romoffset = 0; in pci_emul_alloc_rom()
1042 return (0); in pci_emul_alloc_rom()
1051 if (bootindex < 0) { in pci_emul_add_boot_device()
1081 return (0); in pci_emul_add_boot_device()
1084 #define CAP_START_OFFSET 0x40
1091 assert(caplen > 0); in pci_emul_add_capability()
1096 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) in pci_emul_add_capability()
1106 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { in pci_emul_add_capability()
1113 for (i = 0; i < caplen; i++) in pci_emul_add_capability()
1117 pci_set_cfgdata8(pi, capoff + 1, 0); in pci_emul_add_capability()
1121 return (0); in pci_emul_add_capability()
1153 pdi->pi_lintr.pin = 0; in pci_emul_init()
1162 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); in pci_emul_init()
1168 if (err == 0) in pci_emul_init()
1182 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); in pci_populate_msicap()
1196 pci_populate_msicap(&msicap, msgnum, 0); in pci_emul_add_msicap()
1206 assert(msix_tab_size % 4096 == 0); in pci_populate_msixcap()
1220 * - MSI-X table start at offset 0 in pci_populate_msixcap()
1232 assert(table_entries > 0); in pci_msix_table_init()
1239 for (i = 0; i < table_entries; i++) in pci_msix_table_init()
1250 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); in pci_emul_add_msixcap()
1259 pi->pi_msix.table_offset = 0; in pci_emul_add_msixcap()
1328 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; in msicap_cfgwrite()
1334 pi->pi_msi.maxmsgnum = 0; in msicap_cfgwrite()
1348 #define PCIECAP_VERSION 0x2
1363 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) in pci_emul_add_pciecap()
1369 pciecap.link_capabilities = 0x411; /* gen1, x1 */ in pci_emul_add_pciecap()
1370 pciecap.link_status = 0x11; /* gen1, x1 */ in pci_emul_add_pciecap()
1389 if ((offset & (bytes - 1)) != 0) in pci_emul_capwrite()
1392 if (capoff == 0) { in pci_emul_capwrite()
1397 if (nextoff == 0) in pci_emul_capwrite()
1444 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { in pci_emul_iscap()
1448 return (0); in pci_emul_iscap()
1457 * Ignore writes; return 0xff's for reads. The mem read code in pci_emul_fallback_handler()
1461 *val = 0xffffffffffffffff; in pci_emul_fallback_handler()
1464 return (0); in pci_emul_fallback_handler()
1473 coff = addr & 0xfff; in pci_emul_ecfg_handler()
1474 func = (addr >> 12) & 0x7; in pci_emul_ecfg_handler()
1475 slot = (addr >> 15) & 0x1f; in pci_emul_ecfg_handler()
1476 bus = (addr >> 20) & 0xff; in pci_emul_ecfg_handler()
1479 *val = ~0UL; in pci_emul_ecfg_handler()
1481 return (0); in pci_emul_ecfg_handler()
1500 return (0); in init_bootorder()
1544 for (bus = 0; bus < MAXBUSES; bus++) { in init_pci()
1561 for (slot = 0; slot < MAXSLOTS; slot++) { in init_pci()
1563 for (func = 0; func < MAXFUNCS; func++) { in init_pci()
1635 for (bus = 0; bus < MAXBUSES; bus++) { in init_pci()
1639 for (slot = 0; slot < MAXSLOTS; slot++) { in init_pci()
1641 for (func = 0; func < MAXFUNCS; func++) { in init_pci()
1653 if ((error = init_bootorder()) != 0) { in init_pci()
1660 * [0, lowmem) guest system memory in init_pci()
1661 * [lowmem, 0xC0000000) memory hole (may be absent) in init_pci()
1662 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation) in init_pci()
1663 * [0xE0000000, 0xF0000000) PCI extended config window in init_pci()
1664 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware in init_pci()
1669 * [0x0DF00000, 0x10000000) PCI I/O memory in init_pci()
1670 * [0xA0000000, 0xE0000000) PCI 32-bit BAR allocation in init_pci()
1671 * [0xE0000000, 0xF0000000) PCI extended config window in init_pci()
1675 * "lowmem" is guest memory below 0xC0000000. amd64 guests provisioned in init_pci()
1682 * memory or PCI devices return 0xff's. in init_pci()
1692 assert(error == 0); in init_pci()
1702 assert(error == 0); in init_pci()
1704 return (0); in init_pci()
1715 dsdt_line(" 0x%X,", slot << 16 | 0xffff); in pci_apic_prt_entry()
1716 dsdt_line(" 0x%02X,", pin - 1); in pci_apic_prt_entry()
1718 dsdt_line(" 0x%X", irq->ioapic_irq); in pci_apic_prt_entry()
1733 dsdt_line(" 0x%X,", slot << 16 | 0xffff); in pci_pirq_prt_entry()
1734 dsdt_line(" 0x%02X,", pin - 1); in pci_pirq_prt_entry()
1736 dsdt_line(" 0x00"); in pci_pirq_prt_entry()
1759 * Bus 0 is special because it decodes the I/O ports used in pci_bus_write_dsdt()
1763 if (bus != 0) in pci_bus_write_dsdt()
1771 dsdt_line(" Method (_BBN, 0, NotSerialized)"); in pci_bus_write_dsdt()
1773 dsdt_line(" Return (0x%08X)", bus); in pci_bus_write_dsdt()
1779 dsdt_line(" 0x0000, // Granularity"); in pci_bus_write_dsdt()
1780 dsdt_line(" 0x%04X, // Range Minimum", bus); in pci_bus_write_dsdt()
1781 dsdt_line(" 0x%04X, // Range Maximum", bus); in pci_bus_write_dsdt()
1782 dsdt_line(" 0x0000, // Translation Offset"); in pci_bus_write_dsdt()
1783 dsdt_line(" 0x0001, // Length"); in pci_bus_write_dsdt()
1787 if (bus == 0) { in pci_bus_write_dsdt()
1789 dsdt_fixed_ioport(0xCF8, 8); in pci_bus_write_dsdt()
1794 dsdt_line(" 0x0000, // Granularity"); in pci_bus_write_dsdt()
1795 dsdt_line(" 0x0000, // Range Minimum"); in pci_bus_write_dsdt()
1796 dsdt_line(" 0x0CF7, // Range Maximum"); in pci_bus_write_dsdt()
1797 dsdt_line(" 0x0000, // Translation Offset"); in pci_bus_write_dsdt()
1798 dsdt_line(" 0x0CF8, // Length"); in pci_bus_write_dsdt()
1803 dsdt_line(" 0x0000, // Granularity"); in pci_bus_write_dsdt()
1804 dsdt_line(" 0x0D00, // Range Minimum"); in pci_bus_write_dsdt()
1805 dsdt_line(" 0x%04X, // Range Maximum", in pci_bus_write_dsdt()
1807 dsdt_line(" 0x0000, // Translation Offset"); in pci_bus_write_dsdt()
1808 dsdt_line(" 0x%04X, // Length", in pci_bus_write_dsdt()
1809 PCI_EMUL_IOBASE - 0x0D00); in pci_bus_write_dsdt()
1823 dsdt_line(" 0x0000, // Granularity"); in pci_bus_write_dsdt()
1824 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); in pci_bus_write_dsdt()
1825 dsdt_line(" 0x%04X, // Range Maximum", in pci_bus_write_dsdt()
1827 dsdt_line(" 0x0000, // Translation Offset"); in pci_bus_write_dsdt()
1828 dsdt_line(" 0x%04X, // Length", in pci_bus_write_dsdt()
1835 dsdt_line(" 0x00000000, // Granularity"); in pci_bus_write_dsdt()
1836 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); in pci_bus_write_dsdt()
1837 dsdt_line(" 0x%08X, // Range Maximum\n", in pci_bus_write_dsdt()
1839 dsdt_line(" 0x00000000, // Translation Offset"); in pci_bus_write_dsdt()
1840 dsdt_line(" 0x%08X, // Length\n", in pci_bus_write_dsdt()
1847 dsdt_line(" 0x0000000000000000, // Granularity"); in pci_bus_write_dsdt()
1848 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); in pci_bus_write_dsdt()
1849 dsdt_line(" 0x%016lX, // Range Maximum\n", in pci_bus_write_dsdt()
1851 dsdt_line(" 0x0000000000000000, // Translation Offset"); in pci_bus_write_dsdt()
1852 dsdt_line(" 0x%016lX, // Length\n", in pci_bus_write_dsdt()
1858 if (pci_count_lintr(bus) != 0) { in pci_bus_write_dsdt()
1868 dsdt_line("Method (_PRT, 0, NotSerialized)"); in pci_bus_write_dsdt()
1884 for (slot = 0; slot < MAXSLOTS; slot++) { in pci_bus_write_dsdt()
1886 for (func = 0; func < MAXFUNCS; func++) { in pci_bus_write_dsdt()
1905 dsdt_line("Name (PICM, 0x00)"); in pci_write_dsdt()
1913 for (bus = 0; bus < MAXBUSES; bus++) in pci_write_dsdt()
1922 assert(bus >= 0 && bus < MAXBUSES); in pci_bus_configured()
1938 return (0); in pci_msi_maxmsgnum()
1963 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { in pci_generate_msix()
2006 bestpin = 0; in pci_lintr_request()
2007 bestcount = si->si_intpins[0].ii_count; in pci_lintr_request()
2027 if (pi->pi_lintr.pin == 0) in pci_lintr_route()
2043 assert(pi->pi_lintr.pin > 0); in pci_lintr_assert()
2060 assert(pi->pi_lintr.pin > 0); in pci_lintr_deassert()
2092 count = 0; in pci_count_lintr()
2094 for (slot = 0; slot < MAXSLOTS; slot++) { in pci_count_lintr()
2096 for (pin = 0; pin < 4; pin++) { in pci_count_lintr()
2097 if (slotinfo->si_intpins[pin].ii_count != 0) in pci_count_lintr()
2116 for (slot = 0; slot < MAXSLOTS; slot++) { in pci_walk_lintr()
2118 for (pin = 0; pin < 4; pin++) { in pci_walk_lintr()
2120 if (ii->ii_count != 0) in pci_walk_lintr()
2128 * Return 0 otherwise.
2137 numfuncs = 0; in pci_emul_is_mfdev()
2140 for (f = 0; f < MAXFUNCS; f++) { in pci_emul_is_mfdev()
2195 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) { in pci_emul_cmd_changed()
2225 assert(0); in pci_emul_cmd_changed()
2251 rshift = (coff & 0x3) * 8; in pci_emul_cmdsts_write()
2252 readonly = 0xFFFFF880 >> rshift; in pci_emul_cmdsts_write()
2284 (coff & (bytes - 1)) != 0) { in pci_cfgrw()
2286 *valp = 0xffffffff; in pci_cfgrw()
2296 *valp = 0xffffffff; in pci_cfgrw()
2300 * with all 0s in the extended capability header at in pci_cfgrw()
2304 *valp = 0x00000000; in pci_cfgrw()
2329 (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0) in pci_cfgrw()
2340 if (bytes != 4 || (coff & 0x3) != 0) in pci_cfgrw()
2344 idx = (coff - PCIR_BAR(0)) / 4; in pci_cfgrw()
2355 pi->pi_bar[idx].addr = bar = 0; in pci_cfgrw()
2411 assert(0); in pci_cfgrw()
2416 pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0); in pci_cfgrw()
2436 *eax = (bytes == 2) ? 0xffff : 0xff; in pci_emul_cfgaddr()
2437 return (0); in pci_emul_cfgaddr()
2448 cfgoff = (x & PCI_REGMAX) & ~0x03; in pci_emul_cfgaddr()
2454 return (0); in pci_emul_cfgaddr()
2472 *eax = 0xffffffff; in pci_emul_cfgdata()
2474 return (0); in pci_emul_cfgdata()
2477 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata);
2485 * Saves/restores PCI device emulated state. Returns 0 on success.
2513 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { in pci_snapshot_pci_dev()
2520 for (i = 0; i < pi->pi_msix.table_count; i++) { in pci_snapshot_pci_dev()
2549 if (ret == 0) in pci_snapshot()
2562 return (0); in pci_pause()
2575 return (0); in pci_resume()
2607 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); in pci_emul_dinit()
2608 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); in pci_emul_dinit()
2609 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); in pci_emul_dinit()
2612 assert(error == 0); in pci_emul_dinit()
2614 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); in pci_emul_dinit()
2615 assert(error == 0); in pci_emul_dinit()
2618 assert(error == 0); in pci_emul_dinit()
2621 assert(error == 0); in pci_emul_dinit()
2623 return (0); in pci_emul_dinit()
2633 if (baridx == 0) { in pci_emul_diow()
2641 sc->ioregs[offset] = value & 0xff; in pci_emul_diow()
2643 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; in pci_emul_diow()
2656 if (value == 0xabcdef) { in pci_emul_diow()
2657 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) in pci_emul_diow()
2688 if (baridx > 2 || baridx < 0) { in pci_emul_diow()
2700 if (baridx == 0) { in pci_emul_dior()
2704 return (0); in pci_emul_dior()
2707 value = 0; in pci_emul_dior()
2723 return (0); in pci_emul_dior()
2742 if (baridx > 2 || baridx < 0) { in pci_emul_dior()
2744 return (0); in pci_emul_dior()
2754 unsigned bus = 0, slot = 0, func = 0; in pci_next()
2759 bus = cursor ? cursor->pi_bus : 0; in pci_next()
2760 slot = cursor ? cursor->pi_slot : 0; in pci_next()
2761 func = cursor ? (cursor->pi_func + 1) : 0; in pci_next()
2768 slot = 0; in pci_next()
2773 func = 0; in pci_next()
2790 return (0); in pci_emul_snapshot()