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/freebsd/crypto/openssl/Configurations/
H A D50-win-onecore.conf21 if ($SDKver_split[0] < 10
22 || ($SDKver_split[0] == 10
23 && $SDKver_split[1] == 0
102 "_WIN32_WINNT=0x0A00"),
112 "_WIN32_WINNT=0x0A00"),
122 "_WIN32_WINNT=0x0A00"),
132 "_WIN32_WINNT=0x0A00"),
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dgate.txt31 - #clock-cells : from common clock binding; shall be set to 0
45 #clock-cells = <0>;
48 reg = <0x0a00>;
53 #clock-cells = <0>;
56 reg = <0x0a00>;
61 #clock-cells = <0>;
64 reg = <0x0e00>;
65 ti,bit-shift = <0>;
69 #clock-cells = <0>;
72 reg = <0x059c>;
[all …]
/freebsd/sys/arm64/include/
H A Dcmn600_reg.h34 #define CMN600_COMMON_PMU_EVENT_SEL 0x2000 /* rw */
36 #define CMN600_COMMON_PMU_EVENT_SEL_OCC_MASK (0x7UL << 32)
68 #define POR_CFGM_NODE_INFO 0x0000 /* ro */
69 #define POR_CFGM_NODE_INFO_LOGICAL_ID_MASK 0xffff00000000UL
71 #define POR_CFGM_NODE_INFO_NODE_ID_MASK 0xffff0000
73 #define POR_CFGM_NODE_INFO_NODE_TYPE_MASK 0xffff
74 #define POR_CFGM_NODE_INFO_NODE_TYPE_SHIFT 0
76 #define NODE_ID_SUB_MASK 0x3
77 #define NODE_ID_SUB_SHIFT 0
78 #define NODE_ID_PORT_MASK 0x4
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/freebsd/sys/powerpc/powermac/
H A Dviareg.h32 #define vBufB 0x0000 /* register B */
33 #define vDirB 0x0400 /* data direction register */
34 #define vDirA 0x0600 /* data direction register */
35 #define vT1C 0x0800 /* Timer 1 counter Lo */
36 #define vT1CH 0x0a00 /* Timer 1 counter Hi */
37 #define vSR 0x1400 /* shift register */
38 #define vACR 0x1600 /* aux control register */
39 #define vPCR 0x1800 /* peripheral control register */
40 #define vIFR 0x1a00 /* interrupt flag register */
41 #define vIER 0x1c00 /* interrupt enable register */
[all …]
/freebsd/sys/libkern/
H A Dcrc16.c32 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */
34 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
35 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
36 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
37 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
38 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
39 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
40 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
41 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
42 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/freebsd/crypto/openssl/crypto/conf/
H A Dconf_def.h43 0x0008, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
44 0x0000, 0x0010, 0x0010, 0x0000, 0x0000, 0x0010, 0x0000, 0x0000,
45 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
46 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
47 0x0010, 0x0200, 0x0040, 0x0080, 0x1000, 0x0200, 0x0200, 0x0040,
48 0x0000, 0x0000, 0x0200, 0x0200, 0x0200, 0x0200, 0x0200, 0x0200,
49 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001, 0x0001,
50 0x0001, 0x0001, 0x0000, 0x0200, 0x0000, 0x0000, 0x0000, 0x0200,
51 0x0200, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
52 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002, 0x0002,
[all …]
/freebsd/sys/dev/amdsbwd/
H A Damd_chipset.h36 * a PCI Device ID of 0x43851002 and a revision less than 0x40
39 * Device ID of 0x43851002 and a revision greater than or equal to 0x40
40 * o FCHs where the controller has an ID of 0x780b1022 and a revision less
41 * than 0x41 (various variants of "Hudson" and "Bolton" as well as FCHs
43 * o FCHs where the controller has an ID of 0x790b1022 and a revision less
44 * than 0x49
46 * o FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022
47 * and a revision greater than or equal to 0x41 (integrated into "Mullins"
49 * o FCHs where the controller has an ID of 0x790b1022 and a revision greater
50 * than or equal to 0x49 (integrated into "Carrizo" processors, code named
[all …]
/freebsd/sys/dev/ice/
H A Dice_adminq_cmd.h44 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
59 /* Get version (direct 0x0001) */
73 /* Send driver version (indirect 0x0002) */
84 /* Queue Shutdown (direct 0x0003) */
87 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
91 /* Get Expanded Error Code (0x0005, direct) */
94 #define ICE_AQC_EXPANDED_ERROR_NOT_PROVIDED 0xFFFFFFFF
99 /* Request resource ownership (direct 0x0008)
100 * Release resource ownership (direct 0x0009)
125 #define ICE_AQ_RES_GLBL_SUCCESS 0
[all...]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8723d.h14 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
18 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
20 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
22 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
24 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
26 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
28 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0))
30 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0))
[all...]
H A Ddebug.c84 return 0; in rtw_debugfs_close()
122 seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); in rtw_debugfs_get_read_reg()
126 seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); in rtw_debugfs_get_read_reg()
130 seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); in rtw_debugfs_get_read_reg()
133 return 0; in rtw_debugfs_get_read_reg()
151 seq_printf(m, "rf_read path:%d addr:0x%08x mask:0x%08x val=0x%08x\n", in rtw_debugfs_get_rf_read()
154 return 0; in rtw_debugfs_get_rf_read()
166 return 0; in rtw_debugfs_get_fix_rate()
170 return 0; in rtw_debugfs_get_fix_rate()
179 memset(tmp, 0, size); in rtw_debugfs_copy_from_user()
[all …]
/freebsd/sys/arm/ti/cpsw/
H A Dif_cpswreg.h32 #define CPSW_SS_OFFSET 0x0000
33 #define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00)
34 #define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
35 #define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
36 #define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
37 #define CPSW_SS_FLOW_CONTROL (CPSW_SS_OFFSET + 0x24)
39 #define CPSW_PORT_OFFSET 0x0100
40 #define CPSW_PORT_P_MAX_BLKS(p) (CPSW_PORT_OFFSET + 0x08 + ((p) * 0x100))
41 #define CPSW_PORT_P_BLK_CNT(p) (CPSW_PORT_OFFSET + 0x0C + ((p) * 0x100))
42 #define CPSW_PORT_P_VLAN(p) (CPSW_PORT_OFFSET + 0x14 + ((p) * 0x100))
[all …]
/freebsd/sys/ufs/ufs/
H A Dquota.h58 #define USRQUOTA 0 /* element used for user quotas */
77 #define SUBCMDMASK 0x00ff
81 #define Q_QUOTAON 0x0100 /* enable quotas */
82 #define Q_QUOTAOFF 0x0200 /* disable quotas */
83 #define Q_GETQUOTA32 0x0300 /* get limits and usage (32-bit version) */
84 #define Q_SETQUOTA32 0x0400 /* set limits and usage (32-bit version) */
85 #define Q_SETUSE32 0x0500 /* set usage (32-bit version) */
86 #define Q_SYNC 0x0600 /* sync disk copy of a filesystems quotas */
87 #define Q_GETQUOTA 0x0700 /* get limits and usage (64-bit version) */
88 #define Q_SETQUOTA 0x0800 /* set limits and usage (64-bit version) */
[all …]
/freebsd/sys/dev/ixl/
H A Di40e_adminq_cmd.h44 #define I40E_FW_API_VERSION_MAJOR 0x0001
45 #define I40E_FW_API_VERSION_MINOR_X722 0x000C
46 #define I40E_FW_API_VERSION_MINOR_X710 0x000F
53 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
55 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
57 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
59 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
86 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
91 #define I40E_AQ_FLAG_DD_SHIFT 0
103 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
[all …]
/freebsd/sys/dev/iavf/
H A Diavf_adminq_cmd.h43 #define IAVF_FW_API_VERSION_MAJOR 0x0001
44 #define IAVF_FW_API_VERSION_MINOR_X722 0x0006
45 #define IAVF_FW_API_VERSION_MINOR_X710 0x0007
52 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
54 #define IAVF_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
81 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
86 #define IAVF_AQ_FLAG_DD_SHIFT 0
98 #define IAVF_AQ_FLAG_DD (1 << IAVF_AQ_FLAG_DD_SHIFT) /* 0x1 */
99 #define IAVF_AQ_FLAG_CMP (1 << IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2 */
100 #define IAVF_AQ_FLAG_ERR (1 << IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4 */
[all …]
/freebsd/sys/dev/bnxt/bnxt_re/
H A Dib_verbs.h41 #define BNXT_RE_ROCE_V2_UDP_SPORT 0x8CD1
42 #define BNXT_RE_QP_RANDOM_QKEY 0x81818181
97 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256MB 0x1cUL
488 return 0; in bnxt_re_init_pow2_flag()
508 return 0; in bnxt_re_init_rsvd_wqe_flag()
516 return _is_chip_gen_p5_p7(cctx) ? 0 : BNXT_QPLIB_RESERVED_QP_WRS; in bnxt_re_get_diff()
518 return 0; in bnxt_re_get_diff()
559 return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | in compare_ether_header()
572 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */ in crc16()
574 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, in crc16()
[all …]
/freebsd/sys/dev/mii/
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
/freebsd/sys/net/
H A Dethernet.h37 ((hasfcs) ? ETHER_CRC_LEN : 0) + \
38 (((etype) == ETHERTYPE_VLAN) ? ETHER_VLAN_ENCAP_LEN : 0))
48 #define ETHER_CRC_POLY_LE 0xedb88320
49 #define ETHER_CRC_POLY_BE 0x04c11db6
73 #define ETHER_IS_MULTICAST(addr) (*(addr) & 0x01) /* is address mcast/bcast? */
75 (((addr)[0] == 0x33) && ((addr)[1] == 0x33))
77 (((addr)[0] & (addr)[1] & (addr)[2] & \
78 (addr)[3] & (addr)[4] & (addr)[5]) == 0xf
[all...]
/freebsd/sys/dev/pci/
H A Dpcireg.h53 #define PCIE_ARI_SLOTMAX 0
59 #define PCI_RID_FUNC_SHIFT 0
74 #define PCIE_ARI_RID2SLOT(rid) (0)
83 #define PCIR_DEVVENDOR 0x00
84 #define PCIR_VENDOR 0x00
85 #define PCIR_DEVICE 0x02
86 #define PCIR_COMMAND 0x04
87 #define PCIM_CMD_PORTEN 0x0001
88 #define PCIM_CMD_MEMEN 0x0002
89 #define PCIM_CMD_BUSMASTEREN 0x0004
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dapple6 0 search/1/t FiLeStArTfIlEsTaRt binscii (apple ][) text
7 0 string \x0aGL Binary II (apple ][) data
8 0 string \x76\xff Squeezed (apple ][) data
9 0 string NuFile NuFile archive (apple ][) data
10 0 string N\xf5F\xe9l\xe5 NuFile archive (apple ][) data
11 0 belong 0x00051600 AppleSingle encoded Macintosh file
12 0 belong 0x00051607 AppleDouble encoded Macintosh file
18 0 string A2R
20 >>0 use applesauce
22 >>0 use applesauce
[all …]
/freebsd/sys/dev/sk/
H A Dif_skreg.h54 #define SK_GENESIS 0x0A
55 #define SK_YUKON 0xB0
56 #define SK_YUKON_LITE 0xB1
57 #define SK_YUKON_LP 0xB2
58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
61 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
62 #define SK_YUKON_LITE_REV_A1 0x3
63 #define SK_YUKON_LITE_REV_A3 0x7
68 #define VENDORID_SK 0x1148
73 #define VENDORID_MARVELL 0x11AB
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h32 #define AR_CR 0x0008 /* control register */
33 #define AR_RXDP 0x000C /* receive queue descriptor pointer */
34 #define AR_CFG 0x0014 /* configuration and status register */
35 #define AR_IER 0x0024 /* Interrupt enable register */
36 #define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
37 #define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
40 #define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
41 #define AR_MIBC 0x0040 /* MIB control register */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h27 #define AR_CR 0x0008 /* MAC control register */
28 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29 #define AR_CFG 0x0014 /* MAC configuration and status register */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
31 /* 0x28 is RTSD0 on the 5211 */
32 /* 0x2c is RTSD1 on the 5211 */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
35 /* 0x38 is the jumbo descriptor address on the 5211 */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
[all …]
/freebsd/contrib/libpcap/msdos/
H A Dpktdrvr.c34 #define DIM(x) (sizeof((x)) / sizeof(x[0]))
40 } while (0)
105 #define FIRST_RX_BUF offsetof (PktRealStub,_pktRxBuf [0])
118 #define FIRST_RX_BUF (WORD) &pktRxBuf [0]
158 static int para_skip = 0;
174 LOCAL int para_skip = 0;
204 PUBLIC ETHER myAddress = { 0, 0, 0, 0, 0, 0 };
241 if (errNum < 0 || errNum >= DIM(errStr)) in PktGetErrorStr()
313 okay = ((reg.flags & 1) == 0); /* OK if carry clear */ in PktInterrupt()
317 okay = ((reg.x.flags & 1) == 0); in PktInterrupt()
[all …]

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