Lines Matching +full:0 +full:x0a00
36 * a PCI Device ID of 0x43851002 and a revision less than 0x40
39 * Device ID of 0x43851002 and a revision greater than or equal to 0x40
40 * o FCHs where the controller has an ID of 0x780b1022 and a revision less
41 * than 0x41 (various variants of "Hudson" and "Bolton" as well as FCHs
43 * o FCHs where the controller has an ID of 0x790b1022 and a revision less
44 * than 0x49
46 * o FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022
47 * and a revision greater than or equal to 0x41 (integrated into "Mullins"
49 * o FCHs where the controller has an ID of 0x790b1022 and a revision greater
50 * than or equal to 0x49 (integrated into "Carrizo" processors, code named
61 #define AMDSB_PMIO_INDEX 0xcd6
69 #define AMDSB_PM_RESET_STATUS0 0x44
70 #define AMDSB_PM_RESET_STATUS1 0x45
71 #define AMDSB_WD_RST_STS 0x02
72 #define AMDSB_PM_WDT_CTRL 0x69
73 #define AMDSB_WDT_DISABLE 0x01
74 #define AMDSB_WDT_RES_MASK (0x02 | 0x04)
75 #define AMDSB_WDT_RES_32US 0x00
76 #define AMDSB_WDT_RES_10MS 0x02
77 #define AMDSB_WDT_RES_100MS 0x04
78 #define AMDSB_WDT_RES_1S 0x06
79 #define AMDSB_PM_WDT_BASE_LSB 0x6c
80 #define AMDSB_PM_WDT_BASE_MSB 0x6f
86 #define AMDSB8_PM_SMBUS_EN 0x2c
87 #define AMDSB8_SMBUS_EN 0x01
88 #define AMDSB8_SMBUS_ADDR_MASK 0xffe0u
89 #define AMDSB8_PM_WDT_EN 0x48
90 #define AMDSB8_WDT_DEC_EN 0x01
91 #define AMDSB8_WDT_DISABLE 0x02
92 #define AMDSB8_PM_WDT_CTRL 0x4c
93 #define AMDSB8_WDT_32KHZ 0x00
94 #define AMDSB8_WDT_1HZ 0x03
95 #define AMDSB8_WDT_RES_MASK 0x03
96 #define AMDSB8_PM_RESET_STATUS 0xc0 /* 32 bit wide */
97 #define AMDSB8_WD_RST_STS 0x2000000
98 #define AMDSB8_PM_RESET_CTRL 0xc4
99 #define AMDSB8_RST_STS_DIS 0x04
105 #define AMDFCH41_PM_DECODE_EN0 0x00
106 #define AMDFCH41_SMBUS_EN 0x10
107 #define AMDFCH41_WDT_EN 0x80
108 #define AMDFCH41_PM_DECODE_EN1 0x01
109 #define AMDFCH41_PM_DECODE_EN3 0x03
110 #define AMDFCH41_WDT_RES_MASK 0x03
111 #define AMDFCH41_WDT_RES_32US 0x00
112 #define AMDFCH41_WDT_RES_10MS 0x01
113 #define AMDFCH41_WDT_RES_100MS 0x02
114 #define AMDFCH41_WDT_RES_1S 0x03
115 #define AMDFCH41_WDT_EN_MASK 0x0c
116 #define AMDFCH41_WDT_ENABLE 0x00
117 #define AMDFCH41_PM_ISA_CTRL 0x04
118 #define AMDFCH41_MMIO_EN 0x02
124 #define AMDFCH41_WDT_FIXED_ADDR 0xfeb00000u
125 #define AMDFCH41_MMIO_ADDR 0xfed80000u
126 #define AMDFCH41_MMIO_PM_OFF 0x0300
127 #define AMDFCH41_MMIO_SMBUS_OFF 0x0a00
128 #define AMDFCH41_MMIO_WDT_OFF 0x0b00
137 * BKDG for Family 16h Models 00h-0Fh 3.26.7.1,
141 #define AMDSB_SMBUS_DEVID 0x43851002
142 #define AMDSB8_SMBUS_REVID 0x40
143 #define AMDFCH_SMBUS_DEVID 0x780b1022
144 #define AMDFCH41_SMBUS_REVID 0x41
145 #define AMDCZ_SMBUS_DEVID 0x790b1022
146 #define AMDCZ49_SMBUS_REVID 0x49
147 #define AMDCZ51_SMBUS_REVID 0x51
149 #define HYGONCZ_SMBUS_DEVID 0x790b1d94