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/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
H A Dpinctrl-mt8195.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000,
14 * iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000,
15 * iocfg[6]:0x11f40000.
21 32, 0)
28 PIN_FIELD(0, 144, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 144, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 144, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 144, 0x100, 0x10, 0, 1),
44 PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1),
45 PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1),
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-exynos-arm.c27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
36 #define S5P_OTHERS 0xE000
43 #define S5P_PIN_PULL_DISABLE 0
86 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
106 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
107 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
108 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
109 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
110 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
[all …]
H A Dpinctrl-exynos-arm64.c24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
67 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
76 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
77 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
78 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu-sun4i-a10.c32 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
34 .m = _SUNXI_CCU_DIV(0, 2),
37 .reg = 0x000,
41 0),
57 #define SUN4I_PLL_AUDIO_REG 0x008
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
66 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
67 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
68 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
[all …]
H A Dccu-sun50i-a64.c31 .m = _SUNXI_CCU_DIV(0, 2),
34 .reg = 0x000,
54 #define SUN50I_A64_PLL_AUDIO_REG 0x008
57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
62 "osc24M", 0x008,
64 0, 5, /* M */
66 0x284, BIT(31),
72 "osc24M", 0x010,
76 0, 4, /* M */
[all …]
H A Dccu-sun8i-h3.c29 "osc24M", 0x000,
32 0, 2, /* M */
50 #define SUN8I_H3_PLL_AUDIO_REG 0x008
53 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
54 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
58 "osc24M", 0x008,
60 0, 5, /* M */
62 0x284, BIT(31),
68 "osc24M", 0x0010,
72 0, 4, /* M */
[all …]
H A Dccu-sun6i-a31.c33 "osc24M", 0x000,
36 0, 2, /* M */
39 0);
53 #define SUN6I_A31_PLL_AUDIO_REG 0x008
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
61 "osc24M", 0x008,
63 0, 5, /* M */
65 0x284, BIT(31),
71 "osc24M", 0x010,
[all …]
H A Dccu-sun8i-r40.c33 .m = _SUNXI_CCU_DIV(0, 2),
36 .reg = 0x000,
56 #define SUN8I_R40_PLL_AUDIO_REG 0x008
59 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
60 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
64 "osc24M", 0x008,
66 0, 5, /* M */
68 0x284, BIT(31),
74 "osc24M", 0x0010,
78 0, 4, /* M */
[all …]
H A Dccu-sun8i-a83t.c24 #define CCU_SUN8I_A83T_LOCK_REG 0x20c
33 #define SUN8I_A83T_PLL_C0CPUX_REG 0x000
34 #define SUN8I_A83T_PLL_C1CPUX_REG 0x004
38 .lock = BIT(0),
39 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
53 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
68 * which is d1 = 0, d2 = 1.
70 #define SUN8I_A83T_PLL_AUDIO_REG 0x008
74 { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
75 { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
[all …]
H A Dccu-sun5i.c28 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
30 .m = _SUNXI_CCU_DIV(0, 2),
33 .reg = 0x000,
37 0),
53 #define SUN5I_PLL_AUDIO_REG 0x008
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
62 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
68 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
69 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
[all …]
H A Dccu-sun8i-a33.c32 .m = _SUNXI_CCU_DIV(0, 2),
36 .reg = 0x000,
39 0),
55 #define SUN8I_A33_PLL_AUDIO_REG 0x008
58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
63 "osc24M", 0x008,
65 0, 5, /* M */
67 0x284, BIT(31),
73 "osc24M", 0x010,
[all …]
H A Dccu-sun8i-a23.c34 .m = _SUNXI_CCU_DIV(0, 2),
38 .reg = 0x000,
41 0),
57 #define SUN8I_A23_PLL_AUDIO_REG 0x008
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
65 "osc24M", 0x008,
67 0, 5, /* M */
69 0x284, BIT(31),
75 "osc24M", 0x010,
[all …]
H A Dccu-sun8i-v3s.c31 "osc24M", 0x000,
34 0, 2, /* M */
38 0);
52 #define SUN8I_V3S_PLL_AUDIO_REG 0x008
55 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
56 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
60 "osc24M", 0x008,
62 0, 5, /* M */
64 0x284, BIT(31),
70 "osc24M", 0x0010,
[all …]
H A Dccu-suniv-f1c100s.c33 .m = _SUNXI_CCU_DIV(0, 2),
38 .reg = 0x000,
53 #define SUNIV_PLL_AUDIO_REG 0x008
56 "osc24M", 0x008,
58 0, 5, /* M */
64 "osc24M", 0x010,
66 0, 4, /* M */
69 270000000, /* frac rate 0 */
76 "osc24M", 0x018,
78 0, 4, /* M */
[all …]
/linux/sound/pci/oxygen/
H A Dwm8785.h5 #define WM8785_R0 0
11 #define WM8785_MCR_MASK 0x007
12 #define WM8785_MCR_SLAVE 0x000
13 #define WM8785_MCR_MASTER_128 0x001
14 #define WM8785_MCR_MASTER_192 0x002
15 #define WM8785_MCR_MASTER_256 0x003
16 #define WM8785_MCR_MASTER_384 0x004
17 #define WM8785_MCR_MASTER_512 0x005
18 #define WM8785_MCR_MASTER_768 0x006
19 #define WM8785_OSR_MASK 0x018
[all …]
H A Dwm8766.h5 #define WM8766_LDA1 0x00
6 #define WM8766_RDA1 0x01
7 #define WM8766_DAC_CTRL 0x02
8 #define WM8766_INT_CTRL 0x03
9 #define WM8766_LDA2 0x04
10 #define WM8766_RDA2 0x05
11 #define WM8766_LDA3 0x06
12 #define WM8766_RDA3 0x07
13 #define WM8766_MASTDA 0x08
14 #define WM8766_DAC_CTRL2 0x09
[all …]
/linux/drivers/media/usb/go7007/
H A Ds2250-board.c26 #define TLV320_ADDRESS 0x34
27 #define VPX322_ADDR_ANALOGCONTROL1 0x02
28 #define VPX322_ADDR_BRIGHTNESS0 0x0127
29 #define VPX322_ADDR_BRIGHTNESS1 0x0131
30 #define VPX322_ADDR_CONTRAST0 0x0128
31 #define VPX322_ADDR_CONTRAST1 0x0132
32 #define VPX322_ADDR_HUE 0x00dc
33 #define VPX322_ADDR_SAT 0x0030
50 0x1e, 0x00,
51 0x00, 0x17,
[all …]
/linux/drivers/net/ethernet/ti/
H A Dam65-cpsw-qos.h49 #define AM65_CPSW_REG_CTL 0x004
50 #define AM65_CPSW_PN_REG_CTL 0x004
51 #define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
52 #define AM65_CPSW_PN_REG_EST_CTL 0x060
53 #define AM65_CPSW_PN_REG_PRI_CIR(pri) (0x140 + 4 * (pri))
54 #define AM65_CPSW_P0_REG_PRI_EIR(pri) (0x160 + 4 * (pri))
56 #define AM65_CPSW_PN_REG_CTL 0x004
57 #define AM65_CPSW_PN_REG_TX_PRI_MAP 0x018
58 #define AM65_CPSW_PN_REG_RX_PRI_MAP 0x020
59 #define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
[all …]
/linux/Documentation/devicetree/bindings/powerpc/4xx/
H A Dppc440spe-adma.txt23 reg = <0x00000004 0x00100000 0x100>;
24 dcr-reg = <0x060 0x020>;
34 (typically 0x0 and 0x1 for DMA0 and DMA1)
46 cell-index = <0>;
47 reg = <0x00000004 0x00100100 0x100>;
48 dcr-reg = <0x060 0x020>;
50 interrupts = <0 1>;
52 #address-cells = <0>;
53 #size-cells = <0>;
55 0 &UIC0 0x14 4
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7986-topckgen.c176 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
178 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
179 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
180 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
182 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
184 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
185 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
186 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
187 0x014, 0x018, 8, 2, 15, 0x1C0, 5),
188 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
[all …]
H A Dclk-mt7981-topckgen.c293 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
295 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
297 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2),
299 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
302 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4),
304 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5),
306 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6),
308 pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31,
309 0x1C0, 7),
312 emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7,
[all …]
H A Dclk-mt7622.c217 .set_ofs = 0x120,
218 .clr_ofs = 0x120,
219 .sta_ofs = 0x120,
223 .set_ofs = 0x128,
224 .clr_ofs = 0x128,
225 .sta_ofs = 0x128,
229 .set_ofs = 0x8,
230 .clr_ofs = 0x10,
231 .sta_ofs = 0x18,
235 .set_ofs = 0xC,
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]

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