Lines Matching +full:0 +full:x060
31 .m = _SUNXI_CCU_DIV(0, 2),
34 .reg = 0x000,
54 #define SUN50I_A64_PLL_AUDIO_REG 0x008
57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
62 "osc24M", 0x008,
64 0, 5, /* M */
66 0x284, BIT(31),
72 "osc24M", 0x010,
76 0, 4, /* M */
79 270000000, /* frac rate 0 */
86 "osc24M", 0x018,
88 0, 4, /* M */
91 270000000, /* frac rate 0 */
98 "osc24M", 0x020,
101 0, 2, /* M */
113 .reg = 0x028,
127 .reg = 0x02c,
135 "osc24M", 0x030,
139 0, 4, /* M */
142 270000000, /* frac rate 0 */
149 "osc24M", 0x038,
151 0, 4, /* M */
154 270000000, /* frac rate 0 */
166 #define SUN50I_A64_PLL_MIPI_REG 0x040
178 .m = _SUNXI_CCU_DIV(0, 4),
182 .reg = 0x040,
193 "osc24M", 0x044,
195 0, 4, /* M */
198 270000000, /* frac rate 0 */
205 "osc24M", 0x048,
207 0, 4, /* M */
210 270000000, /* frac rate 0 */
217 "osc24M", 0x04c,
219 0, 2, /* M */
227 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
229 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
248 .reg = 0x054,
253 0),
258 { .val = 0, .div = 2 },
265 0x054, 8, 2, apb1_div_table, 0);
270 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
271 0, 5, /* M */
274 0);
282 .shift = 0,
289 .reg = 0x05c,
294 0),
299 0x060, BIT(1), 0);
301 0x060, BIT(5), 0);
303 0x060, BIT(6), 0);
305 0x060, BIT(8), 0);
307 0x060, BIT(9), 0);
309 0x060, BIT(10), 0);
311 0x060, BIT(13), 0);
313 0x060, BIT(14), 0);
315 0x060, BIT(17), 0);
317 0x060, BIT(18), 0);
319 0x060, BIT(19), 0);
321 0x060, BIT(20), 0);
323 0x060, BIT(21), 0);
325 0x060, BIT(23), 0);
327 0x060, BIT(24), 0);
329 0x060, BIT(25), 0);
331 0x060, BIT(28), 0);
333 0x060, BIT(29), 0);
336 0x064, BIT(0), 0);
338 0x064, BIT(3), 0);
340 0x064, BIT(4), 0);
342 0x064, BIT(5), 0);
344 0x064, BIT(8), 0);
346 0x064, BIT(11), 0);
348 0x064, BIT(12), 0);
350 0x064, BIT(20), 0);
352 0x064, BIT(21), 0);
354 0x064, BIT(22), 0);
357 0x068, BIT(0), 0);
359 0x068, BIT(1), 0);
361 0x068, BIT(5), 0);
363 0x068, BIT(8), 0);
365 0x068, BIT(12), 0);
367 0x068, BIT(13), 0);
369 0x068, BIT(14), 0);
372 0x06c, BIT(0), 0);
374 0x06c, BIT(1), 0);
376 0x06c, BIT(2), 0);
378 0x06c, BIT(5), 0);
380 0x06c, BIT(16), 0);
382 0x06c, BIT(17), 0);
384 0x06c, BIT(18), 0);
386 0x06c, BIT(19), 0);
388 0x06c, BIT(20), 0);
391 0x070, BIT(7), 0);
394 { .val = 0, .div = 1 },
403 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table),
406 .reg = 0x074,
410 0),
416 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
417 0, 4, /* M */
421 0);
437 mmc_default_parents, 0x088,
438 0, 4, /* M */
443 0);
446 mmc_default_parents, 0x08c,
447 0, 4, /* M */
452 0);
455 mmc_default_parents, 0x090,
456 0, 4, /* M */
461 0);
464 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
465 0, 4, /* M */
469 0);
471 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c,
472 0, 4, /* M */
476 0);
478 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
479 0, 4, /* M */
483 0);
485 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
486 0, 4, /* M */
490 0);
495 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
498 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
501 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
504 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
507 0x0cc, BIT(8), 0);
509 0x0cc, BIT(9), 0);
511 0x0cc, BIT(10), 0);
513 0x0cc, BIT(11), 0);
515 0x0cc, BIT(16), 0);
517 0x0cc, BIT(17), 0);
521 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
524 0x100, BIT(0), 0);
526 0x100, BIT(1), 0);
528 0x100, BIT(2), 0);
530 0x100, BIT(3), 0);
534 0x104, 0, 4, 24, 3, BIT(31),
541 #define SUN50I_A64_TCON0_CLK_REG 0x118
544 static const u8 tcon0_table[] = { 0, 2, };
546 tcon0_table, 0x118, 24, 3, BIT(31),
550 static const u8 tcon1_table[] = { 0, 2, };
552 tcon1_table, 0x11c,
553 0, 4, /* M */
560 0x124, 0, 4, 24, 3, BIT(31), 0);
563 0x130, BIT(31), 0);
567 0x134, 16, 4, 24, 3, BIT(31), 0);
571 0x134, 0, 5, 8, 3, BIT(15), 0);
574 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
577 0x140, BIT(31), CLK_SET_RATE_PARENT);
580 0x140, BIT(30), CLK_SET_RATE_PARENT);
583 0x144, BIT(31), 0);
587 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
590 0x154, BIT(31), 0);
595 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
598 static const u8 dsi_dphy_table[] = { 0, 2, };
601 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
604 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
607 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
628 1, 2, 0);
631 1, 2, 0);
862 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
863 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
864 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
866 [RST_DRAM] = { 0x0f4, BIT(31) },
867 [RST_MBUS] = { 0x0fc, BIT(31) },
869 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
870 [RST_BUS_CE] = { 0x2c0, BIT(5) },
871 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
872 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
873 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
874 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
875 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
876 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
877 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
878 [RST_BUS_TS] = { 0x2c0, BIT(18) },
879 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
880 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
881 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
882 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
883 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
884 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
885 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
886 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
888 [RST_BUS_VE] = { 0x2c4, BIT(0) },
889 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
890 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
891 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
892 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
893 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
894 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
895 [RST_BUS_DE] = { 0x2c4, BIT(12) },
896 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
897 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
898 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
899 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
901 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
903 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
904 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
905 [RST_BUS_THS] = { 0x2d0, BIT(8) },
906 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
907 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
908 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
910 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
911 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
912 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
913 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
914 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
915 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
916 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
917 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
918 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
951 reg = devm_platform_ioremap_resource(pdev, 0); in sun50i_a64_ccu_probe()
958 writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); in sun50i_a64_ccu_probe()
960 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); in sun50i_a64_ccu_probe()
965 writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG); in sun50i_a64_ccu_probe()
978 return 0; in sun50i_a64_ccu_probe()