Lines Matching +full:0 +full:x060
32 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
34 .m = _SUNXI_CCU_DIV(0, 2),
37 .reg = 0x000,
41 0),
57 #define SUN4I_PLL_AUDIO_REG 0x008
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
66 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
67 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
68 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
69 0x00c, BIT(31)),
71 .reg = 0x008,
76 0),
83 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
87 .reg = 0x010,
94 0),
100 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
102 .m = _SUNXI_CCU_DIV(0, 2),
105 .reg = 0x018,
109 0),
115 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
118 .reg = 0x018,
122 0),
128 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
131 .reg = 0x020,
135 0),
139 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
145 .reg = 0x020,
148 0),
154 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
157 .reg = 0x028,
161 0),
172 .div = _SUNXI_CCU_DIV(0, 2),
175 .reg = 0x028,
179 &ccu_div_ops, 0),
185 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
189 .reg = 0x030,
196 0),
203 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
206 .reg = 0x040,
210 0),
214 static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
222 #define SUN4I_AHB_REG 0x054
231 .reg = 0x054,
240 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
245 .reg = 0x054,
246 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
266 .reg = 0x054,
270 0),
275 { .val = 0, .div = 2 },
282 0x054, 8, 2, apb0_div_table, 0);
285 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
286 0, 5, /* M */
289 0);
293 0x05c, BIT(31), 0);
296 0x060, BIT(0), 0);
298 0x060, BIT(1), 0);
300 0x060, BIT(2), 0);
302 0x060, BIT(3), 0);
304 0x060, BIT(4), 0);
306 0x060, BIT(5), 0);
308 0x060, BIT(6), 0);
310 0x060, BIT(7), 0);
312 0x060, BIT(8), 0);
314 0x060, BIT(9), 0);
316 0x060, BIT(10), 0);
318 0x060, BIT(11), 0);
320 0x060, BIT(12), 0);
322 0x060, BIT(13), 0);
324 0x060, BIT(14), CLK_IS_CRITICAL);
327 0x060, BIT(16), 0);
329 0x060, BIT(17), 0);
331 0x060, BIT(18), 0);
333 0x060, BIT(20), 0);
335 0x060, BIT(21), 0);
337 0x060, BIT(22), 0);
339 0x060, BIT(23), 0);
341 0x060, BIT(24), 0);
344 0x060, BIT(25), 0);
347 0x060, BIT(26), 0);
350 0x060, BIT(28), 0);
353 0x064, BIT(0), 0);
355 0x064, BIT(1), 0);
357 0x064, BIT(2), 0);
359 0x064, BIT(3), 0);
361 0x064, BIT(4), 0);
363 0x064, BIT(5), 0);
365 0x064, BIT(8), 0);
367 0x064, BIT(9), 0);
370 0x064, BIT(10), 0);
372 0x064, BIT(11), 0);
374 0x064, BIT(12), 0);
376 0x064, BIT(13), 0);
378 0x064, BIT(14), 0);
380 0x064, BIT(15), 0);
383 0x064, BIT(17), 0);
385 0x064, BIT(18), 0);
387 0x064, BIT(20), 0);
390 0x068, BIT(0), 0);
392 0x068, BIT(1), 0);
394 0x068, BIT(2), 0);
396 0x068, BIT(3), 0);
399 0x068, BIT(4), 0);
401 0x068, BIT(5), 0);
403 0x068, BIT(6), 0);
405 0x068, BIT(7), 0);
408 0x068, BIT(8), 0);
410 0x068, BIT(10), 0);
413 0x06c, BIT(0), 0);
415 0x06c, BIT(1), 0);
417 0x06c, BIT(2), 0);
420 0x06c, BIT(3), 0);
422 0x06c, BIT(4), 0);
424 0x06c, BIT(5), 0);
426 0x06c, BIT(6), 0);
428 0x06c, BIT(7), 0);
431 0x06c, BIT(15), 0);
433 0x06c, BIT(16), 0);
435 0x06c, BIT(17), 0);
437 0x06c, BIT(18), 0);
439 0x06c, BIT(19), 0);
441 0x06c, BIT(20), 0);
443 0x06c, BIT(21), 0);
445 0x06c, BIT(22), 0);
447 0x06c, BIT(23), 0);
451 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
452 0, 4, /* M */
456 0);
459 static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
460 0, 4, /* M */
464 0);
466 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
467 0, 4, /* M */
471 0);
475 0x088, 8, 3, 0);
477 0x088, 20, 3, 0);
479 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
480 0, 4, /* M */
484 0);
488 0x08c, 8, 3, 0);
490 0x08c, 20, 3, 0);
492 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
493 0, 4, /* M */
497 0);
501 0x090, 8, 3, 0);
503 0x090, 20, 3, 0);
505 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
506 0, 4, /* M */
510 0);
514 0x094, 8, 3, 0);
516 0x094, 20, 3, 0);
518 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
519 0, 4, /* M */
523 0);
525 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
526 0, 4, /* M */
530 0);
532 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
533 0, 4, /* M */
537 0);
539 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
540 0, 4, /* M */
544 0);
546 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
547 0, 4, /* M */
551 0);
554 static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
555 0, 4, /* M */
559 0);
564 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,
565 0, 4, /* M */
569 0);
571 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,
572 0, 4, /* M */
576 0);
579 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,
580 0, 4, /* M */
584 0);
586 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,
587 0, 4, /* M */
591 0);
596 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
599 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
603 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
606 static const u8 keypad_table[] = { 0, 2 };
609 .m = _SUNXI_CCU_DIV(0, 5),
613 .reg = 0x0c4,
617 0),
628 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
632 0x0cc, BIT(6), 0);
634 0x0cc, BIT(7), 0);
636 0x0cc, BIT(8), 0);
638 /* TODO: GPS CLK 0x0d0 */
640 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
641 0, 4, /* M */
645 0);
649 0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
653 0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
656 0x100, BIT(0), 0);
658 0x100, BIT(1), 0);
660 0x100, BIT(2), 0);
662 0x100, BIT(3), 0);
664 0x100, BIT(4), 0);
666 0x100, BIT(5), 0);
668 0x100, BIT(6), 0);
672 0x100, BIT(15), CLK_IS_CRITICAL);
674 0x100, BIT(24), 0);
676 0x100, BIT(25), 0);
678 0x100, BIT(26), 0);
680 0x100, BIT(27), 0);
682 0x100, BIT(28), 0);
684 0x100, BIT(29), 0);
689 0x104, 0, 4, 24, 2, BIT(31), 0);
692 0x108, 0, 4, 24, 2, BIT(31), 0);
695 0x10c, 0, 4, 24, 2, BIT(31), 0);
698 0x110, 0, 4, 24, 2, BIT(31), 0);
702 0x114, 0, 4, 24, 2, BIT(31), 0);
707 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
709 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
716 0x120, 0, 4, 24, 2, BIT(31), 0);
721 0x128, 24, 1, BIT(31), 0);
726 0x128,
727 0, 4, /* M */
731 0);
734 0x128, 0, 4, BIT(31), 0);
738 0x12c, 0, 4, 24, 2, BIT(31),
743 0x12c, 11, 1, BIT(15),
748 0x130, 0, 4, 24, 2, BIT(31),
753 0x130, 11, 1, BIT(15),
758 static const u8 csi_table[] = { 0, 1, 2, 5, 6};
761 0x134, 0, 5, 24, 3, BIT(31), 0);
765 0x138, 0, 5, 24, 3, BIT(31), 0);
767 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
770 0x140, BIT(31), CLK_SET_RATE_PARENT);
772 static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
776 0x148, 0, 4, 24, 1, BIT(31), 0);
779 0x150, 0, 4, 24, 2, BIT(31),
786 0x154, 0, 4, 24, 2, BIT(31),
792 static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };
795 0x154, 0, 4, 24, 3, BIT(31),
801 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
802 0);
806 0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
809 static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
812 static const u8 hdmi1_table[] = { 0, 1};
815 0x17c, 0, 4, 24, 2, BIT(31),
820 { .index = 0, .div = 750, },
834 .reg = 0x1f0,
839 0),
853 .reg = 0x1f4,
858 0),
1386 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1387 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1388 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1389 [RST_GPS] = { 0x0d0, BIT(0) },
1390 [RST_DE_BE0] = { 0x104, BIT(30) },
1391 [RST_DE_BE1] = { 0x108, BIT(30) },
1392 [RST_DE_FE0] = { 0x10c, BIT(30) },
1393 [RST_DE_FE1] = { 0x110, BIT(30) },
1394 [RST_DE_MP] = { 0x114, BIT(30) },
1395 [RST_TVE0] = { 0x118, BIT(29) },
1396 [RST_TCON0] = { 0x118, BIT(30) },
1397 [RST_TVE1] = { 0x11c, BIT(29) },
1398 [RST_TCON1] = { 0x11c, BIT(30) },
1399 [RST_CSI0] = { 0x134, BIT(30) },
1400 [RST_CSI1] = { 0x138, BIT(30) },
1401 [RST_VE] = { 0x13c, BIT(0) },
1402 [RST_ACE] = { 0x148, BIT(16) },
1403 [RST_LVDS] = { 0x14c, BIT(0) },
1404 [RST_GPU] = { 0x154, BIT(30) },
1405 [RST_HDMI_H] = { 0x170, BIT(0) },
1406 [RST_HDMI_SYS] = { 0x170, BIT(1) },
1407 [RST_HDMI_AUDIO_DMA] = { 0x170, BIT(2) },
1440 reg = devm_platform_ioremap_resource(pdev, 0); in sun4i_a10_ccu_probe()