1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10 #include <linux/regmap.h>
11
12 #include "ccu_common.h"
13 #include "ccu_reset.h"
14
15 #include "ccu_div.h"
16 #include "ccu_gate.h"
17 #include "ccu_mp.h"
18 #include "ccu_mult.h"
19 #include "ccu_nk.h"
20 #include "ccu_nkm.h"
21 #include "ccu_nkmp.h"
22 #include "ccu_nm.h"
23 #include "ccu_phase.h"
24
25 #include "ccu-sun8i-r40.h"
26
27 /* TODO: The result of N*K is required to be in [10, 88] range. */
28 static struct ccu_nkmp pll_cpu_clk = {
29 .enable = BIT(31),
30 .lock = BIT(28),
31 .n = _SUNXI_CCU_MULT(8, 5),
32 .k = _SUNXI_CCU_MULT(4, 2),
33 .m = _SUNXI_CCU_DIV(0, 2),
34 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
35 .common = {
36 .reg = 0x000,
37 .hw.init = CLK_HW_INIT("pll-cpu",
38 "osc24M",
39 &ccu_nkmp_ops,
40 CLK_SET_RATE_UNGATE),
41 },
42 };
43
44 /*
45 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
46 * the base (2x, 4x and 8x), and one variable divider (the one true
47 * pll audio).
48 *
49 * With sigma-delta modulation for fractional-N on the audio PLL,
50 * we have to use specific dividers. This means the variable divider
51 * can no longer be used, as the audio codec requests the exact clock
52 * rates we support through this mechanism. So we now hard code the
53 * variable divider to 1. This means the clock rates will no longer
54 * match the clock names.
55 */
56 #define SUN8I_R40_PLL_AUDIO_REG 0x008
57
58 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
59 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
60 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
61 };
62
63 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
64 "osc24M", 0x008,
65 8, 7, /* N */
66 0, 5, /* M */
67 pll_audio_sdm_table, BIT(24),
68 0x284, BIT(31),
69 BIT(31), /* gate */
70 BIT(28), /* lock */
71 CLK_SET_RATE_UNGATE);
72
73 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
74 "osc24M", 0x0010,
75 192000000, /* Minimum rate */
76 1008000000, /* Maximum rate */
77 8, 7, /* N */
78 0, 4, /* M */
79 BIT(24), /* frac enable */
80 BIT(25), /* frac select */
81 270000000, /* frac rate 0 */
82 297000000, /* frac rate 1 */
83 BIT(31), /* gate */
84 BIT(28), /* lock */
85 CLK_SET_RATE_UNGATE);
86
87 /* TODO: The result of N/M is required to be in [8, 25] range. */
88 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
89 "osc24M", 0x0018,
90 8, 7, /* N */
91 0, 4, /* M */
92 BIT(24), /* frac enable */
93 BIT(25), /* frac select */
94 270000000, /* frac rate 0 */
95 297000000, /* frac rate 1 */
96 BIT(31), /* gate */
97 BIT(28), /* lock */
98 CLK_SET_RATE_UNGATE);
99
100 /* TODO: The result of N*K is required to be in [10, 77] range. */
101 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
102 "osc24M", 0x020,
103 8, 5, /* N */
104 4, 2, /* K */
105 0, 2, /* M */
106 BIT(31), /* gate */
107 BIT(28), /* lock */
108 CLK_SET_RATE_UNGATE);
109
110 /* TODO: The result of N*K is required to be in [21, 58] range. */
111 static struct ccu_nk pll_periph0_clk = {
112 .enable = BIT(31),
113 .lock = BIT(28),
114 .n = _SUNXI_CCU_MULT(8, 5),
115 .k = _SUNXI_CCU_MULT(4, 2),
116 .fixed_post_div = 2,
117 .common = {
118 .reg = 0x028,
119 .features = CCU_FEATURE_FIXED_POSTDIV,
120 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
121 &ccu_nk_ops,
122 CLK_SET_RATE_UNGATE),
123 },
124 };
125
126 static struct ccu_div pll_periph0_sata_clk = {
127 .enable = BIT(24),
128 .div = _SUNXI_CCU_DIV(0, 2),
129 /*
130 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
131 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
132 * 6/2 = 3.
133 */
134 .fixed_post_div = 3,
135 .common = {
136 .reg = 0x028,
137 .features = CCU_FEATURE_FIXED_POSTDIV,
138 .hw.init = CLK_HW_INIT("pll-periph0-sata",
139 "pll-periph0",
140 &ccu_div_ops, 0),
141 },
142 };
143
144 /* TODO: The result of N*K is required to be in [21, 58] range. */
145 static struct ccu_nk pll_periph1_clk = {
146 .enable = BIT(31),
147 .lock = BIT(28),
148 .n = _SUNXI_CCU_MULT(8, 5),
149 .k = _SUNXI_CCU_MULT(4, 2),
150 .fixed_post_div = 2,
151 .common = {
152 .reg = 0x02c,
153 .features = CCU_FEATURE_FIXED_POSTDIV,
154 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
155 &ccu_nk_ops,
156 CLK_SET_RATE_UNGATE),
157 },
158 };
159
160 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1",
161 "osc24M", 0x030,
162 192000000, /* Minimum rate */
163 1008000000, /* Maximum rate */
164 8, 7, /* N */
165 0, 4, /* M */
166 BIT(24), /* frac enable */
167 BIT(25), /* frac select */
168 270000000, /* frac rate 0 */
169 297000000, /* frac rate 1 */
170 BIT(31), /* gate */
171 BIT(28), /* lock */
172 CLK_SET_RATE_UNGATE);
173
174 static struct ccu_nkm pll_sata_clk = {
175 .enable = BIT(31),
176 .lock = BIT(28),
177 .n = _SUNXI_CCU_MULT(8, 5),
178 .k = _SUNXI_CCU_MULT(4, 2),
179 .m = _SUNXI_CCU_DIV(0, 2),
180 .fixed_post_div = 6,
181 .common = {
182 .reg = 0x034,
183 .features = CCU_FEATURE_FIXED_POSTDIV,
184 .hw.init = CLK_HW_INIT("pll-sata", "osc24M",
185 &ccu_nkm_ops,
186 CLK_SET_RATE_UNGATE),
187 },
188 };
189
190 static const char * const pll_sata_out_parents[] = { "pll-sata",
191 "pll-periph0-sata" };
192 static SUNXI_CCU_MUX_WITH_GATE(pll_sata_out_clk, "pll-sata-out",
193 pll_sata_out_parents, 0x034,
194 30, 1, /* mux */
195 BIT(14), /* gate */
196 CLK_SET_RATE_PARENT);
197
198 /* TODO: The result of N/M is required to be in [8, 25] range. */
199 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
200 "osc24M", 0x038,
201 8, 7, /* N */
202 0, 4, /* M */
203 BIT(24), /* frac enable */
204 BIT(25), /* frac select */
205 270000000, /* frac rate 0 */
206 297000000, /* frac rate 1 */
207 BIT(31), /* gate */
208 BIT(28), /* lock */
209 CLK_SET_RATE_UNGATE);
210
211 /*
212 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
213 *
214 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
215 * integer / fractional clock with switchable multipliers and dividers.
216 * This is not supported here. We hardcode the PLL to MIPI mode.
217 *
218 * TODO: In the MIPI mode, M/N is required to be equal or lesser than 3,
219 * which cannot be implemented now.
220 */
221 #define SUN8I_R40_PLL_MIPI_REG 0x040
222
223 static const char * const pll_mipi_parents[] = { "pll-video0" };
224 static struct ccu_nkm pll_mipi_clk = {
225 .enable = BIT(31) | BIT(23) | BIT(22),
226 .lock = BIT(28),
227 .n = _SUNXI_CCU_MULT(8, 4),
228 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2),
229 .m = _SUNXI_CCU_DIV(0, 4),
230 .mux = _SUNXI_CCU_MUX(21, 1),
231 .common = {
232 .reg = 0x040,
233 .hw.init = CLK_HW_INIT_PARENTS("pll-mipi",
234 pll_mipi_parents,
235 &ccu_nkm_ops,
236 CLK_SET_RATE_UNGATE)
237 },
238 };
239
240 /* TODO: The result of N/M is required to be in [8, 25] range. */
241 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
242 "osc24M", 0x048,
243 8, 7, /* N */
244 0, 4, /* M */
245 BIT(24), /* frac enable */
246 BIT(25), /* frac select */
247 270000000, /* frac rate 0 */
248 297000000, /* frac rate 1 */
249 BIT(31), /* gate */
250 BIT(28), /* lock */
251 CLK_SET_RATE_UNGATE);
252
253 /* TODO: The N factor is required to be in [16, 75] range. */
254 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1",
255 "osc24M", 0x04c,
256 8, 7, /* N */
257 0, 2, /* M */
258 BIT(31), /* gate */
259 BIT(28), /* lock */
260 CLK_SET_RATE_UNGATE);
261
262 static const char * const cpu_parents[] = { "osc32k", "osc24M",
263 "pll-cpu", "pll-cpu" };
264 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
265 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
266
267 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
268
269 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
270 "axi", "pll-periph0" };
271 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
272 { .index = 3, .shift = 6, .width = 2 },
273 };
274 static struct ccu_div ahb1_clk = {
275 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
276
277 .mux = {
278 .shift = 12,
279 .width = 2,
280
281 .var_predivs = ahb1_predivs,
282 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
283 },
284
285 .common = {
286 .reg = 0x054,
287 .features = CCU_FEATURE_VARIABLE_PREDIV,
288 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
289 ahb1_parents,
290 &ccu_div_ops,
291 0),
292 },
293 };
294
295 static struct clk_div_table apb1_div_table[] = {
296 { .val = 0, .div = 2 },
297 { .val = 1, .div = 2 },
298 { .val = 2, .div = 4 },
299 { .val = 3, .div = 8 },
300 { /* Sentinel */ },
301 };
302 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
303 0x054, 8, 2, apb1_div_table, 0);
304
305 static const char * const apb2_parents[] = { "osc32k", "osc24M",
306 "pll-periph0-2x",
307 "pll-periph0-2x" };
308 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
309 0, 5, /* M */
310 16, 2, /* P */
311 24, 2, /* mux */
312 0);
313
314 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
315 0x060, BIT(1), 0);
316 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1",
317 0x060, BIT(5), 0);
318 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
319 0x060, BIT(6), 0);
320 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
321 0x060, BIT(8), 0);
322 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
323 0x060, BIT(9), 0);
324 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
325 0x060, BIT(10), 0);
326 static SUNXI_CCU_GATE(bus_mmc3_clk, "bus-mmc3", "ahb1",
327 0x060, BIT(11), 0);
328 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
329 0x060, BIT(13), 0);
330 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
331 0x060, BIT(14), 0);
332 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb1",
333 0x060, BIT(17), 0);
334 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1",
335 0x060, BIT(18), 0);
336 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
337 0x060, BIT(19), 0);
338 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
339 0x060, BIT(20), 0);
340 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
341 0x060, BIT(21), 0);
342 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb1",
343 0x060, BIT(22), 0);
344 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb1",
345 0x060, BIT(23), 0);
346 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb1",
347 0x060, BIT(24), 0);
348 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
349 0x060, BIT(25), 0);
350 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1",
351 0x060, BIT(26), 0);
352 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb1",
353 0x060, BIT(27), 0);
354 static SUNXI_CCU_GATE(bus_ehci2_clk, "bus-ehci2", "ahb1",
355 0x060, BIT(28), 0);
356 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1",
357 0x060, BIT(29), 0);
358 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb1",
359 0x060, BIT(30), 0);
360 static SUNXI_CCU_GATE(bus_ohci2_clk, "bus-ohci2", "ahb1",
361 0x060, BIT(31), 0);
362
363 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
364 0x064, BIT(0), 0);
365 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb1",
366 0x064, BIT(2), 0);
367 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1",
368 0x064, BIT(5), 0);
369 static SUNXI_CCU_GATE(bus_csi0_clk, "bus-csi0", "ahb1",
370 0x064, BIT(8), 0);
371 static SUNXI_CCU_GATE(bus_csi1_clk, "bus-csi1", "ahb1",
372 0x064, BIT(9), 0);
373 static SUNXI_CCU_GATE(bus_hdmi0_clk, "bus-hdmi0", "ahb1",
374 0x064, BIT(10), 0);
375 static SUNXI_CCU_GATE(bus_hdmi1_clk, "bus-hdmi1", "ahb1",
376 0x064, BIT(11), 0);
377 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
378 0x064, BIT(12), 0);
379 static SUNXI_CCU_GATE(bus_tve0_clk, "bus-tve0", "ahb1",
380 0x064, BIT(13), 0);
381 static SUNXI_CCU_GATE(bus_tve1_clk, "bus-tve1", "ahb1",
382 0x064, BIT(14), 0);
383 static SUNXI_CCU_GATE(bus_tve_top_clk, "bus-tve-top", "ahb1",
384 0x064, BIT(15), 0);
385 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
386 0x064, BIT(17), 0);
387 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
388 0x064, BIT(20), 0);
389 static SUNXI_CCU_GATE(bus_tvd0_clk, "bus-tvd0", "ahb1",
390 0x064, BIT(21), 0);
391 static SUNXI_CCU_GATE(bus_tvd1_clk, "bus-tvd1", "ahb1",
392 0x064, BIT(22), 0);
393 static SUNXI_CCU_GATE(bus_tvd2_clk, "bus-tvd2", "ahb1",
394 0x064, BIT(23), 0);
395 static SUNXI_CCU_GATE(bus_tvd3_clk, "bus-tvd3", "ahb1",
396 0x064, BIT(24), 0);
397 static SUNXI_CCU_GATE(bus_tvd_top_clk, "bus-tvd-top", "ahb1",
398 0x064, BIT(25), 0);
399 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb1",
400 0x064, BIT(26), 0);
401 static SUNXI_CCU_GATE(bus_tcon_lcd1_clk, "bus-tcon-lcd1", "ahb1",
402 0x064, BIT(27), 0);
403 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb1",
404 0x064, BIT(28), 0);
405 static SUNXI_CCU_GATE(bus_tcon_tv1_clk, "bus-tcon-tv1", "ahb1",
406 0x064, BIT(29), 0);
407 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb1",
408 0x064, BIT(30), 0);
409
410 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
411 0x068, BIT(0), 0);
412 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
413 0x068, BIT(1), 0);
414 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb1",
415 0x068, BIT(2), 0);
416 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
417 0x068, BIT(5), 0);
418 static SUNXI_CCU_GATE(bus_ir0_clk, "bus-ir0", "apb1",
419 0x068, BIT(6), 0);
420 static SUNXI_CCU_GATE(bus_ir1_clk, "bus-ir1", "apb1",
421 0x068, BIT(7), 0);
422 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1",
423 0x068, BIT(8), 0);
424 static SUNXI_CCU_GATE(bus_keypad_clk, "bus-keypad", "apb1",
425 0x068, BIT(10), 0);
426 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
427 0x068, BIT(12), 0);
428 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
429 0x068, BIT(13), 0);
430 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
431 0x068, BIT(14), 0);
432
433 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
434 0x06c, BIT(0), 0);
435 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
436 0x06c, BIT(1), 0);
437 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
438 0x06c, BIT(2), 0);
439 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2",
440 0x06c, BIT(3), 0);
441 /*
442 * In datasheet here's "Reserved", however the gate exists in BSP soucre
443 * code.
444 */
445 static SUNXI_CCU_GATE(bus_can_clk, "bus-can", "apb2",
446 0x06c, BIT(4), 0);
447 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2",
448 0x06c, BIT(5), 0);
449 static SUNXI_CCU_GATE(bus_ps20_clk, "bus-ps20", "apb2",
450 0x06c, BIT(6), 0);
451 static SUNXI_CCU_GATE(bus_ps21_clk, "bus-ps21", "apb2",
452 0x06c, BIT(7), 0);
453 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb2",
454 0x06c, BIT(15), 0);
455 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
456 0x06c, BIT(16), 0);
457 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
458 0x06c, BIT(17), 0);
459 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
460 0x06c, BIT(18), 0);
461 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
462 0x06c, BIT(19), 0);
463 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
464 0x06c, BIT(20), 0);
465 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb2",
466 0x06c, BIT(21), 0);
467 static SUNXI_CCU_GATE(bus_uart6_clk, "bus-uart6", "apb2",
468 0x06c, BIT(22), 0);
469 static SUNXI_CCU_GATE(bus_uart7_clk, "bus-uart7", "apb2",
470 0x06c, BIT(23), 0);
471
472 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1",
473 0x070, BIT(7), 0);
474
475 static const char * const ths_parents[] = { "osc24M" };
476 static struct ccu_div ths_clk = {
477 .enable = BIT(31),
478 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
479 .mux = _SUNXI_CCU_MUX(24, 2),
480 .common = {
481 .reg = 0x074,
482 .hw.init = CLK_HW_INIT_PARENTS("ths",
483 ths_parents,
484 &ccu_div_ops,
485 0),
486 },
487 };
488
489 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
490 "pll-periph1" };
491 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
492 0, 4, /* M */
493 16, 2, /* P */
494 24, 2, /* mux */
495 BIT(31), /* gate */
496 0);
497
498 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
499 0, 4, /* M */
500 16, 2, /* P */
501 24, 2, /* mux */
502 BIT(31), /* gate */
503 0);
504
505 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
506 0, 4, /* M */
507 16, 2, /* P */
508 24, 2, /* mux */
509 BIT(31), /* gate */
510 0);
511
512 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
513 0, 4, /* M */
514 16, 2, /* P */
515 24, 2, /* mux */
516 BIT(31), /* gate */
517 0);
518
519 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
520 0, 4, /* M */
521 16, 2, /* P */
522 24, 2, /* mux */
523 BIT(31), /* gate */
524 0);
525
526 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
527 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
528 0, 4, /* M */
529 16, 2, /* P */
530 24, 4, /* mux */
531 BIT(31), /* gate */
532 0);
533
534 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x",
535 "pll-periph1-2x" };
536 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
537 0, 4, /* M */
538 16, 2, /* P */
539 24, 2, /* mux */
540 BIT(31), /* gate */
541 0);
542
543 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
544 0, 4, /* M */
545 16, 2, /* P */
546 24, 2, /* mux */
547 BIT(31), /* gate */
548 0);
549
550 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
551 0, 4, /* M */
552 16, 2, /* P */
553 24, 2, /* mux */
554 BIT(31), /* gate */
555 0);
556
557 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
558 0, 4, /* M */
559 16, 2, /* P */
560 24, 2, /* mux */
561 BIT(31), /* gate */
562 0);
563
564 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
565 0, 4, /* M */
566 16, 2, /* P */
567 24, 2, /* mux */
568 BIT(31), /* gate */
569 0);
570
571 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
572 "pll-audio-2x", "pll-audio" };
573 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
574 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
575
576 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
577 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
578
579 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
580 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
581
582 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", i2s_parents,
583 0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
584
585 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_parents,
586 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
587
588 static const char * const keypad_parents[] = { "osc24M", "osc32k" };
589 static const u8 keypad_table[] = { 0, 2 };
590 static struct ccu_mp keypad_clk = {
591 .enable = BIT(31),
592 .m = _SUNXI_CCU_DIV(0, 5),
593 .p = _SUNXI_CCU_DIV(16, 2),
594 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
595 .common = {
596 .reg = 0x0c4,
597 .hw.init = CLK_HW_INIT_PARENTS("keypad",
598 keypad_parents,
599 &ccu_mp_ops,
600 0),
601 }
602 };
603
604 static const char * const sata_parents[] = { "pll-sata-out", "sata-ext" };
605 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
606 0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
607
608 /*
609 * There are 3 OHCI 12M clock source selection bits in this register.
610 * We will force them to 0 (12M divided from 48M).
611 */
612 #define SUN8I_R40_USB_CLK_REG 0x0cc
613
614 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
615 0x0cc, BIT(8), 0);
616 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
617 0x0cc, BIT(9), 0);
618 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M",
619 0x0cc, BIT(10), 0);
620 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M",
621 0x0cc, BIT(16), 0);
622 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc12M",
623 0x0cc, BIT(17), 0);
624 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc12M",
625 0x0cc, BIT(18), 0);
626
627 static const char * const ir_parents[] = { "osc24M", "pll-periph0",
628 "pll-periph1", "osc32k" };
629 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_clk, "ir0", ir_parents, 0x0d0,
630 0, 4, /* M */
631 16, 2, /* P */
632 24, 2, /* mux */
633 BIT(31), /* gate */
634 0);
635
636 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_clk, "ir1", ir_parents, 0x0d4,
637 0, 4, /* M */
638 16, 2, /* P */
639 24, 2, /* mux */
640 BIT(31), /* gate */
641 0);
642
643 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" };
644 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
645 0x0f4, 0, 2, 20, 2, CLK_IS_CRITICAL);
646
647 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
648 0x100, BIT(0), 0);
649 static SUNXI_CCU_GATE(dram_csi0_clk, "dram-csi0", "dram",
650 0x100, BIT(1), 0);
651 static SUNXI_CCU_GATE(dram_csi1_clk, "dram-csi1", "dram",
652 0x100, BIT(2), 0);
653 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
654 0x100, BIT(3), 0);
655 static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "dram",
656 0x100, BIT(4), 0);
657 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "dram",
658 0x100, BIT(5), 0);
659 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
660 0x100, BIT(6), 0);
661
662 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
663 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
664 0x104, 0, 4, 24, 3, BIT(31),
665 CLK_SET_RATE_PARENT);
666 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
667 0x108, 0, 4, 24, 3, BIT(31), 0);
668
669 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
670 "pll-video0-2x", "pll-video1-2x",
671 "pll-mipi" };
672 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
673 0x110, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
674 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
675 0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
676 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
677 0x118, 0, 4, 24, 3, BIT(31),
678 CLK_SET_RATE_PARENT);
679 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
680 0x11c, 0, 4, 24, 3, BIT(31),
681 CLK_SET_RATE_PARENT);
682
683 static const char * const deinterlace_parents[] = { "pll-periph0",
684 "pll-periph1" };
685 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
686 deinterlace_parents, 0x124, 0, 4, 24, 3,
687 BIT(31), 0);
688
689 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1",
690 "pll-periph1" };
691 static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk", csi_mclk_parents,
692 0x130, 0, 5, 8, 3, BIT(15), 0);
693
694 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
695 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
696 0x134, 16, 4, 24, 3, BIT(31), 0);
697
698 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
699 0x134, 0, 5, 8, 3, BIT(15), 0);
700
701 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
702 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
703
704 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
705 0x140, BIT(31), CLK_SET_RATE_PARENT);
706 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
707 0x144, BIT(31), 0);
708
709 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
710 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
711 0x150, 0, 4, 24, 2, BIT(31),
712 CLK_SET_RATE_PARENT);
713
714 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
715 0x154, BIT(31), 0);
716
717 /*
718 * In the SoC's user manual, the P factor is mentioned, but not used in
719 * the frequency formula.
720 *
721 * Here the factor is included, according to the BSP kernel source,
722 * which contains the P factor of this clock.
723 */
724 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
725 "pll-ddr0" };
726 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x15c,
727 0, 4, /* M */
728 16, 2, /* P */
729 24, 2, /* mux */
730 BIT(31), /* gate */
731 CLK_IS_CRITICAL);
732
733 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-video1",
734 "pll-periph0" };
735 static SUNXI_CCU_M_WITH_MUX_GATE(dsi_dphy_clk, "dsi-dphy", dsi_dphy_parents,
736 0x168, 0, 4, 8, 2, BIT(15), 0);
737
738 static SUNXI_CCU_M_WITH_MUX_GATE(tve0_clk, "tve0", tcon_parents,
739 0x180, 0, 4, 24, 3, BIT(31), 0);
740 static SUNXI_CCU_M_WITH_MUX_GATE(tve1_clk, "tve1", tcon_parents,
741 0x184, 0, 4, 24, 3, BIT(31), 0);
742
743 static const char * const tvd_parents[] = { "pll-video0", "pll-video1",
744 "pll-video0-2x", "pll-video1-2x" };
745 static SUNXI_CCU_M_WITH_MUX_GATE(tvd0_clk, "tvd0", tvd_parents,
746 0x188, 0, 4, 24, 3, BIT(31), 0);
747 static SUNXI_CCU_M_WITH_MUX_GATE(tvd1_clk, "tvd1", tvd_parents,
748 0x18c, 0, 4, 24, 3, BIT(31), 0);
749 static SUNXI_CCU_M_WITH_MUX_GATE(tvd2_clk, "tvd2", tvd_parents,
750 0x190, 0, 4, 24, 3, BIT(31), 0);
751 static SUNXI_CCU_M_WITH_MUX_GATE(tvd3_clk, "tvd3", tvd_parents,
752 0x194, 0, 4, 24, 3, BIT(31), 0);
753
754 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
755 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
756
757 static const char * const out_parents[] = { "osc24M", "osc32k", "osc24M" };
758 static const struct ccu_mux_fixed_prediv out_predivs[] = {
759 { .index = 0, .div = 750, },
760 };
761
762 static struct ccu_mp outa_clk = {
763 .enable = BIT(31),
764 .m = _SUNXI_CCU_DIV(8, 5),
765 .p = _SUNXI_CCU_DIV(20, 2),
766 .mux = {
767 .shift = 24,
768 .width = 2,
769 .fixed_predivs = out_predivs,
770 .n_predivs = ARRAY_SIZE(out_predivs),
771 },
772 .common = {
773 .reg = 0x1f0,
774 .features = CCU_FEATURE_FIXED_PREDIV,
775 .hw.init = CLK_HW_INIT_PARENTS("outa", out_parents,
776 &ccu_mp_ops,
777 CLK_SET_RATE_PARENT),
778 }
779 };
780
781 static struct ccu_mp outb_clk = {
782 .enable = BIT(31),
783 .m = _SUNXI_CCU_DIV(8, 5),
784 .p = _SUNXI_CCU_DIV(20, 2),
785 .mux = {
786 .shift = 24,
787 .width = 2,
788 .fixed_predivs = out_predivs,
789 .n_predivs = ARRAY_SIZE(out_predivs),
790 },
791 .common = {
792 .reg = 0x1f4,
793 .features = CCU_FEATURE_FIXED_PREDIV,
794 .hw.init = CLK_HW_INIT_PARENTS("outb", out_parents,
795 &ccu_mp_ops,
796 CLK_SET_RATE_PARENT),
797 }
798 };
799
800 static struct ccu_common *sun8i_r40_ccu_clks[] = {
801 &pll_cpu_clk.common,
802 &pll_audio_base_clk.common,
803 &pll_video0_clk.common,
804 &pll_ve_clk.common,
805 &pll_ddr0_clk.common,
806 &pll_periph0_clk.common,
807 &pll_periph0_sata_clk.common,
808 &pll_periph1_clk.common,
809 &pll_video1_clk.common,
810 &pll_sata_clk.common,
811 &pll_sata_out_clk.common,
812 &pll_gpu_clk.common,
813 &pll_mipi_clk.common,
814 &pll_de_clk.common,
815 &pll_ddr1_clk.common,
816 &cpu_clk.common,
817 &axi_clk.common,
818 &ahb1_clk.common,
819 &apb1_clk.common,
820 &apb2_clk.common,
821 &bus_mipi_dsi_clk.common,
822 &bus_ce_clk.common,
823 &bus_dma_clk.common,
824 &bus_mmc0_clk.common,
825 &bus_mmc1_clk.common,
826 &bus_mmc2_clk.common,
827 &bus_mmc3_clk.common,
828 &bus_nand_clk.common,
829 &bus_dram_clk.common,
830 &bus_emac_clk.common,
831 &bus_ts_clk.common,
832 &bus_hstimer_clk.common,
833 &bus_spi0_clk.common,
834 &bus_spi1_clk.common,
835 &bus_spi2_clk.common,
836 &bus_spi3_clk.common,
837 &bus_sata_clk.common,
838 &bus_otg_clk.common,
839 &bus_ehci0_clk.common,
840 &bus_ehci1_clk.common,
841 &bus_ehci2_clk.common,
842 &bus_ohci0_clk.common,
843 &bus_ohci1_clk.common,
844 &bus_ohci2_clk.common,
845 &bus_ve_clk.common,
846 &bus_mp_clk.common,
847 &bus_deinterlace_clk.common,
848 &bus_csi0_clk.common,
849 &bus_csi1_clk.common,
850 &bus_hdmi0_clk.common,
851 &bus_hdmi1_clk.common,
852 &bus_de_clk.common,
853 &bus_tve0_clk.common,
854 &bus_tve1_clk.common,
855 &bus_tve_top_clk.common,
856 &bus_gmac_clk.common,
857 &bus_gpu_clk.common,
858 &bus_tvd0_clk.common,
859 &bus_tvd1_clk.common,
860 &bus_tvd2_clk.common,
861 &bus_tvd3_clk.common,
862 &bus_tvd_top_clk.common,
863 &bus_tcon_lcd0_clk.common,
864 &bus_tcon_lcd1_clk.common,
865 &bus_tcon_tv0_clk.common,
866 &bus_tcon_tv1_clk.common,
867 &bus_tcon_top_clk.common,
868 &bus_codec_clk.common,
869 &bus_spdif_clk.common,
870 &bus_ac97_clk.common,
871 &bus_pio_clk.common,
872 &bus_ir0_clk.common,
873 &bus_ir1_clk.common,
874 &bus_ths_clk.common,
875 &bus_keypad_clk.common,
876 &bus_i2s0_clk.common,
877 &bus_i2s1_clk.common,
878 &bus_i2s2_clk.common,
879 &bus_i2c0_clk.common,
880 &bus_i2c1_clk.common,
881 &bus_i2c2_clk.common,
882 &bus_i2c3_clk.common,
883 &bus_can_clk.common,
884 &bus_scr_clk.common,
885 &bus_ps20_clk.common,
886 &bus_ps21_clk.common,
887 &bus_i2c4_clk.common,
888 &bus_uart0_clk.common,
889 &bus_uart1_clk.common,
890 &bus_uart2_clk.common,
891 &bus_uart3_clk.common,
892 &bus_uart4_clk.common,
893 &bus_uart5_clk.common,
894 &bus_uart6_clk.common,
895 &bus_uart7_clk.common,
896 &bus_dbg_clk.common,
897 &ths_clk.common,
898 &nand_clk.common,
899 &mmc0_clk.common,
900 &mmc1_clk.common,
901 &mmc2_clk.common,
902 &mmc3_clk.common,
903 &ts_clk.common,
904 &ce_clk.common,
905 &spi0_clk.common,
906 &spi1_clk.common,
907 &spi2_clk.common,
908 &spi3_clk.common,
909 &i2s0_clk.common,
910 &i2s1_clk.common,
911 &i2s2_clk.common,
912 &ac97_clk.common,
913 &spdif_clk.common,
914 &keypad_clk.common,
915 &sata_clk.common,
916 &usb_phy0_clk.common,
917 &usb_phy1_clk.common,
918 &usb_phy2_clk.common,
919 &usb_ohci0_clk.common,
920 &usb_ohci1_clk.common,
921 &usb_ohci2_clk.common,
922 &ir0_clk.common,
923 &ir1_clk.common,
924 &dram_clk.common,
925 &dram_ve_clk.common,
926 &dram_csi0_clk.common,
927 &dram_csi1_clk.common,
928 &dram_ts_clk.common,
929 &dram_tvd_clk.common,
930 &dram_mp_clk.common,
931 &dram_deinterlace_clk.common,
932 &de_clk.common,
933 &mp_clk.common,
934 &tcon_lcd0_clk.common,
935 &tcon_lcd1_clk.common,
936 &tcon_tv0_clk.common,
937 &tcon_tv1_clk.common,
938 &deinterlace_clk.common,
939 &csi1_mclk_clk.common,
940 &csi_sclk_clk.common,
941 &csi0_mclk_clk.common,
942 &ve_clk.common,
943 &codec_clk.common,
944 &avs_clk.common,
945 &hdmi_clk.common,
946 &hdmi_slow_clk.common,
947 &mbus_clk.common,
948 &dsi_dphy_clk.common,
949 &tve0_clk.common,
950 &tve1_clk.common,
951 &tvd0_clk.common,
952 &tvd1_clk.common,
953 &tvd2_clk.common,
954 &tvd3_clk.common,
955 &gpu_clk.common,
956 &outa_clk.common,
957 &outb_clk.common,
958 };
959
960 /* Fixed Factor clocks */
961 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
962
963 static const struct clk_hw *clk_parent_pll_audio[] = {
964 &pll_audio_base_clk.common.hw
965 };
966
967 /* We hardcode the divider to 1 for now */
968 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
969 clk_parent_pll_audio,
970 1, 1, CLK_SET_RATE_PARENT);
971 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
972 clk_parent_pll_audio,
973 2, 1, CLK_SET_RATE_PARENT);
974 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
975 clk_parent_pll_audio,
976 1, 1, CLK_SET_RATE_PARENT);
977 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
978 clk_parent_pll_audio,
979 1, 2, CLK_SET_RATE_PARENT);
980 static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
981 &pll_periph0_clk.common.hw,
982 1, 2, 0);
983 static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
984 &pll_periph1_clk.common.hw,
985 1, 2, 0);
986 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
987 &pll_video0_clk.common.hw,
988 1, 2, 0);
989 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
990 &pll_video1_clk.common.hw,
991 1, 2, 0);
992
993 static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
994 .hws = {
995 [CLK_OSC_12M] = &osc12M_clk.hw,
996 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
997 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
998 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
999 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
1000 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
1001 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
1002 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
1003 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw,
1004 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
1005 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
1006 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
1007 [CLK_PLL_PERIPH0_SATA] = &pll_periph0_sata_clk.common.hw,
1008 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
1009 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
1010 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
1011 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
1012 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw,
1013 [CLK_PLL_SATA] = &pll_sata_clk.common.hw,
1014 [CLK_PLL_SATA_OUT] = &pll_sata_out_clk.common.hw,
1015 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
1016 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
1017 [CLK_PLL_DE] = &pll_de_clk.common.hw,
1018 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
1019 [CLK_CPU] = &cpu_clk.common.hw,
1020 [CLK_AXI] = &axi_clk.common.hw,
1021 [CLK_AHB1] = &ahb1_clk.common.hw,
1022 [CLK_APB1] = &apb1_clk.common.hw,
1023 [CLK_APB2] = &apb2_clk.common.hw,
1024 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
1025 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
1026 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
1027 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
1028 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
1029 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
1030 [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw,
1031 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
1032 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
1033 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
1034 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
1035 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
1036 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
1037 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
1038 [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw,
1039 [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw,
1040 [CLK_BUS_SATA] = &bus_sata_clk.common.hw,
1041 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
1042 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
1043 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
1044 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
1045 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
1046 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
1047 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
1048 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
1049 [CLK_BUS_MP] = &bus_mp_clk.common.hw,
1050 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
1051 [CLK_BUS_CSI0] = &bus_csi0_clk.common.hw,
1052 [CLK_BUS_CSI1] = &bus_csi1_clk.common.hw,
1053 [CLK_BUS_HDMI0] = &bus_hdmi0_clk.common.hw,
1054 [CLK_BUS_HDMI1] = &bus_hdmi1_clk.common.hw,
1055 [CLK_BUS_DE] = &bus_de_clk.common.hw,
1056 [CLK_BUS_TVE0] = &bus_tve0_clk.common.hw,
1057 [CLK_BUS_TVE1] = &bus_tve1_clk.common.hw,
1058 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
1059 [CLK_BUS_GMAC] = &bus_gmac_clk.common.hw,
1060 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
1061 [CLK_BUS_TVD0] = &bus_tvd0_clk.common.hw,
1062 [CLK_BUS_TVD1] = &bus_tvd1_clk.common.hw,
1063 [CLK_BUS_TVD2] = &bus_tvd2_clk.common.hw,
1064 [CLK_BUS_TVD3] = &bus_tvd3_clk.common.hw,
1065 [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
1066 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1067 [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw,
1068 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
1069 [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw,
1070 [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
1071 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
1072 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
1073 [CLK_BUS_AC97] = &bus_ac97_clk.common.hw,
1074 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
1075 [CLK_BUS_IR0] = &bus_ir0_clk.common.hw,
1076 [CLK_BUS_IR1] = &bus_ir1_clk.common.hw,
1077 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
1078 [CLK_BUS_KEYPAD] = &bus_keypad_clk.common.hw,
1079 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
1080 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
1081 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
1082 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
1083 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
1084 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
1085 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
1086 [CLK_BUS_CAN] = &bus_can_clk.common.hw,
1087 [CLK_BUS_SCR] = &bus_scr_clk.common.hw,
1088 [CLK_BUS_PS20] = &bus_ps20_clk.common.hw,
1089 [CLK_BUS_PS21] = &bus_ps21_clk.common.hw,
1090 [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw,
1091 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
1092 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
1093 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
1094 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
1095 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
1096 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
1097 [CLK_BUS_UART6] = &bus_uart6_clk.common.hw,
1098 [CLK_BUS_UART7] = &bus_uart7_clk.common.hw,
1099 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
1100 [CLK_THS] = &ths_clk.common.hw,
1101 [CLK_NAND] = &nand_clk.common.hw,
1102 [CLK_MMC0] = &mmc0_clk.common.hw,
1103 [CLK_MMC1] = &mmc1_clk.common.hw,
1104 [CLK_MMC2] = &mmc2_clk.common.hw,
1105 [CLK_MMC3] = &mmc3_clk.common.hw,
1106 [CLK_TS] = &ts_clk.common.hw,
1107 [CLK_CE] = &ce_clk.common.hw,
1108 [CLK_SPI0] = &spi0_clk.common.hw,
1109 [CLK_SPI1] = &spi1_clk.common.hw,
1110 [CLK_SPI2] = &spi2_clk.common.hw,
1111 [CLK_SPI3] = &spi3_clk.common.hw,
1112 [CLK_I2S0] = &i2s0_clk.common.hw,
1113 [CLK_I2S1] = &i2s1_clk.common.hw,
1114 [CLK_I2S2] = &i2s2_clk.common.hw,
1115 [CLK_AC97] = &ac97_clk.common.hw,
1116 [CLK_SPDIF] = &spdif_clk.common.hw,
1117 [CLK_KEYPAD] = &keypad_clk.common.hw,
1118 [CLK_SATA] = &sata_clk.common.hw,
1119 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
1120 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
1121 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
1122 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1123 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1124 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
1125 [CLK_IR0] = &ir0_clk.common.hw,
1126 [CLK_IR1] = &ir1_clk.common.hw,
1127 [CLK_DRAM] = &dram_clk.common.hw,
1128 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
1129 [CLK_DRAM_CSI0] = &dram_csi0_clk.common.hw,
1130 [CLK_DRAM_CSI1] = &dram_csi1_clk.common.hw,
1131 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
1132 [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
1133 [CLK_DRAM_MP] = &dram_mp_clk.common.hw,
1134 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
1135 [CLK_DE] = &de_clk.common.hw,
1136 [CLK_MP] = &mp_clk.common.hw,
1137 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
1138 [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw,
1139 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
1140 [CLK_TCON_TV1] = &tcon_tv1_clk.common.hw,
1141 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
1142 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw,
1143 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
1144 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw,
1145 [CLK_VE] = &ve_clk.common.hw,
1146 [CLK_CODEC] = &codec_clk.common.hw,
1147 [CLK_AVS] = &avs_clk.common.hw,
1148 [CLK_HDMI] = &hdmi_clk.common.hw,
1149 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
1150 [CLK_MBUS] = &mbus_clk.common.hw,
1151 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
1152 [CLK_TVE0] = &tve0_clk.common.hw,
1153 [CLK_TVE1] = &tve1_clk.common.hw,
1154 [CLK_TVD0] = &tvd0_clk.common.hw,
1155 [CLK_TVD1] = &tvd1_clk.common.hw,
1156 [CLK_TVD2] = &tvd2_clk.common.hw,
1157 [CLK_TVD3] = &tvd3_clk.common.hw,
1158 [CLK_GPU] = &gpu_clk.common.hw,
1159 [CLK_OUTA] = &outa_clk.common.hw,
1160 [CLK_OUTB] = &outb_clk.common.hw,
1161 },
1162 .num = CLK_NUMBER,
1163 };
1164
1165 static struct ccu_reset_map sun8i_r40_ccu_resets[] = {
1166 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1167 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1168 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1169
1170 [RST_DRAM] = { 0x0f4, BIT(31) },
1171 [RST_MBUS] = { 0x0fc, BIT(31) },
1172
1173 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
1174 [RST_BUS_CE] = { 0x2c0, BIT(5) },
1175 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
1176 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
1177 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
1178 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
1179 [RST_BUS_MMC3] = { 0x2c0, BIT(11) },
1180 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
1181 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
1182 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
1183 [RST_BUS_TS] = { 0x2c0, BIT(18) },
1184 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
1185 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
1186 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
1187 [RST_BUS_SPI2] = { 0x2c0, BIT(22) },
1188 [RST_BUS_SPI3] = { 0x2c0, BIT(23) },
1189 [RST_BUS_SATA] = { 0x2c0, BIT(24) },
1190 [RST_BUS_OTG] = { 0x2c0, BIT(25) },
1191 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
1192 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
1193 [RST_BUS_EHCI2] = { 0x2c0, BIT(28) },
1194 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
1195 [RST_BUS_OHCI1] = { 0x2c0, BIT(30) },
1196 [RST_BUS_OHCI2] = { 0x2c0, BIT(31) },
1197
1198 [RST_BUS_VE] = { 0x2c4, BIT(0) },
1199 [RST_BUS_MP] = { 0x2c4, BIT(2) },
1200 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
1201 [RST_BUS_CSI0] = { 0x2c4, BIT(8) },
1202 [RST_BUS_CSI1] = { 0x2c4, BIT(9) },
1203 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
1204 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
1205 [RST_BUS_DE] = { 0x2c4, BIT(12) },
1206 [RST_BUS_TVE0] = { 0x2c4, BIT(13) },
1207 [RST_BUS_TVE1] = { 0x2c4, BIT(14) },
1208 [RST_BUS_TVE_TOP] = { 0x2c4, BIT(15) },
1209 [RST_BUS_GMAC] = { 0x2c4, BIT(17) },
1210 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
1211 [RST_BUS_TVD0] = { 0x2c4, BIT(21) },
1212 [RST_BUS_TVD1] = { 0x2c4, BIT(22) },
1213 [RST_BUS_TVD2] = { 0x2c4, BIT(23) },
1214 [RST_BUS_TVD3] = { 0x2c4, BIT(24) },
1215 [RST_BUS_TVD_TOP] = { 0x2c4, BIT(25) },
1216 [RST_BUS_TCON_LCD0] = { 0x2c4, BIT(26) },
1217 [RST_BUS_TCON_LCD1] = { 0x2c4, BIT(27) },
1218 [RST_BUS_TCON_TV0] = { 0x2c4, BIT(28) },
1219 [RST_BUS_TCON_TV1] = { 0x2c4, BIT(29) },
1220 [RST_BUS_TCON_TOP] = { 0x2c4, BIT(30) },
1221 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
1222
1223 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
1224
1225 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
1226 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
1227 [RST_BUS_AC97] = { 0x2d0, BIT(2) },
1228 [RST_BUS_IR0] = { 0x2d0, BIT(6) },
1229 [RST_BUS_IR1] = { 0x2d0, BIT(7) },
1230 [RST_BUS_THS] = { 0x2d0, BIT(8) },
1231 [RST_BUS_KEYPAD] = { 0x2d0, BIT(10) },
1232 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
1233 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
1234 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
1235
1236 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
1237 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
1238 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
1239 [RST_BUS_I2C3] = { 0x2d8, BIT(3) },
1240 [RST_BUS_CAN] = { 0x2d8, BIT(4) },
1241 [RST_BUS_SCR] = { 0x2d8, BIT(5) },
1242 [RST_BUS_PS20] = { 0x2d8, BIT(6) },
1243 [RST_BUS_PS21] = { 0x2d8, BIT(7) },
1244 [RST_BUS_I2C4] = { 0x2d8, BIT(15) },
1245 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
1246 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
1247 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
1248 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
1249 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
1250 [RST_BUS_UART5] = { 0x2d8, BIT(21) },
1251 [RST_BUS_UART6] = { 0x2d8, BIT(22) },
1252 [RST_BUS_UART7] = { 0x2d8, BIT(23) },
1253 };
1254
1255 static const struct sunxi_ccu_desc sun8i_r40_ccu_desc = {
1256 .ccu_clks = sun8i_r40_ccu_clks,
1257 .num_ccu_clks = ARRAY_SIZE(sun8i_r40_ccu_clks),
1258
1259 .hw_clks = &sun8i_r40_hw_clks,
1260
1261 .resets = sun8i_r40_ccu_resets,
1262 .num_resets = ARRAY_SIZE(sun8i_r40_ccu_resets),
1263 };
1264
1265 static struct ccu_pll_nb sun8i_r40_pll_cpu_nb = {
1266 .common = &pll_cpu_clk.common,
1267 /* copy from pll_cpu_clk */
1268 .enable = BIT(31),
1269 .lock = BIT(28),
1270 };
1271
1272 static struct ccu_mux_nb sun8i_r40_cpu_nb = {
1273 .common = &cpu_clk.common,
1274 .cm = &cpu_clk.mux,
1275 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
1276 .bypass_index = 1, /* index of 24 MHz oscillator */
1277 };
1278
1279 /*
1280 * Add a regmap for the GMAC driver (dwmac-sun8i) to access the
1281 * GMAC configuration register.
1282 * Only this register is allowed to be written, in order to
1283 * prevent overriding critical clock configuration.
1284 */
1285
1286 #define SUN8I_R40_GMAC_CFG_REG 0x164
sun8i_r40_ccu_regmap_accessible_reg(struct device * dev,unsigned int reg)1287 static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
1288 unsigned int reg)
1289 {
1290 if (reg == SUN8I_R40_GMAC_CFG_REG)
1291 return true;
1292 return false;
1293 }
1294
1295 static const struct regmap_config sun8i_r40_ccu_regmap_config = {
1296 .reg_bits = 32,
1297 .val_bits = 32,
1298 .reg_stride = 4,
1299 .max_register = 0x320, /* PLL_LOCK_CTRL_REG */
1300
1301 /* other devices have no business accessing other registers */
1302 .readable_reg = sun8i_r40_ccu_regmap_accessible_reg,
1303 .writeable_reg = sun8i_r40_ccu_regmap_accessible_reg,
1304 };
1305
1306 #define SUN8I_R40_SYS_32K_CLK_REG 0x310
1307 #define SUN8I_R40_SYS_32K_CLK_KEY (0x16AA << 16)
1308
sun8i_r40_ccu_probe(struct platform_device * pdev)1309 static int sun8i_r40_ccu_probe(struct platform_device *pdev)
1310 {
1311 struct regmap *regmap;
1312 void __iomem *reg;
1313 u32 val;
1314 int ret;
1315
1316 reg = devm_platform_ioremap_resource(pdev, 0);
1317 if (IS_ERR(reg))
1318 return PTR_ERR(reg);
1319
1320 /* Force the PLL-Audio-1x divider to 1 */
1321 val = readl(reg + SUN8I_R40_PLL_AUDIO_REG);
1322 val &= ~GENMASK(19, 16);
1323 writel(val | (0 << 16), reg + SUN8I_R40_PLL_AUDIO_REG);
1324
1325 /* Force PLL-MIPI to MIPI mode */
1326 val = readl(reg + SUN8I_R40_PLL_MIPI_REG);
1327 val &= ~BIT(16);
1328 writel(val, reg + SUN8I_R40_PLL_MIPI_REG);
1329
1330 /* Force OHCI 12M parent to 12M divided from 48M */
1331 val = readl(reg + SUN8I_R40_USB_CLK_REG);
1332 val &= ~GENMASK(25, 20);
1333 writel(val, reg + SUN8I_R40_USB_CLK_REG);
1334
1335 /*
1336 * Force SYS 32k (otherwise known as LOSC throughout the CCU)
1337 * clock parent to LOSC output from RTC module instead of the
1338 * CCU's internal RC oscillator divided output.
1339 */
1340 writel(SUN8I_R40_SYS_32K_CLK_KEY | BIT(8),
1341 reg + SUN8I_R40_SYS_32K_CLK_REG);
1342
1343 regmap = devm_regmap_init_mmio(&pdev->dev, reg,
1344 &sun8i_r40_ccu_regmap_config);
1345 if (IS_ERR(regmap))
1346 return PTR_ERR(regmap);
1347
1348 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_r40_ccu_desc);
1349 if (ret)
1350 return ret;
1351
1352 /* Gate then ungate PLL CPU after any rate changes */
1353 ccu_pll_notifier_register(&sun8i_r40_pll_cpu_nb);
1354
1355 /* Reparent CPU during PLL CPU rate changes */
1356 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1357 &sun8i_r40_cpu_nb);
1358
1359 return 0;
1360 }
1361
1362 static const struct of_device_id sun8i_r40_ccu_ids[] = {
1363 { .compatible = "allwinner,sun8i-r40-ccu" },
1364 { }
1365 };
1366 MODULE_DEVICE_TABLE(of, sun8i_r40_ccu_ids);
1367
1368 static struct platform_driver sun8i_r40_ccu_driver = {
1369 .probe = sun8i_r40_ccu_probe,
1370 .driver = {
1371 .name = "sun8i-r40-ccu",
1372 .suppress_bind_attrs = true,
1373 .of_match_table = sun8i_r40_ccu_ids,
1374 },
1375 };
1376 module_platform_driver(sun8i_r40_ccu_driver);
1377
1378 MODULE_IMPORT_NS(SUNXI_CCU);
1379 MODULE_DESCRIPTION("Support for the Allwinner R40 CCU");
1380 MODULE_LICENSE("GPL");
1381