Lines Matching +full:0 +full:x060
31 "osc24M", 0x000,
34 0, 2, /* M */
38 0);
52 #define SUN8I_V3S_PLL_AUDIO_REG 0x008
55 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
56 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
60 "osc24M", 0x008,
62 0, 5, /* M */
64 0x284, BIT(31),
70 "osc24M", 0x0010,
72 0, 4, /* M */
75 270000000, /* frac rate 0 */
79 0);
82 "osc24M", 0x0018,
84 0, 4, /* M */
87 270000000, /* frac rate 0 */
91 0);
94 "osc24M", 0x020,
97 0, 2, /* M */
100 0);
103 "osc24M", 0x028,
109 0);
112 "osc24M", 0x002c,
114 0, 4, /* M */
117 270000000, /* frac rate 0 */
121 0);
124 "osc24M", 0x044,
130 0);
133 "osc24M", 0x04c,
135 0, 2, /* M */
138 0);
143 0x050, 16, 2, CLK_IS_CRITICAL);
145 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
164 .reg = 0x054,
169 0),
174 { .val = 0, .div = 2 },
181 0x054, 8, 2, apb1_div_table, 0);
185 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
186 0, 5, /* M */
189 0);
197 .shift = 0,
204 .reg = 0x05c,
209 0),
214 0x060, BIT(5), 0);
216 0x060, BIT(6), 0);
218 0x060, BIT(8), 0);
220 0x060, BIT(9), 0);
222 0x060, BIT(10), 0);
224 0x060, BIT(14), 0);
226 0x060, BIT(17), 0);
228 0x060, BIT(19), 0);
230 0x060, BIT(20), 0);
232 0x060, BIT(24), 0);
234 0x060, BIT(26), 0);
236 0x060, BIT(29), 0);
239 0x064, BIT(0), 0);
241 0x064, BIT(4), 0);
243 0x064, BIT(8), 0);
245 0x064, BIT(12), 0);
248 0x068, BIT(0), 0);
250 0x068, BIT(5), 0);
252 0x068, BIT(12), 0);
255 0x06c, BIT(0), 0);
257 0x06c, BIT(1), 0);
259 0x06c, BIT(16), 0);
261 0x06c, BIT(17), 0);
263 0x06c, BIT(18), 0);
266 0x070, BIT(0), 0);
268 0x070, BIT(7), 0);
272 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
273 0, 4, /* M */
277 0);
280 0x088, 20, 3, 0);
282 0x088, 8, 3, 0);
284 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
285 0, 4, /* M */
289 0);
292 0x08c, 20, 3, 0);
294 0x08c, 8, 3, 0);
296 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
297 0, 4, /* M */
301 0);
304 0x090, 20, 3, 0);
306 0x090, 8, 3, 0);
310 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
311 0, 4, /* M */
315 0);
317 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
318 0, 4, /* M */
322 0);
327 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
330 0x0cc, BIT(8), 0);
332 0x0cc, BIT(16), 0);
337 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
340 0x100, BIT(0), 0);
342 0x100, BIT(1), 0);
344 0x100, BIT(17), 0);
346 0x100, BIT(18), 0);
350 0x104, 0, 4, 24, 2, BIT(31),
355 0x118, 0, 4, 24, 3, BIT(31), 0);
358 0x130, BIT(31), 0);
363 0x130, 0, 5, 8, 3, BIT(15), 0);
367 0x134, 16, 4, 24, 3, BIT(31), 0);
370 0x134, 0, 5, 8, 3, BIT(15), 0);
373 0x13c, 16, 3, BIT(31), 0);
376 0x140, BIT(31), CLK_SET_RATE_PARENT);
378 0x144, BIT(31), 0);
383 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
388 0x16c, 0, 3, 24, 2, BIT(31), 0);
483 1, 2, 0);
648 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
650 [RST_MBUS] = { 0x0fc, BIT(31) },
652 [RST_BUS_CE] = { 0x2c0, BIT(5) },
653 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
654 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
655 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
656 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
657 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
658 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
659 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
660 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
661 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
662 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
663 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
665 [RST_BUS_VE] = { 0x2c4, BIT(0) },
666 [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
667 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
668 [RST_BUS_DE] = { 0x2c4, BIT(12) },
669 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
671 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
673 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
675 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
676 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
677 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
678 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
679 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
683 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
685 [RST_MBUS] = { 0x0fc, BIT(31) },
687 [RST_BUS_CE] = { 0x2c0, BIT(5) },
688 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
689 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
690 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
691 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
692 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
693 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
694 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
695 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
696 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
697 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
698 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
700 [RST_BUS_VE] = { 0x2c4, BIT(0) },
701 [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
702 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
703 [RST_BUS_DE] = { 0x2c4, BIT(12) },
704 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
706 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
708 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
709 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
711 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
712 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
713 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
714 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
715 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
748 reg = devm_platform_ioremap_resource(pdev, 0); in sun8i_v3s_ccu_probe()