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/freebsd/sys/dev/sound/pci/
H A Dcs4281.h32 #define CS4281_PCI_ID 0x60051013
39 #define CS4281PCI_HISR 0x000
40 # define CS4281PCI_HISR_DMAI 0x00040000
41 # define CS4281PCI_HISR_DMA(x) (0x0100 << (x))
43 #define CS4281PCI_HICR 0x008
44 # define CS4281PCI_HICR_EOI 0x00000003
46 #define CS4281PCI_HIMR 0x00c
47 # define CS4281PCI_HIMR_DMAI 0x00040000
48 # define CS4281PCI_HIMR_DMA(x) (0x0100 << (x))
50 #define CS4281PCI_IIER 0x010
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dklondike.dts16 dcr-parent = <&{/cpus/cpu@0}>;
25 #size-cells = <0>;
27 cpu@0 {
30 reg = <0x00000000>;
44 reg = <0x00000000 0x20000000>; /* Filled in by U-Boot */
50 cell-index = <0>;
51 dcr-reg = <0x0c0 0x010>;
52 #address-cells = <0>;
53 #size-cells = <0>;
61 dcr-reg = <0x0d0 0x010>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhikey960-pinctrl.dtsi18 reg = <0x0 0xe896c000 0x0 0x1f0>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
25 &range 0 7 0
26 &range 8 116 0>;
30 0x008 MUX_M1 /* PMU1_SSI */
31 0x00c MUX_M1 /* PMU2_SSI */
32 0x010 MUX_M1 /* PMU_CLKOUT */
33 0x100 MUX_M1 /* PMU_HKADC_SSI */
[all …]
H A Dhikey970-pinctrl.dtsi16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
H A Dpoplar-pinctrl.dtsi21 0x000 MUX_M2
22 0x004 MUX_M2
23 0x008 MUX_M2
24 0x00c MUX_M2
25 0x010 MUX_M2
26 0x014 MUX_M2
27 0x018 MUX_M2
28 0x01c MUX_M2
29 0x024 MUX_M2
32 PINCTRL_PULLDOWN(0, 1, 0, 1)
[all …]
/freebsd/sys/dev/hyperv/netvsc/
H A Dndis.h30 #define NDIS_MEDIA_STATE_CONNECTED 0
37 #define NDIS_OFFLOAD_SET_NOCHG 0
42 #define NDIS_ENCAP_TYPE_NVGRE 0x00000001
44 #define NDIS_HASH_FUNCTION_MASK 0x000000FF /* see hash function */
45 #define NDIS_HASH_TYPE_MASK 0x00FFFF00 /* see hash type */
48 #define NDIS_HASH_FUNCTION_TOEPLITZ 0x00000001
51 #define NDIS_HASH_IPV4 0x00000100
52 #define NDIS_HASH_TCP_IPV4 0x00000200
53 #define NDIS_HASH_IPV6 0x00000400
54 #define NDIS_HASH_IPV6_EX 0x00000800
[all …]
/freebsd/contrib/nvi/common/
H A Dexf.h49 #define F_DEVSET 0x001 /* mdev/minode fields initialized. */
50 #define F_FIRSTMODIFY 0x002 /* File not yet modified. */
51 #define F_MODIFIED 0x004 /* File is currently dirty. */
52 #define F_MULTILOCK 0x008 /* Multiple processes running, lock. */
53 #define F_NOLOG 0x010 /* Logging turned off. */
54 #define F_RCV_NORM 0x020 /* Don't delete recovery files. */
55 #define F_RCV_ON 0x040 /* Recovery is possible. */
56 #define F_UNDO 0x080 /* No change since last undo. */
61 #define DBG_FATAL 0x001 /* If DNE, error message. */
62 #define DBG_NOCACHE 0x002 /* Ignore the front-end cache. */
[all …]
/freebsd/sys/dev/hwpmc/
H A Dpmu_dmc620_reg.h35 #define DMC620_SNAPSHOT_REQ 0x000 /* WO */
36 #define DMC620_SNAPSHOT_ACK 0x004 /* RO */
37 #define DMC620_OVERFLOW_STATUS_CLKDIV2 0x008 /* RW */
38 #define DMC620_OVERFLOW_STATUS_CLK 0x00C /* RW */
40 #define DMC620_COUNTER_MASK_LO 0x000 /* RW */
41 #define DMC620_COUNTER_MASK_HI 0x004 /* RW */
42 #define DMC620_COUNTER_MATCH_LO 0x008 /* RW */
43 #define DMC620_COUNTER_MATCH_HI 0x00C /* RW */
44 #define DMC620_COUNTER_CONTROL 0x010 /* RW */
45 #define DMC620_COUNTER_CONTROL_ENABLE (1 << 0)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dregs.h37 #define MT_HW_REV MT_HW_INFO(0x000)
38 #define MT_HW_CHIPID MT_HW_INFO(0x008)
39 #define MT_TOP_STRAP_STA MT_HW_INFO(0x010)
42 #define MT_TOP_OFF_RSV 0x1128
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
46 #define MT_TOP_MISC2_FW_STATE GENMASK(2, 0)
51 #define MT_MCU_BASE 0x2000
54 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
55 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
57 #define MT_PCIE_REMAP_BASE_1 0x40000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dnvidia,tegra30-smmu.txt15 reg = <0x7000f010 0x02c
16 0x7000f1f0 0x010
17 0x7000f228 0x05c>;
19 dma-window = <0 0x40000000>; /* IOVA start & length */
/freebsd/sys/dev/pms/RefTisa/tisa/sassata/common/
H A Dwcs.h33 0x011, // 00000 = 0 - PHY_RESET_START
34 0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY
35 0x009, // 0x002 = 2 -
36 0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE
37 0x010, // 0x004 = 4 -
38 0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED
39 0x01e, // 0x006 = 6 -
40 0x0ff, // 0x007 = 7 - JUMP
41 0x001, // 0x008 = 8 -
42 0x010, // 0x009 = 9 - SEND_ID_FRAME
[all …]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Dmellanox,i2c-mlxbf.txt27 reg = <0x02804000 0x800>,
28 <0x02801200 0x020>,
29 <0x02801260 0x020>;
36 reg = <0x02808800 0x600>,
37 <0x02808e00 0x020>,
38 <0x02808e20 0x020>,
39 <0x02808e40 0x010>;
H A Dmellanox,i2c-mlxbf.yaml61 reg = <0x02804000 0x800>,
62 <0x02801200 0x020>,
63 <0x02801260 0x020>;
71 reg = <0x02808800 0x600>,
72 <0x02808e00 0x020>,
73 <0x02808e20 0x020>,
74 <0x02808e40 0x010>;
/freebsd/sys/compat/linux/
H A Dlinux_event.h30 #define LINUX_EPOLLIN 0x001
31 #define LINUX_EPOLLPRI 0x002
32 #define LINUX_EPOLLOUT 0x004
33 #define LINUX_EPOLLRDNORM 0x040
34 #define LINUX_EPOLLRDBAND 0x080
35 #define LINUX_EPOLLWRNORM 0x100
36 #define LINUX_EPOLLWRBAND 0x200
37 #define LINUX_EPOLLMSG 0x400
38 #define LINUX_EPOLLERR 0x008
39 #define LINUX_EPOLLHUP 0x010
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dregs.h6 #define MT_HW_REV 0x1000
7 #define MT_HW_CHIPID 0x1008
8 #define MT_TOP_MISC2 0x1134
10 #define MT_MCU_BASE 0x2000
13 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500)
14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0)
17 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504)
18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0)
21 #define MT_HIF_BASE 0x4000
24 #define MT_INT_SOURCE_CSR MT_HIF(0x200)
[all …]
/freebsd/sys/crypto/ccp/
H A Dccp_hardware.h31 #define CMD_QUEUE_MASK_OFFSET 0x000
32 #define CMD_QUEUE_PRIO_OFFSET 0x004
33 #define CMD_REQID_CONFIG_OFFSET 0x008
34 #define TRNG_OUT_OFFSET 0x00C
35 #define CMD_CMD_TIMEOUT_OFFSET 0x010
36 #define LSB_PUBLIC_MASK_LO_OFFSET 0x018
37 #define LSB_PUBLIC_MASK_HI_OFFSET 0x01C
38 #define LSB_PRIVATE_MASK_LO_OFFSET 0x020
39 #define LSB_PRIVATE_MASK_HI_OFFSET 0x024
41 #define VERSION_REG 0x100
[all …]
/freebsd/sys/arm/freescale/
H A Dfsl_ocotpreg.h32 #define FSL_OCOTP_CTRL 0x000
33 #define FSL_OCOTP_CTRL_SET 0x004
34 #define FSL_OCOTP_CTRL_CLR 0x008
35 #define FSL_OCOTP_CTRL_TOG 0x00C
36 #define FSL_OCOTP_TIMING 0x010
37 #define FSL_OCOTP_DATA 0x020
38 #define FSL_OCOTP_READ_CTRL 0x030
39 #define FSL_OCOTP_READ_FUSE_DATA 0x040
40 #define FSL_OCOTP_SW_STICKY 0x050
41 #define FSL_OCOTP_SCS 0x060
[all …]
/freebsd/sys/nfs/
H A Dnfssvc.h41 #define NFSSVC_OLDNFSD 0x004
42 #define NFSSVC_ADDSOCK 0x008
43 #define NFSSVC_NFSD 0x010
48 #define NFSSVC_NOPUBLICFH 0x00000020
49 #define NFSSVC_STABLERESTART 0x00000040
50 #define NFSSVC_NFSDNFSD 0x00000080
51 #define NFSSVC_NFSDADDSOCK 0x00000100
52 #define NFSSVC_IDNAME 0x00000200
53 #define NFSSVC_GSSDDELETEALL 0x00000400
54 #define NFSSVC_GSSDADDPORT 0x00000800
[all …]
/freebsd/sys/dev/usb/controller/
H A Duhcireg.h36 #define PCI_UHCI_BASE_REG 0x20
39 #define PCI_USBREV 0x60 /* USB protocol revision */
40 #define PCI_USB_REV_MASK 0xff
41 #define PCI_USB_REV_PRE_1_0 0x00
42 #define PCI_USB_REV_1_0 0x10
43 #define PCI_USB_REV_1_1 0x11
44 #define PCI_LEGSUP 0xc0 /* Legacy Support register */
45 #define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */
46 #define PCI_CBIO 0x20 /* configuration base IO */
47 #define PCI_INTERFACE_UHCI 0x00
[all …]
/freebsd/sys/dev/virtio/mmio/
H A Dvirtio_mmio.h59 #define VIRTIO_MMIO_MAGIC_VALUE 0x000
60 #define VIRTIO_MMIO_VERSION 0x004
61 #define VIRTIO_MMIO_DEVICE_ID 0x008
62 #define VIRTIO_MMIO_VENDOR_ID 0x00c
63 #define VIRTIO_MMIO_HOST_FEATURES 0x010
64 #define VIRTIO_MMIO_HOST_FEATURES_SEL 0x014
65 #define VIRTIO_MMIO_GUEST_FEATURES 0x020
66 #define VIRTIO_MMIO_GUEST_FEATURES_SEL 0x024
67 #define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028 /* version 1 only */
68 #define VIRTIO_MMIO_QUEUE_SEL 0x030
[all …]
/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pcireg.h32 #define BHND_PCI_DMA32_TRANSLATION 0x40000000 /**< PCI DMA32 address translation (sbtopci2) */
35 #define BHND_PCIE_DMA32_TRANSLATION 0x80000000 /**< PCIe-Gen1 DMA32 address translation (sb2pcitr…
45 #define BHND_PCI_CTL 0x000 /**< PCI core control*/
46 #define BHND_PCI_ARB_CTL 0x010 /**< PCI arbiter control */
47 #define BHND_PCI_CLKRUN_CTL 0x014 /**< PCI clckrun control (>= rev11) */
48 #define BHND_PCI_INTR_STATUS 0x020 /**< Interrupt status */
49 #define BHND_PCI_INTR_MASK 0x024 /**< Interrupt mask */
50 #define BHND_PCI_SBTOPCI_MBOX 0x028 /**< Sonics to PCI mailbox */
51 #define BHND_PCI_BCAST_ADDR 0x050 /**< Sonics broadcast address (pci) */
52 #define BHND_PCI_BCAST_DATA 0x054 /**< Sonics broadcast data (pci) */
[all …]
/freebsd/sys/powerpc/powermac/
H A Ddbdmavar.h67 DBDMA registers are found at 0x8000 + n*0x100 in the macio register space,
71 0x000 Channel Control 4
72 0x004 Channel Status 4
73 0x00C Command Phys Addr 4
74 0x010 Interrupt Select 4
75 0x014 Branch Select 4
76 0x018 Wait Select 4
79 #define CHAN_CONTROL_REG 0x00
80 #define CHAN_STATUS_REG 0x04
81 #define CHAN_CMDPTR_HI 0x08
[all …]
/freebsd/contrib/ntp/include/
H A Dntp_tty.h44 #define TCIFLUSH 0
83 #define LDISC_STD 0x000 /* standard */
84 #define LDISC_CLK 0x001 /* depredated tty_clk \n */
85 #define LDISC_CLKPPS 0x002 /* depredated tty_clk \377 */
86 #define LDISC_ACTS 0x004 /* depredated tty_clk #* */
87 #define LDISC_CHU 0x008 /* depredated */
88 #define LDISC_PPS 0x010 /* depredated */
89 #define LDISC_RAW 0x020 /* raw binary */
90 #define LDISC_ECHO 0x04
[all...]
/freebsd/sys/dev/qlxgbe/
H A Dql_tmplt.h57 #define Q8_CE_OPCODE_NOP 0x000
58 #define Q8_CE_OPCODE_WRITE_LIST 0x001
59 #define Q8_CE_OPCODE_READ_WRITE_LIST 0x002
60 #define Q8_CE_OPCODE_POLL_LIST 0x004
61 #define Q8_CE_OPCODE_POLL_WRITE_LIST 0x008
62 #define Q8_CE_OPCODE_READ_MODIFY_WRITE 0x010
63 #define Q8_CE_OPCODE_SEQ_PAUSE 0x020
64 #define Q8_CE_OPCODE_SEQ_END 0x040
65 #define Q8_CE_OPCODE_TMPLT_END 0x080
66 #define Q8_CE_OPCODE_POLL_RD_LIST 0x100

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