Lines Matching +full:0 +full:x010
18 reg = <0x0 0xe896c000 0x0 0x1f0>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
25 &range 0 7 0
26 &range 8 116 0>;
30 0x008 MUX_M1 /* PMU1_SSI */
31 0x00c MUX_M1 /* PMU2_SSI */
32 0x010 MUX_M1 /* PMU_CLKOUT */
33 0x100 MUX_M1 /* PMU_HKADC_SSI */
39 0x044 MUX_M0 /* CSI0_PWD_N */
45 0x04c MUX_M0 /* CSI1_PWD_N */
51 0x058 MUX_M1 /* ISP_CLK0 */
52 0x064 MUX_M1 /* ISP_SCL0 */
53 0x068 MUX_M1 /* ISP_SDA0 */
59 0x05c MUX_M1 /* ISP_CLK1 */
60 0x06c MUX_M1 /* ISP_SCL1 */
61 0x070 MUX_M1 /* ISP_SDA1 */
67 0x080 MUX_M0 /* GPIO_034 */
73 0x02c MUX_M1 /* I2C3_SCL */
74 0x030 MUX_M1 /* I2C3_SDA */
80 0x090 MUX_M1 /* I2C4_SCL */
81 0x094 MUX_M1 /* I2C4_SDA */
87 0x15c MUX_M1 /* PCIE_PERST_N */
93 0x11c MUX_M0 /* GPIO_073 */
94 0x120 MUX_M0 /* GPIO_074 */
100 0x0cc MUX_M2 /* UART0_RXD */
101 0x0d0 MUX_M2 /* UART0_TXD */
107 0x0b0 MUX_M2 /* UART1_CTS_N */
108 0x0b4 MUX_M2 /* UART1_RTS_N */
109 0x0a8 MUX_M2 /* UART1_RXD */
110 0x0ac MUX_M2 /* UART1_TXD */
116 0x0bc MUX_M2 /* UART2_CTS_N */
117 0x0c0 MUX_M2 /* UART2_RTS_N */
118 0x0c8 MUX_M2 /* UART2_RXD */
119 0x0c4 MUX_M2 /* UART2_TXD */
125 0x0dc MUX_M1 /* UART3_CTS_N */
126 0x0e0 MUX_M1 /* UART3_RTS_N */
127 0x0e4 MUX_M1 /* UART3_RXD */
128 0x0e8 MUX_M1 /* UART3_TXD */
134 0x0ec MUX_M1 /* UART4_CTS_N */
135 0x0f0 MUX_M1 /* UART4_RTS_N */
136 0x0f4 MUX_M1 /* UART4_RXD */
137 0x0f8 MUX_M1 /* UART4_TXD */
143 0x0c4 MUX_M3 /* UART5_CTS_N */
144 0x0c8 MUX_M3 /* UART5_RTS_N */
145 0x0bc MUX_M3 /* UART5_RXD */
146 0x0c0 MUX_M3 /* UART5_TXD */
152 0x0cc MUX_M1 /* UART6_CTS_N */
153 0x0d0 MUX_M1 /* UART6_RTS_N */
154 0x0d4 MUX_M1 /* UART6_RXD */
155 0x0d8 MUX_M1 /* UART6_TXD */
161 0x0c8 MUX_M0 /* CAM0_RST */
167 0x124 MUX_M0 /* CAM1_RST */
175 reg = <0x0 0xff37e000 0x0 0x18>;
176 #gpio-range-cells = <0x3>;
178 pinctrl-single,register-width = <0x20>;
179 pinctrl-single,function-mask = <0x7>;
181 pinctrl-single,gpio-range = <&range 0 6 0>;
185 0x000 MUX_M1 /* SD_CLK */
186 0x004 MUX_M1 /* SD_CMD */
187 0x008 MUX_M1 /* SD_DATA0 */
188 0x00c MUX_M1 /* SD_DATA1 */
189 0x010 MUX_M1 /* SD_DATA2 */
190 0x014 MUX_M1 /* SD_DATA3 */
198 reg = <0x0 0xff3b6000 0x0 0x30>;
200 #gpio-range-cells = <0x3>;
201 pinctrl-single,register-width = <0x20>;
202 pinctrl-single,function-mask = <0x7>;
204 pinctrl-single,gpio-range = <&range 0 12 0>;
208 0x000 MUX_M1 /* UFS_REF_CLK */
209 0x004 MUX_M1 /* UFS_RST_N */
215 0x008 MUX_M1 /* SPI3_CLK */
216 0x00c MUX_M1 /* SPI3_DI */
217 0x010 MUX_M1 /* SPI3_DO */
218 0x014 MUX_M1 /* SPI3_CS0_N */
226 reg = <0x0 0xff3fd000 0x0 0x18>;
228 #gpio-range-cells = <0x3>;
229 pinctrl-single,register-width = <0x20>;
230 pinctrl-single,function-mask = <0x7>;
232 pinctrl-single,gpio-range = <&range 0 6 0>;
236 0x000 MUX_M1 /* SDIO_CLK */
237 0x004 MUX_M1 /* SDIO_CMD */
238 0x008 MUX_M1 /* SDIO_DATA0 */
239 0x00c MUX_M1 /* SDIO_DATA1 */
240 0x010 MUX_M1 /* SDIO_DATA2 */
241 0x014 MUX_M1 /* SDIO_DATA3 */
249 reg = <0x0 0xfff11000 0x0 0xa8>;
251 #gpio-range-cells = <0x3>;
252 pinctrl-single,register-width = <0x20>;
253 pinctrl-single,function-mask = <0x7>;
255 pinctrl-single,gpio-range = <&range 0 42 0>;
259 0x044 MUX_M1 /* I2S2_DI */
260 0x048 MUX_M1 /* I2S2_DO */
261 0x04c MUX_M1 /* I2S2_XCLK */
262 0x050 MUX_M1 /* I2S2_XFS */
268 0x02c MUX_M1 /* SLIMBUS_CLK */
269 0x030 MUX_M1 /* SLIMBUS_DATA */
275 0x014 MUX_M1 /* I2C0_SCL */
276 0x018 MUX_M1 /* I2C0_SDA */
282 0x01c MUX_M1 /* I2C1_SCL */
283 0x020 MUX_M1 /* I2C1_SDA */
289 0x024 MUX_M3 /* I2C7_SCL */
290 0x028 MUX_M3 /* I2C7_SDA */
296 0x084 MUX_M1 /* PCIE_CLKREQ_N */
297 0x088 MUX_M1 /* PCIE_WAKE_N */
303 0x08c MUX_M1 /* SPI2_CLK */
304 0x090 MUX_M1 /* SPI2_DI */
305 0x094 MUX_M1 /* SPI2_DO */
306 0x098 MUX_M1 /* SPI2_CS0_N */
312 0x034 MUX_M1 /* I2S0_DI */
313 0x038 MUX_M1 /* I2S0_DO */
314 0x03c MUX_M1 /* I2S0_XCLK */
315 0x040 MUX_M1 /* I2S0_XFS */
322 reg = <0x0 0xe896c800 0x0 0x200>;
324 pinctrl-single,register-width = <0x20>;
328 0x010 0x0 /* PMU1_SSI */
329 0x014 0x0 /* PMU2_SSI */
330 0x018 0x0 /* PMU_CLKOUT */
331 0x10c 0x0 /* PMU_HKADC_SSI */
352 0x038 0x0 /* I2C3_SCL */
353 0x03c 0x0 /* I2C3_SDA */
374 0x050 0x0 /* CSI0_PWD_N */
395 0x058 0x0 /* CSI1_PWD_N */
416 0x064 0x0 /* ISP_CLK0 */
417 0x070 0x0 /* ISP_SCL0 */
418 0x074 0x0 /* ISP_SDA0 */
438 0x068 0x0 /* ISP_CLK1 */
439 0x078 0x0 /* ISP_SCL1 */
440 0x07c 0x0 /* ISP_SDA1 */
461 0x08c 0x0 /* GPIO_034 */
482 0x0b4 0x0 /* UART1_RXD */
483 0x0b8 0x0 /* UART1_TXD */
484 0x0bc 0x0 /* UART1_CTS_N */
485 0x0c0 0x0 /* UART1_RTS_N */
506 0x0c8 0x0 /* UART2_CTS_N */
507 0x0cc 0x0 /* UART2_RTS_N */
508 0x0d0 0x0 /* UART2_TXD */
509 0x0d4 0x0 /* UART2_RXD */
530 0x0c8 0x0 /* UART5_RXD */
531 0x0cc 0x0 /* UART5_TXD */
532 0x0d0 0x0 /* UART5_CTS_N */
533 0x0d4 0x0 /* UART5_RTS_N */
554 0x0d4 0x0 /* CAM0_RST */
575 0x0d8 0x0 /* UART0_RXD */
576 0x0dc 0x0 /* UART0_TXD */
597 0x0d8 0x0 /* UART6_CTS_N */
598 0x0dc 0x0 /* UART6_RTS_N */
599 0x0e0 0x0 /* UART6_RXD */
600 0x0e4 0x0 /* UART6_TXD */
621 0x0e8 0x0 /* UART3_CTS_N */
622 0x0ec 0x0 /* UART3_RTS_N */
623 0x0f0 0x0 /* UART3_RXD */
624 0x0f4 0x0 /* UART3_TXD */
645 0x0f8 0x0 /* UART4_CTS_N */
646 0x0fc 0x0 /* UART4_RTS_N */
647 0x100 0x0 /* UART4_RXD */
648 0x104 0x0 /* UART4_TXD */
669 0x130 0x0 /* CAM1_RST */
691 reg = <0x0 0xff3b6800 0x0 0x18>;
693 pinctrl-single,register-width = <0x20>;
697 0x000 0x0 /* UFS_REF_CLK */
698 0x004 0x0 /* UFS_RST_N */
719 0x008 0x0 /* SPI3_CLK */
720 0x00c 0x0 /* SPI3_DI */
721 0x010 0x0 /* SPI3_DO */
722 0x014 0x0 /* SPI3_CS0_N */
744 reg = <0x0 0xff3fd800 0x0 0x18>;
746 pinctrl-single,register-width = <0x20>;
750 0x000 0x0 /* SDIO_CLK */
771 0x004 0x0 /* SDIO_CMD */
772 0x008 0x0 /* SDIO_DATA0 */
773 0x00c 0x0 /* SDIO_DATA1 */
774 0x010 0x0 /* SDIO_DATA2 */
775 0x014 0x0 /* SDIO_DATA3 */
797 reg = <0x0 0xff37e800 0x0 0x18>;
799 pinctrl-single,register-width = <0x20>;
803 0x000 0x0 /* SD_CLK */
825 0x004 0x0 /* SD_CMD */
826 0x008 0x0 /* SD_DATA0 */
827 0x00c 0x0 /* SD_DATA1 */
828 0x010 0x0 /* SD_DATA2 */
829 0x014 0x0 /* SD_DATA3 */
852 reg = <0x0 0xfff11800 0x0 0xbc>;
854 pinctrl-single,register-width = <0x20>;
858 0x01c 0x0 /* I2C0_SCL */
859 0x020 0x0 /* I2C0_SDA */
880 0x024 0x0 /* I2C1_SCL */
881 0x028 0x0 /* I2C1_SDA */
902 0x02c 0x0 /* I2C7_SCL */
903 0x030 0x0 /* I2C7_SDA */
924 0x034 0x0 /* SLIMBUS_CLK */
925 0x038 0x0 /* SLIMBUS_DATA */
946 0x040 0x0 /* I2S0_DI */
947 0x044 0x0 /* I2S0_DO */
948 0x048 0x0 /* I2S0_XCLK */
949 0x04c 0x0 /* I2S0_XFS */
970 0x050 0x0 /* I2S2_DI */
971 0x054 0x0 /* I2S2_DO */
972 0x058 0x0 /* I2S2_XCLK */
973 0x05c 0x0 /* I2S2_XFS */
994 0x094 0x0 /* PCIE_CLKREQ_N */
995 0x098 0x0 /* PCIE_WAKE_N */
1016 0x09c 0x0 /* SPI2_CLK */
1017 0x0a0 0x0 /* SPI2_DI */
1018 0x0a4 0x0 /* SPI2_DO */
1019 0x0a8 0x0 /* SPI2_CS0_N */
1040 0x0ac 0x0 /* GPIO_219 */