Lines Matching +full:0 +full:x010

67    DBDMA registers are found at 0x8000 + n*0x100 in the macio register space,
71    0x000 			Channel Control 	4
72    0x004 			Channel Status		4
73    0x00C			Command Phys Addr	4
74    0x010			Interrupt Select	4
75    0x014			Branch Select		4
76    0x018			Wait Select		4
79 #define CHAN_CONTROL_REG	0x00
80 #define	CHAN_STATUS_REG		0x04
81 #define CHAN_CMDPTR_HI		0x08
82 #define CHAN_CMDPTR		0x0C
83 #define	CHAN_INTR_SELECT	0x10
84 #define CHAN_BRANCH_SELECT	0x14
85 #define CHAN_WAIT_SELECT	0x18
92 /* Status bits 0-7 are device dependent status bits */