Lines Matching +full:0 +full:x010

36 #define	PCI_UHCI_BASE_REG	0x20
39 #define	PCI_USBREV		0x60	/* USB protocol revision */
40 #define	PCI_USB_REV_MASK		0xff
41 #define	PCI_USB_REV_PRE_1_0	0x00
42 #define	PCI_USB_REV_1_0		0x10
43 #define	PCI_USB_REV_1_1		0x11
44 #define	PCI_LEGSUP		0xc0	/* Legacy Support register */
45 #define	PCI_LEGSUP_USBPIRQDEN	0x2000	/* USB PIRQ D Enable */
46 #define	PCI_CBIO		0x20	/* configuration base IO */
47 #define	PCI_INTERFACE_UHCI	0x00
50 #define	UHCI_CMD		0x00
51 #define	UHCI_CMD_RS		0x0001
52 #define	UHCI_CMD_HCRESET	0x0002
53 #define	UHCI_CMD_GRESET		0x0004
54 #define	UHCI_CMD_EGSM		0x0008
55 #define	UHCI_CMD_FGR		0x0010
56 #define	UHCI_CMD_SWDBG		0x0020
57 #define	UHCI_CMD_CF		0x0040
58 #define	UHCI_CMD_MAXP		0x0080
59 #define	UHCI_STS		0x02
60 #define	UHCI_STS_USBINT		0x0001
61 #define	UHCI_STS_USBEI		0x0002
62 #define	UHCI_STS_RD		0x0004
63 #define	UHCI_STS_HSE		0x0008
64 #define	UHCI_STS_HCPE		0x0010
65 #define	UHCI_STS_HCH		0x0020
66 #define	UHCI_STS_ALLINTRS	0x003f
67 #define	UHCI_INTR		0x04
68 #define	UHCI_INTR_TOCRCIE	0x0001
69 #define	UHCI_INTR_RIE		0x0002
70 #define	UHCI_INTR_IOCE		0x0004
71 #define	UHCI_INTR_SPIE		0x0008
72 #define	UHCI_FRNUM		0x06
73 #define	UHCI_FRNUM_MASK		0x03ff
74 #define	UHCI_FLBASEADDR		0x08
75 #define	UHCI_SOF		0x0c
76 #define	UHCI_SOF_MASK		0x7f
77 #define	UHCI_PORTSC1      	0x010
78 #define	UHCI_PORTSC2      	0x012
79 #define	UHCI_PORTSC_CCS		0x0001
80 #define	UHCI_PORTSC_CSC		0x0002
81 #define	UHCI_PORTSC_PE		0x0004
82 #define	UHCI_PORTSC_POEDC	0x0008
83 #define	UHCI_PORTSC_LS		0x0030
85 #define	UHCI_PORTSC_RD		0x0040
86 #define	UHCI_PORTSC_LSDA	0x0100
87 #define	UHCI_PORTSC_PR		0x0200
88 #define	UHCI_PORTSC_OCI		0x0400
89 #define	UHCI_PORTSC_OCIC	0x0800
90 #define	UHCI_PORTSC_SUSP	0x1000